Searched refs:read (Results 1 - 25 of 1133) sorted by path

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/drivers/acpi/
H A Dac.c110 .read = seq_read,
184 seq_puts(seq, "ERROR: Unable to read AC Adapter state\n");
H A Dbattery.c841 seq_printf(seq, "ERROR: Unable to read battery info\n");
887 seq_printf(seq, "ERROR: Unable to read battery state\n");
911 seq_printf(seq, "ERROR: Unable to read battery alarm\n");
983 .read = seq_read, \
996 .read = seq_read, \
H A Dbutton.c141 .read = seq_read,
H A Dec_sys.c56 return *off - init_off; /* partial read */
103 .read = acpi_ec_read_io,
H A Dproc.c141 .read = seq_read,
H A Dsysfs.c311 table_attr->attr.read = acpi_table_show;
/drivers/acpi/apei/
H A Deinj.c617 .read = seq_read,
H A Derst-dbg.c119 * should be zero indicating the read operation is EOF.
127 /* The record may be cleared by others, try read next record */
211 .read = erst_dbg_read,
H A Derst.c948 .read = erst_reader,
1023 /* The record may be cleared by others, try read next record */
/drivers/ata/
H A Dpata_mpc52xx.c448 unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE), si; local
452 if (read)
466 if (read) {
505 unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE); local
517 if (read) {
/drivers/atm/
H A Dambassador.h395 __be32 read; member in struct:__anon99::__anon100::__anon108
H A Dfore200e.c254 if ((ok = (fore200e->bus->read(addr) == val)))
262 fore200e->bus->read(addr), val);
747 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY;
753 return fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_INTR_REQ;
758 u32 hcr = fore200e->bus->read(fore200e->regs.sba.hcr) & SBA200E_HCR_STICKY;
2180 fore200e->bus->read(&fore200e->cp_queues->cp_bsq[ scheme ][ magn ]);
2235 cp_entry = fore200e->virt_base + fore200e->bus->read(&fore200e->cp_queues->cp_rxq);
2294 cp_entry = fore200e->virt_base + fore200e->bus->read(&fore200e->cp_queues->cp_txq);
2345 cp_entry = fore200e->virt_base + fore200e->bus->read(&fore200e->cp_queues->cp_cmdq);
2452 c = (int) fore200e->bus->read(
[all...]
H A Dfore200e.h732 u32 recv; /* read register */
805 u32 (*read)(volatile u32 __iomem *); member in struct:fore200e_bus
912 #define PCA200E_HCR_RESET (1<<0) /* read / write */
913 #define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */
914 #define PCA200E_HCR_I960FAIL (1<<2) /* read */
916 #define PCA200E_HCR_HOLD_ACK (1<<3) /* read */
918 #define PCA200E_HCR_OUTFULL (1<<4) /* read */
920 #define PCA200E_HCR_ESPHOLD (1<<5) /* read */
921 #define PCA200E_HCR_INFULL (1<<6) /* read */
922 #define PCA200E_HCR_TESTMODE (1<<7) /* read */
[all...]
H A Diphase.c530 TstSchedTbl = (u16*)(SchedTbl+testSlot); //set index and read in value
554 // set table index and read in value
746 * Now read the rest of the bits, the next bit read is D14, then D13,
1116 /* update the read pointer - maybe we shud do this in the end*/
1281 /* free all the dles done, that is just update our own dle read pointer
1286 dle = iadev->rx_dle_q.read;
1356 iadev->rx_dle_q.read = dle;
1440 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1611 /* to clear the interrupt status register - read i
[all...]
H A Diphase.h294 struct dle *read; member in struct:dle_q
669 ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
673 ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
697 ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */
699 ffreg_t abrwq_rptr; /* ABR wait queue read pointer */
701 ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */
722 rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */
723 rreg_t err_cntr; /* Error Counter (cleared on read) */
727 rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */
728 rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */
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H A Dlanai.c105 * We normally read the onboard EEPROM in order to discover our MAC
396 Reset_Reg = 0x00, /* Reset; read for chip type; bits: */
421 #define READMODE_PLAIN (0) /* Plain memory read */
422 #define READMODE_LINE (2) /* Memory read line */
423 #define READMODE_MULTIPLE (3) /* Memory read multiple */
563 "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n",
779 int read, write, lastread = -1; local
799 read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
800 if (read == write && /* Is TX buffer empty? */
805 if (read !
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/drivers/base/
H A Ddevcoredump.c34 /* if data isn't read by userspace after 5 minutes then delete it */
42 ssize_t (*read)(char *buffer, loff_t offset, size_t count, member in struct:devcd_entry
90 return devcd->read(buffer, offset, count, devcd->data, devcd->datalen);
108 .read = devcd_data_read,
171 * dev_coredumpm - create device coredump with read/free methods
173 * @owner: the module that contains the read/free functions, use %THIS_MODULE
174 * @data: data cookie for the @read/@free functions
177 * @read: function to read from the given buffer
181 * been read ye
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H A Dfirmware_class.c836 .read = firmware_data_read,
/drivers/base/power/
H A Ddomain.c2352 .read = seq_read,
H A Dwakeup.c941 .read = seq_read,
/drivers/base/regmap/
H A Dinternal.h154 int (*read)(struct regmap *map, unsigned int reg, unsigned int *value); member in struct:regcache_ops
H A Dregcache-flat.c70 .read = regcache_flat_read,
H A Dregcache-lzo.c375 .read = regcache_lzo_read,
H A Dregcache-rbtree.c188 .read = seq_read,
334 /* If there is a read table then use it to guess at an allocation */
532 .read = regcache_rbtree_read,
H A Dregcache.c43 /* Bypass the cache access till data read from HW*/
128 if (!map->cache_ops->read ||
213 ret = map->cache_ops->read(map, reg, value);

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