Searched refs:reg (Results 1 - 25 of 2563) sorted by path

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/drivers/acpi/
H A Dacpi_lpss.c382 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) argument
384 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
388 unsigned int reg)
390 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
393 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) argument
414 *val = __lpss_reg_read(pdata, reg);
425 unsigned int reg; local
428 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
429 ret = lpss_reg_read(dev, reg, &ltr_value);
516 dev_dbg(dev, "saving 0x%08x from LPSS reg a
387 __lpss_reg_write(u32 val, struct lpss_private_data *pdata, unsigned int reg) argument
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H A Dosl.c1049 acpi_os_read_pci_configuration(struct acpi_pci_id * pci_id, u32 reg, argument
1074 reg, size, &value32);
1081 acpi_os_write_pci_configuration(struct acpi_pci_id * pci_id, u32 reg, argument
1102 reg, size, value);
H A Dprocessor_idle.c380 struct acpi_power_register *reg; local
397 reg = (struct acpi_power_register *)obj->buffer.pointer;
399 if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
400 (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
416 cx.address = reg->address;
420 if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
422 (pr->id, &cx, reg) == 0) {
/drivers/acpi/acpica/
H A Dachware.h66 acpi_hw_validate_register(struct acpi_generic_address *reg,
69 acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg);
71 acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg);
H A Dacmacros.h279 #define ACPI_REGISTER_INSERT_VALUE(reg, pos, mask, val) \
280 reg = (reg & (~(mask))) | ACPI_REGISTER_PREPARE_BITS(val, pos, mask)
H A Dhwregs.c70 * PARAMETERS: reg - GAS register structure
83 acpi_hw_validate_register(struct acpi_generic_address *reg, argument
89 if (!reg) {
98 ACPI_MOVE_64_TO_64(address, &reg->address);
105 if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
106 (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) {
108 "Unsupported address space: 0x%X", reg->space_id));
114 if ((reg->bit_width != 8) &&
115 (reg->bit_width != 16) &&
116 (reg
155 acpi_hw_read(u32 *value, struct acpi_generic_address *reg) argument
212 acpi_hw_write(u32 value, struct acpi_generic_address *reg) argument
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H A Dhwxface.c114 * reg - GAS register structure
127 acpi_status acpi_read(u64 *return_value, struct acpi_generic_address *reg)
143 status = acpi_hw_validate_register(reg, 64, &address);
152 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
155 reg->bit_width);
164 width = reg->bit_width;
175 if (reg->bit_width == 64) {
194 ACPI_FORMAT_UINT64(*return_value), reg->bit_width,
196 acpi_ut_get_region_name(reg->space_id)));
208 * reg
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/drivers/acpi/apei/
H A Dapei-base.c561 static int apei_check_gar(struct acpi_generic_address *reg, u64 *paddr, argument
566 bit_width = reg->bit_width;
567 bit_offset = reg->bit_offset;
568 access_size_code = reg->access_width;
569 space_id = reg->space_id;
570 *paddr = get_unaligned(&reg->address);
616 int apei_map_generic_address(struct acpi_generic_address *reg) argument
622 rc = apei_check_gar(reg, &address, &access_bit_width);
625 return acpi_os_map_generic_address(reg);
630 int apei_read(u64 *val, struct acpi_generic_address *reg) argument
664 apei_write(u64 val, struct acpi_generic_address *reg) argument
700 struct acpi_generic_address *reg = &entry->register_region; local
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H A Dapei-internal.h72 int apei_map_generic_address(struct acpi_generic_address *reg);
74 static inline void apei_unmap_generic_address(struct acpi_generic_address *reg) argument
76 acpi_os_unmap_generic_address(reg);
79 int apei_read(u64 *val, struct acpi_generic_address *reg);
80 int apei_write(u64 val, struct acpi_generic_address *reg);
/drivers/ata/
H A Dahci_sunxi.c53 static void sunxi_clrbits(void __iomem *reg, u32 clr_val) argument
57 reg_val = readl(reg);
59 writel(reg_val, reg);
62 static void sunxi_setbits(void __iomem *reg, u32 set_val) argument
66 reg_val = readl(reg);
68 writel(reg_val, reg);
71 static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val) argument
75 reg_val = readl(reg);
78 writel(reg_val, reg);
81 static u32 sunxi_getbits(void __iomem *reg, u argument
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H A Data_piix.c792 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) argument
797 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
802 unsigned int reg, u32 *val)
806 if (reg >= ARRAY_SIZE(piix_sidx_map))
809 piix_sidpr_sel(link, reg);
815 unsigned int reg, u32 val)
819 if (reg >= ARRAY_SIZE(piix_sidx_map))
822 piix_sidpr_sel(link, reg);
801 piix_sidpr_scr_read(struct ata_link *link, unsigned int reg, u32 *val) argument
814 piix_sidpr_scr_write(struct ata_link *link, unsigned int reg, u32 val) argument
H A Dlibata-core.c5117 * @reg: SCR to read
5120 * Read SCR register @reg of @link into *@val. This function is
5130 int sata_scr_read(struct ata_link *link, int reg, u32 *val) argument
5134 return link->ap->ops->scr_read(link, reg, val);
5138 return sata_pmp_scr_read(link, reg, val);
5144 * @reg: SCR to write
5147 * Write @val to SCR register @reg of @link. This function is
5157 int sata_scr_write(struct ata_link *link, int reg, u32 val) argument
5161 return link->ap->ops->scr_write(link, reg, val);
5165 return sata_pmp_scr_write(link, reg, va
5183 sata_scr_write_flush(struct ata_link *link, int reg, u32 val) argument
6725 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, u32 val, unsigned long interval, unsigned long timeout) argument
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H A Dlibata-pmp.c28 * @reg: register to read
39 static unsigned int sata_pmp_read(struct ata_link *link, int reg, u32 *r_val) argument
50 tf.feature = reg;
65 * @reg: register to write
76 static unsigned int sata_pmp_write(struct ata_link *link, int reg, u32 val) argument
86 tf.feature = reg;
130 * @reg: PSCR to read
133 * Read PSCR @reg into @r_val for @link, to be called from
142 int sata_pmp_scr_read(struct ata_link *link, int reg, u32 *r_val) argument
146 if (reg > SATA_PMP_PSCR_CONTRO
173 sata_pmp_scr_write(struct ata_link *link, int reg, u32 val) argument
230 int reg = gscr_to_read[i]; local
297 u32 reg; local
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H A Dlibata.h188 extern int sata_pmp_scr_read(struct ata_link *link, int reg, u32 *val);
189 extern int sata_pmp_scr_write(struct ata_link *link, int reg, u32 val);
194 static inline int sata_pmp_scr_read(struct ata_link *link, int reg, u32 *val) argument
199 static inline int sata_pmp_scr_write(struct ata_link *link, int reg, u32 val) argument
H A Dpata_artop.c321 u8 reg; local
327 pci_read_config_byte(pdev, 0x49, &reg);
328 pci_write_config_byte(pdev, 0x49, reg & ~0x30);
333 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
334 if (reg <= 0x80)
338 pci_read_config_byte(pdev, 0x4a, &reg);
339 pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
H A Dpata_cmd640.c58 u8 reg; local
100 pci_read_config_byte(pdev, arttim, &reg);
101 reg &= 0x3F;
102 reg |= t.setup;
103 pci_write_config_byte(pdev, arttim, reg);
111 pci_read_config_byte(pdev, ARTIM23, &reg);
112 reg &= 0x3F;
113 reg |= t.setup;
114 pci_write_config_byte(pdev, ARTIM23, reg);
H A Dpata_cmd64x.c100 u8 reg; local
159 pci_read_config_byte(pdev, arttim, &reg);
160 reg &= 0x3F;
161 reg |= t.setup;
162 pci_write_config_byte(pdev, arttim, reg);
430 u8 reg; local
474 pci_read_config_byte(pdev, CNTRL, &reg);
477 if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
482 if (port_ok && !(reg & CNTRL_CH1)) {
H A Dpata_cs5530.c89 u8 reg; local
124 reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
125 reg |= (1 << (5 + adev->devno));
126 iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
233 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
242 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
257 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
H A Dpata_cs5535.c105 u32 reg, dummy; local
125 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
126 wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
144 u32 reg, dummy; local
147 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
148 reg &= 0x80000000UL;
150 reg |= udma_timings[mode - XFER_UDMA_0];
152 reg |= mwdma_timings[mode - XFER_MW_DMA_0];
153 wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
H A Dpata_cs5536.c98 static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val) argument
103 rdmsr(MSR_IDE_CFG + reg, *val, dummy);
107 return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
110 static int cs5536_write(struct pci_dev *pdev, int reg, int val) argument
113 wrmsr(MSR_IDE_CFG + reg, val, 0);
117 return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
H A Dpata_cypress.c102 int reg = CY82_INDEX_CHANNEL0 + ap->port_no; local
105 outb(reg, 0x22);
H A Dpata_ep93xx.c263 bool reg)
267 unsigned long t0 = reg ? t->cyc8b : t->cycle;
268 unsigned long t2 = reg ? t->act8b : t->active;
269 unsigned long t2i = reg ? t->rec8b : t->recover;
297 bool reg)
301 unsigned long t0 = reg ? t->cyc8b : t->cycle;
302 unsigned long t2 = reg ? t->act8b : t->active;
303 unsigned long t2i = reg ? t->rec8b : t->recover;
261 ep93xx_pata_read(struct ep93xx_pata_data *drv_data, unsigned long addr, bool reg) argument
295 ep93xx_pata_write(struct ep93xx_pata_data *drv_data, u16 value, unsigned long addr, bool reg) argument
H A Dpata_hpt366.c236 u32 mask, reg, t; local
253 pci_read_config_dword(pdev, addr, &reg);
254 reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
255 pci_write_config_dword(pdev, addr, reg);
H A Dpata_hpt37x.c415 u32 reg, timing, mask; local
437 pci_read_config_dword(pdev, addr1, &reg);
438 reg = (reg & ~mask) | (timing & mask);
439 pci_write_config_dword(pdev, addr1, reg);
509 u32 reg, timing, mask; local
530 pci_read_config_dword(pdev, addr1, &reg);
531 reg = (reg & ~mask) | (timing & mask);
532 pci_write_config_dword(pdev, addr1, reg);
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H A Dpata_hpt3x2n.c186 u32 reg, timing, mask; local
207 pci_read_config_dword(pdev, addr1, &reg);
208 reg = (reg & ~mask) | (timing & mask);
209 pci_write_config_dword(pdev, addr1, reg);

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