Searched refs:status (Results 1 - 25 of 3329) sorted by last modified time

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/drivers/video/fbdev/
H A Dbf54x-lq043fb.c483 u16 status = bfin_read_EPPI0_STATUS(); local
487 if (status) {
H A Dbfin-lq035q1-fb.c549 u16 status = bfin_read_PPI_STATUS(); local
552 if (status) {
H A Dbfin-t350mcqb-fb.c405 u16 status = bfin_read_PPI_STATUS(); local
408 if (status) {
H A Dbfin_adv7393fb.c307 u16 status = bfin_read_PPI_STATUS(); local
309 pr_debug("%s: PPI Status = 0x%X\n", __func__, status);
311 if (status) {
H A Dbw2.c65 u8 status; member in struct:bw2_regs
232 u8 status, mon; local
235 status = sbus_readb(&par->regs->status);
236 mon = status & BWTWO_SR_RES_MASK;
237 switch (status & BWTWO_SR_ID_MASK) {
265 status);
H A Dcg3.c90 u8 status; member in struct:cg3_regs
319 u8 status = sbus_readb(&par->regs->status), mon; local
320 if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
321 mon = status & CG3_SR_RES_MASK;
329 status);
H A Dfsl-diu-fb.c1588 uint32_t status = in_be32(&hw->int_status); local
1590 if (status) {
1592 if (status & INT_UNDRUN) {
1598 else if (status & INT_VSYNC) {
1781 * all of them and clear the status register.
H A Dgoldfishfb.c60 u32 status; local
63 status = readl(fb->reg_base + FB_INT_STATUS);
64 if (status & FB_INT_BASE_UPDATE_DONE) {
69 return status ? IRQ_HANDLED : IRQ_NONE;
H A Dgrvga.c35 u32 status; /* 0x00 */ member in struct:grvga_regs
187 &par->regs->status);
493 __raw_writel(__raw_readl(&par->regs->status) | 1, /* Enable framebuffer */
494 &par->regs->status);
H A Dmacfb.c84 unsigned char status; /* OFFSET: 0x20 */ member in struct:__anon7124
366 * Grab a status word and do some checking;
H A Dps3fb.c62 u32 status; member in struct:display_head
79 u32 status; member in struct:gpu_irq
445 int status; local
455 status = lv1_gpu_fb_blit(ps3fb.context_handle, dst_offset,
462 if (status)
464 status);
466 status = lv1_gpu_display_flip(ps3fb.context_handle, 0, frame_offset);
467 if (status)
469 status);
472 status
912 int status; local
975 int status; local
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/drivers/video/fbdev/core/
H A Dfbcvt.c58 u32 status; member in struct:fb_cvt_data
208 cvt->status = 1;
232 if (cvt->status)
335 cvt.status = 1;
349 cvt.status = 1;
/drivers/video/fbdev/matrox/
H A Dmatroxfb_base.c203 u_int32_t status; local
207 status = mga_inl(M_STATUS);
209 if (status & 0x20) {
216 if (status & 0x200) {
/drivers/video/fbdev/mmp/
H A Dcore.c40 if (path->overlays[i].status)
/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.c202 if (path->status == on) {
204 path->name, stat_name(path->status));
219 path->status = on;
224 if (overlay->status == on) {
226 overlay->path->name, stat_name(overlay->status));
229 overlay->status = on;
232 != overlay->path->status)
H A Dmmp_ctrl.h1418 int status; member in struct:mmphw_ctrl
H A Dmmp_spi.c144 m->status = 0;
/drivers/video/fbdev/mmp/panel/
H A Dtpo_tj032md01bw.c84 void (*plat_onoff)(int status);
88 static void tpohvga_onoff(struct mmp_panel *panel, int status) argument
93 if (status) {
/drivers/video/fbdev/msm/
H A Dmddi.c43 struct mddi_client_status status; member in union:mddi_rev
51 uint32_t status; member in struct:reg_read_info
82 struct mddi_client_status status; member in struct:mddi_info
136 memcpy(&mddi->status, &rev->status,
159 ri->status = 0;
211 ri->status = -EIO;
260 uint32_t active, status; local
265 status = mddi_readl(STAT);
487 if (mddi->status
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H A Dmdp.c113 uint32_t status; local
119 status = mdp_readl(mdp, MDP_INTR_STATUS);
120 mdp_writel(mdp, status, MDP_INTR_CLEAR);
122 status &= mdp_irq_mask;
123 if (status & DL0_DMA2_TERM_DONE) {
131 if (status & DL0_ROI_DONE)
134 if (status)
135 locked_disable_mdp_irq(mdp, status);
/drivers/video/fbdev/omap/
H A Dlcdc.c149 static void reset_controller(u32 status) argument
158 "resetting (status %#010x,reset count %lu)\n",
159 status, reset_count);
243 u32 status; local
245 status = omap_readl(OMAP_LCDC_STATUS);
247 if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
248 reset_controller(status);
250 if (status & OMAP_LCDC_STAT_DONE) {
254 * Disable IRQ_DONE. The status bit will be cleared
263 if (status
607 lcdc_dma_handler(u16 status, void *data) argument
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/drivers/video/fbdev/omap2/dss/
H A Ddispc-compat.c237 static void print_irq_status(u32 status) argument
239 if ((status & dispc_compat.irq_error_mask) == 0)
242 #define PIS(x) (status & DISPC_IRQ_##x) ? (#x " ") : ""
245 status,
H A Ddsi.c606 static void print_irq_status(u32 status) argument
608 if (status == 0)
611 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
614 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
617 status,
638 static void print_irq_status_vc(int channel, u32 status) argument
640 if (status == 0)
643 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
646 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
650 status,
663 print_irq_status_cio(u32 status) argument
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H A Dhdmi4_core.c586 * Set IEC-60958-3 channel status word. It is passed to the IP
591 cfg->iec60958_cfg->status[0]);
593 cfg->iec60958_cfg->status[1]);
595 cfg->iec60958_cfg->status[2]);
596 /* yes, this is correct: status[3] goes to CHST4 register */
598 cfg->iec60958_cfg->status[3]);
599 /* yes, this is correct: status[4] goes to CHST5 register */
601 cfg->iec60958_cfg->status[4]);
698 * In the IEC-60958 status word, check if the audio sample word length
701 if (!(audio->iec->status[
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H A Dhdmi5_core.c706 val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
710 val = (cfg->iec60958_cfg->status[0] &
716 cfg->iec60958_cfg->status[1]);
719 val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
723 val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
745 cfg->iec60958_cfg->status[3]);
749 cfg->iec60958_cfg->status[4]);
816 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
817 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
824 switch (audio->iec->status[
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