/drivers/isdn/hisax/ |
H A D | avm_a1p.c | 67 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset); 68 ret = bytein(cs->hw.avm.cfg_reg + DATAREG_OFFSET); 76 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset); 77 byteout(cs->hw.avm.cfg_reg + DATAREG_OFFSET, value); 83 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_FIFO_OFFSET); 84 insb(cs->hw.avm.cfg_reg + DATAREG_OFFSET, data, size); 90 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_FIFO_OFFSET); 91 outsb(cs->hw.avm.cfg_reg + DATAREG_OFFSET, data, size); 100 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, 102 ret = bytein(cs->hw.avm.cfg_reg [all...] |
H A D | teles3.c | 162 if (cs->hw.teles3.cfg_reg) { 164 release_region(cs->hw.teles3.cfg_reg, 1); 166 release_region(cs->hw.teles3.cfg_reg, 8); 179 if ((cs->hw.teles3.cfg_reg) && (cs->typ != ISDN_CTYPE_COMPAQ_ISA)) { 209 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg); 211 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg | 1); 214 byteout(cs->hw.teles3.cfg_reg, 0xff); 216 byteout(cs->hw.teles3.cfg_reg, 0x00); 330 cs->hw.teles3.cfg_reg = card->para[1]; 331 switch (cs->hw.teles3.cfg_reg) { [all...] |
H A D | s0box.c | 98 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset)); 104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); 110 read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); 116 write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); 122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset)); 128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); 135 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg) 136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data) 137 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt) 138 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.cfg_reg, c [all...] |
H A D | avm_a1.c | 110 while (((sval = bytein(cs->hw.avm.cfg_reg)) & 0xf) != 0x7) { 112 byteout(cs->hw.avm.cfg_reg, 0x1E); 113 sval = bytein(cs->hw.avm.cfg_reg); 140 release_region(cs->hw.avm.cfg_reg, 8); 169 byteout(cs->hw.avm.cfg_reg, 0x16); 170 byteout(cs->hw.avm.cfg_reg, 0x1E); 191 cs->hw.avm.cfg_reg = card->para[1] + 0x1800; 199 if (!request_region(cs->hw.avm.cfg_reg, 8, "avm cfg")) { 202 cs->hw.avm.cfg_reg, 203 cs->hw.avm.cfg_reg [all...] |
H A D | teles0.c | 187 if (cs->hw.teles0.cfg_reg) 188 release_region(cs->hw.teles0.cfg_reg, 8); 198 if (cs->hw.teles0.cfg_reg) { 229 byteout(cs->hw.teles0.cfg_reg + 4, cfval); 231 byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1); 278 cs->hw.teles0.cfg_reg = card->para[2]; 280 cs->hw.teles0.cfg_reg = 0; 289 if (cs->hw.teles0.cfg_reg) { 290 if (!request_region(cs->hw.teles0.cfg_reg, 8, "teles cfg")) { 294 cs->hw.teles0.cfg_reg, [all...] |
H A D | sportster.c | 129 bytein(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ + 1); 139 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, 0); 141 adr = cs->hw.spt.cfg_reg + i * 1024; 150 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); 153 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); 176 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); 191 adr = cs->hw.spt.cfg_reg + i * 1024; 203 adr = cs->hw.spt.cfg_reg + j * 1024; 220 cs->hw.spt.cfg_reg = card->para[1]; 224 cs->hw.spt.isac = cs->hw.spt.cfg_reg [all...] |
H A D | sedlbauer.c | 404 if (cs->hw.sedl.cfg_reg) 405 release_region(cs->hw.sedl.cfg_reg, bytecnt); 427 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_on); 429 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); 454 byteout(cs->hw.sedl.cfg_reg + 5, 0); 474 byteout(cs->hw.sedl.cfg_reg + 5, 0x02); 501 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); 512 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); 567 cs->hw.sedl.cfg_reg = card->para[1]; 616 cs->hw.sedl.cfg_reg [all...] |
H A D | avm_pci.c | 83 outb(idx, cs->hw.avm.cfg_reg + 4); 93 outb(idx, cs->hw.avm.cfg_reg + 4); 100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4); 107 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4); 117 outl(idx, cs->hw.avm.cfg_reg + 4); 127 outl(idx, cs->hw.avm.cfg_reg + 4); 137 outb(idx, cs->hw.avm.cfg_reg + 4); 147 outb(idx, cs->hw.avm.cfg_reg + 4); 264 outl(idx, cs->hw.avm.cfg_reg + 4); 274 outb(idx, cs->hw.avm.cfg_reg [all...] |
H A D | mic.c | 163 if (cs->hw.mic.cfg_reg) 164 release_region(cs->hw.mic.cfg_reg, bytecnt); 202 cs->hw.mic.cfg_reg = card->para[1]; 204 cs->hw.mic.adr = cs->hw.mic.cfg_reg + MIC_ADR; 205 cs->hw.mic.isac = cs->hw.mic.cfg_reg + MIC_ISAC; 206 cs->hw.mic.hscx = cs->hw.mic.cfg_reg + MIC_HSCX; 208 if (!request_region(cs->hw.mic.cfg_reg, bytecnt, "mic isdn")) { 211 cs->hw.mic.cfg_reg, 212 cs->hw.mic.cfg_reg + bytecnt); 216 cs->hw.mic.cfg_reg, c [all...] |
H A D | niccy.c | 133 ival = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 138 outl(ival, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 178 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 180 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 181 release_region(cs->hw.niccy.cfg_reg, 0x40); 194 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 196 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 282 cs->hw.niccy.cfg_reg = 0; 317 cs->hw.niccy.cfg_reg = pci_resource_start(niccy_dev, 0); 318 if (!cs->hw.niccy.cfg_reg) { [all...] |
H A D | saphir.c | 176 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, 0xff); 179 if (cs->hw.saphir.cfg_reg) 180 release_region(cs->hw.saphir.cfg_reg, 6); 207 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val); 208 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 1); 210 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 0); 212 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val); 213 byteout(cs->hw.saphir.cfg_reg + SPARE_REG, 0x02); 254 cs->hw.saphir.cfg_reg = card->para[1]; 259 if (!request_region(cs->hw.saphir.cfg_reg, [all...] |
H A D | diva.c | 196 return (memreadreg(cs->hw.diva.cfg_reg, offset + 0x80)); 202 memwritereg(cs->hw.diva.cfg_reg, offset | 0x80, value); 209 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80); 216 memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++); 222 return (memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0))); 228 memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value); 235 return (memreadreg(cs->hw.diva.cfg_reg, offset)); 241 memwritereg(cs->hw.diva.cfg_reg, offset, value); 248 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0); 255 memwritereg(cs->hw.diva.cfg_reg, [all...] |
H A D | asuscom.c | 245 if (cs->hw.asus.cfg_reg) 246 release_region(cs->hw.asus.cfg_reg, bytecnt); 372 cs->hw.asus.cfg_reg = card->para[1]; 374 if (!request_region(cs->hw.asus.cfg_reg, bytecnt, "asuscom isdn")) { 377 cs->hw.asus.cfg_reg, 378 cs->hw.asus.cfg_reg + bytecnt); 382 cs->hw.asus.cfg_reg, cs->irq); 388 val = readreg(cs->hw.asus.cfg_reg + ASUS_IPAC_ALE, 389 cs->hw.asus.cfg_reg + ASUS_IPAC_DATA, IPAC_ID); 392 cs->hw.asus.adr = cs->hw.asus.cfg_reg [all...] |
H A D | ix1_micro.c | 167 if (cs->hw.ix1.cfg_reg) 168 release_region(cs->hw.ix1.cfg_reg, 4); 179 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 1); 182 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 0); 284 cs->hw.ix1.cfg_reg = card->para[1]; 286 if (cs->hw.ix1.cfg_reg) { 287 if (!request_region(cs->hw.ix1.cfg_reg, 4, "ix1micro cfg")) { 291 cs->hw.ix1.cfg_reg, 292 cs->hw.ix1.cfg_reg + 4); 297 cs->irq, cs->hw.ix1.cfg_reg); [all...] |
H A D | hisax.h | 582 unsigned int cfg_reg; member in struct:teles3_hw 590 unsigned int cfg_reg; member in struct:teles0_hw 596 unsigned int cfg_reg; member in struct:avm_hw 606 unsigned int cfg_reg; member in struct:ix1_hw 614 unsigned long cfg_reg; member in struct:diva_hw 628 unsigned int cfg_reg; member in struct:asus_hw 648 unsigned int cfg_reg; member in struct:sedl_hw 661 unsigned int cfg_reg; member in struct:spt_hw 668 unsigned int cfg_reg; member in struct:mic_hw 769 unsigned int cfg_reg; member in struct:saphir_hw 791 unsigned int cfg_reg; member in struct:gazel_hw [all...] |
H A D | gazel.c | 333 release_region(cs->hw.gazel.cfg_reg, 0x80); 338 release_region(cs->hw.gazel.cfg_reg, 0x80); 350 unsigned long plxcntrl, addr = cs->hw.gazel.cfg_reg; 457 if (!request_region(adr = cs->hw.gazel.cfg_reg, len = 0x80, "gazel")) { 466 if (!request_region(adr = cs->hw.gazel.cfg_reg, len = 0x80, "gazel")) { 499 cs->hw.gazel.cfg_reg = card->para[1] + 0xC000; 515 cs->irq, cs->hw.gazel.isac, cs->hw.gazel.cfg_reg); 584 cs->hw.gazel.cfg_reg = pci_ioaddr0 & 0xfffe; 602 cs->irq, cs->hw.gazel.isac, cs->hw.gazel.cfg_reg); 615 cs->irq, cs->hw.gazel.ipac, cs->hw.gazel.cfg_reg); [all...] |
/drivers/clk/spear/ |
H A D | clk-vco-pll.c | 134 p = readl_relaxed(pll->vco->cfg_reg); 157 val = readl_relaxed(pll->vco->cfg_reg); 160 writel_relaxed(val, pll->vco->cfg_reg); 204 val = readl_relaxed(vco->cfg_reg); 249 val = readl_relaxed(vco->cfg_reg); 261 writel_relaxed(val, vco->cfg_reg); 278 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, 288 if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg || 308 vco->cfg_reg = cfg_reg; 275 clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock, struct clk **pll_clk, struct clk **vco_gate_clk) argument [all...] |
H A D | clk.h | 96 void __iomem *cfg_reg; member in struct:clk_vco 126 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
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/drivers/net/ethernet/altera/ |
H A D | altera_tse_main.c | 638 u32 cfg_reg = ioread32(&priv->mac_dev->command_config); local 644 cfg_reg |= MAC_CMDCFG_HD_ENA; 646 cfg_reg &= ~MAC_CMDCFG_HD_ENA; 659 cfg_reg |= MAC_CMDCFG_ETH_SPEED; 660 cfg_reg &= ~MAC_CMDCFG_ENA_10; 663 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; 664 cfg_reg &= ~MAC_CMDCFG_ENA_10; 667 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; 668 cfg_reg |= MAC_CMDCFG_ENA_10; 678 iowrite32(cfg_reg, [all...] |
/drivers/pinctrl/samsung/ |
H A D | pinctrl-samsung.c | 430 u32 cfg_value, cfg_reg; local 442 cfg_reg = type->reg_offset[cfg_type]; 448 data = readl(reg_base + cfg_reg); 454 writel(data, reg_base + cfg_reg);
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/drivers/mmc/host/ |
H A D | atmel-mci.c | 133 * @cfg_reg: Value of the CFG register. 211 u32 cfg_reg; member in struct:atmel_mci 1156 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1310 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1357 host->cfg_reg |= ATMCI_CFG_HSMODE; 1359 host->cfg_reg &= ~ATMCI_CFG_HSMODE; 1365 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1492 atmci_writel(host, ATMCI_CFG, host->cfg_reg); 1593 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
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/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_ethtool.c | 1872 int cfg_reg; local 1878 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; 1880 cfg_reg = bp->link_params.req_fc_auto_adv; 1882 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == 1884 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
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/drivers/scsi/ |
H A D | gdth.h | 769 u8 cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/ member in struct:__anon5414
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