/drivers/gpu/drm/nouveau/core/subdev/i2c/ |
H A D | anx9805.c | 37 struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent; local 42 nv_wri2cr(mast, chan->addr, 0xa0, link_bw); 43 nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00)); 44 nv_wri2cr(mast, chan->addr, 0xa2, 0x01); 45 nv_wri2cr(mast, chan->addr, 0xa8, 0x01); 48 while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) { 69 struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent; local 76 tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04; 77 nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04); 78 nv_wri2cr(mast, cha 131 struct nouveau_i2c_port *mast = (void *)parent; local 174 struct nouveau_i2c_port *mast = (void *)nv_object(port)->parent; local 246 struct nouveau_i2c_port *mast = (void *)parent; local [all...] |
/drivers/gpu/drm/nouveau/core/subdev/clock/ |
H A D | nvaa.c | 84 u32 mast = nv_rd32(clk, 0x00c054); local 97 switch (mast & 0x000c0000) { 107 switch (mast & 0x00000003) { 115 if ((mast & 0x03000000) != 0x03000000) 118 if ((mast & 0x00000200) == 0x00000000) 121 switch (mast & 0x00000c00) { 129 switch (mast & 0x00000030) { 131 if (mast & 0x00000040) 145 switch (mast & 0x00400000) { 158 nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); 303 u32 pllmask = 0, mast; local [all...] |
H A D | nv50.c | 126 u32 src, mast = nv_rd32(priv, 0x00c040); local 130 src = !!(mast & 0x00200000); 133 src = !!(mast & 0x00400000); 136 src = !!(mast & 0x00010000); 139 src = !!(mast & 0x02000000); 157 u32 mast = nv_rd32(priv, 0x00c040); local 164 if (base == 0x004028 && (mast & 0x00100000)) { 191 u32 mast = nv_rd32(priv, 0x00c040); local 206 switch (mast & 0x30000000) { 214 if (!(mast [all...] |
H A D | nv40.c | 108 u32 mast = nv_rd32(priv, 0x00c040); local 116 return read_clk(priv, (mast & 0x00000003) >> 0); 118 return read_clk(priv, (mast & 0x00000030) >> 4); 125 nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
|
/drivers/gpu/drm/nouveau/ |
H A D | nv50_display.c | 372 struct nv50_mast mast; member in struct:nv50_disp 385 #define nv50_mast(d) (&nv50_disp(d)->mast) 444 struct nv50_mast *mast = nv50_mast(dev); local 445 u32 *push = evo_wait(mast, 8); 453 evo_kick(push, mast); 643 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); local 664 push = evo_wait(mast, 4); 666 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { 670 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) { 682 evo_kick(push, mast); 691 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); local 796 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); local 812 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); local 845 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); local 889 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); local 917 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); local 942 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); local 968 struct nv50_mast *mast = nv50_mast(crtc->dev); local 1007 struct nv50_mast *mast = nv50_mast(crtc->dev); local 1078 struct nv50_mast *mast = nv50_mast(crtc->dev); local 1526 struct nv50_mast *mast = nv50_mast(encoder->dev); local 1575 struct nv50_mast *mast = nv50_mast(encoder->dev); local 1861 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev); local 1913 struct nv50_mast *mast = nv50_mast(encoder->dev); local 2141 struct nv50_mast *mast = nv50_mast(encoder->dev); local 2191 struct nv50_mast *mast = nv50_mast(encoder->dev); local 2292 struct nv50_mast *mast = nv50_mast(dev); local [all...] |
/drivers/gpu/drm/nouveau/core/engine/disp/ |
H A D | nvd0.c | 297 struct nv50_disp_dmac *mast = (void *)object; local 300 ret = nv50_disp_chan_init(&mast->base); 308 nv_wr32(priv, 0x610494, mast->push); 317 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610490)); 328 struct nv50_disp_dmac *mast = (void *)object; local 334 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610490)); 343 return nv50_disp_chan_fini(&mast->base, suspend);
|
H A D | nv50.c | 491 struct nv50_disp_dmac *mast; local 503 0, sizeof(*mast), (void **)&mast); 504 *pobject = nv_object(mast); 515 struct nv50_disp_dmac *mast = (void *)object; local 518 ret = nv50_disp_chan_init(&mast->base); 532 nv_wr32(priv, 0x610204, mast->push); 541 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200)); 552 struct nv50_disp_dmac *mast = (void *)object; local 558 nv_error(mast, "fin [all...] |