1/*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2.  This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "skeleton.dtsi"
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
20
21/ {
22	model = "Marvell Armada 38x family SoC";
23	compatible = "marvell,armada380";
24
25	aliases {
26		gpio0 = &gpio0;
27		gpio1 = &gpio1;
28		eth0 = &eth0;
29		eth1 = &eth1;
30		eth2 = &eth2;
31	};
32
33	soc {
34		compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
35			     "simple-bus";
36		#address-cells = <2>;
37		#size-cells = <1>;
38		controller = <&mbusc>;
39		interrupt-parent = <&gic>;
40		pcie-mem-aperture = <0xe0000000 0x8000000>;
41		pcie-io-aperture  = <0xe8000000 0x100000>;
42
43		bootrom {
44			compatible = "marvell,bootrom";
45			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
46		};
47
48		devbus-bootcs {
49			compatible = "marvell,mvebu-devbus";
50			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
51			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
52			#address-cells = <1>;
53			#size-cells = <1>;
54			clocks = <&coreclk 0>;
55			status = "disabled";
56		};
57
58		devbus-cs0 {
59			compatible = "marvell,mvebu-devbus";
60			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
61			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
62			#address-cells = <1>;
63			#size-cells = <1>;
64			clocks = <&coreclk 0>;
65			status = "disabled";
66		};
67
68		devbus-cs1 {
69			compatible = "marvell,mvebu-devbus";
70			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
71			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
72			#address-cells = <1>;
73			#size-cells = <1>;
74			clocks = <&coreclk 0>;
75			status = "disabled";
76		};
77
78		devbus-cs2 {
79			compatible = "marvell,mvebu-devbus";
80			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
81			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
82			#address-cells = <1>;
83			#size-cells = <1>;
84			clocks = <&coreclk 0>;
85			status = "disabled";
86		};
87
88		devbus-cs3 {
89			compatible = "marvell,mvebu-devbus";
90			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
91			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
92			#address-cells = <1>;
93			#size-cells = <1>;
94			clocks = <&coreclk 0>;
95			status = "disabled";
96		};
97
98		internal-regs {
99			compatible = "simple-bus";
100			#address-cells = <1>;
101			#size-cells = <1>;
102			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
103
104			L2: cache-controller@8000 {
105				compatible = "arm,pl310-cache";
106				reg = <0x8000 0x1000>;
107				cache-unified;
108				cache-level = <2>;
109			};
110
111			scu@c000 {
112				compatible = "arm,cortex-a9-scu";
113				reg = <0xc000 0x58>;
114			};
115
116			timer@c600 {
117				compatible = "arm,cortex-a9-twd-timer";
118				reg = <0xc600 0x20>;
119				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
120				clocks = <&coreclk 2>;
121			};
122
123			gic: interrupt-controller@d000 {
124				compatible = "arm,cortex-a9-gic";
125				#interrupt-cells = <3>;
126				#size-cells = <0>;
127				interrupt-controller;
128				reg = <0xd000 0x1000>,
129				      <0xc100 0x100>;
130			};
131
132			spi0: spi@10600 {
133				compatible = "marvell,orion-spi";
134				reg = <0x10600 0x50>;
135				#address-cells = <1>;
136				#size-cells = <0>;
137				cell-index = <0>;
138				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
139				clocks = <&coreclk 0>;
140				status = "disabled";
141			};
142
143			spi1: spi@10680 {
144				compatible = "marvell,orion-spi";
145				reg = <0x10680 0x50>;
146				#address-cells = <1>;
147				#size-cells = <0>;
148				cell-index = <1>;
149				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
150				clocks = <&coreclk 0>;
151				status = "disabled";
152			};
153
154			i2c0: i2c@11000 {
155				compatible = "marvell,mv64xxx-i2c";
156				reg = <0x11000 0x20>;
157				#address-cells = <1>;
158				#size-cells = <0>;
159				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
160				timeout-ms = <1000>;
161				clocks = <&coreclk 0>;
162				status = "disabled";
163			};
164
165			i2c1: i2c@11100 {
166				compatible = "marvell,mv64xxx-i2c";
167				reg = <0x11100 0x20>;
168				#address-cells = <1>;
169				#size-cells = <0>;
170				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
171				timeout-ms = <1000>;
172				clocks = <&coreclk 0>;
173				status = "disabled";
174			};
175
176			serial@12000 {
177				compatible = "snps,dw-apb-uart";
178				reg = <0x12000 0x100>;
179				reg-shift = <2>;
180				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
181				reg-io-width = <1>;
182				clocks = <&coreclk 0>;
183				status = "disabled";
184			};
185
186			serial@12100 {
187				compatible = "snps,dw-apb-uart";
188				reg = <0x12100 0x100>;
189				reg-shift = <2>;
190				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
191				reg-io-width = <1>;
192				clocks = <&coreclk 0>;
193				status = "disabled";
194			};
195
196			pinctrl {
197				compatible = "marvell,mv88f6820-pinctrl";
198				reg = <0x18000 0x20>;
199			};
200
201			gpio0: gpio@18100 {
202				compatible = "marvell,orion-gpio";
203				reg = <0x18100 0x40>;
204				ngpios = <32>;
205				gpio-controller;
206				#gpio-cells = <2>;
207				interrupt-controller;
208				#interrupt-cells = <2>;
209				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
210					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
211					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
212					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
213			};
214
215			gpio1: gpio@18140 {
216				compatible = "marvell,orion-gpio";
217				reg = <0x18140 0x40>;
218				ngpios = <28>;
219				gpio-controller;
220				#gpio-cells = <2>;
221				interrupt-controller;
222				#interrupt-cells = <2>;
223				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
224					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
225					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
226					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
227			};
228
229			system-controller@18200 {
230				compatible = "marvell,armada-380-system-controller",
231					     "marvell,armada-370-xp-system-controller";
232				reg = <0x18200 0x100>;
233			};
234
235			gateclk: clock-gating-control@18220 {
236				compatible = "marvell,armada-380-gating-clock";
237				reg = <0x18220 0x4>;
238				clocks = <&coreclk 0>;
239				#clock-cells = <1>;
240			};
241
242			coreclk: mvebu-sar@18600 {
243				compatible = "marvell,armada-380-core-clock";
244				reg = <0x18600 0x04>;
245				#clock-cells = <1>;
246			};
247
248			mbusc: mbus-controller@20000 {
249				compatible = "marvell,mbus-controller";
250				reg = <0x20000 0x100>, <0x20180 0x20>;
251			};
252
253			mpic: interrupt-controller@20000 {
254				compatible = "marvell,mpic";
255				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
256				#interrupt-cells = <1>;
257				#size-cells = <1>;
258				interrupt-controller;
259				msi-controller;
260				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
261			};
262
263			timer@20300 {
264				compatible = "marvell,armada-380-timer",
265					     "marvell,armada-xp-timer";
266				reg = <0x20300 0x30>, <0x21040 0x30>;
267				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
268						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
269						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
270						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
271						      <&mpic 5>,
272						      <&mpic 6>;
273				clocks = <&coreclk 2>, <&refclk>;
274				clock-names = "nbclk", "fixed";
275			};
276
277			watchdog@20300 {
278				compatible = "marvell,armada-380-wdt";
279				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
280				clocks = <&coreclk 2>, <&refclk>;
281				clock-names = "nbclk", "fixed";
282			};
283
284			cpurst@20800 {
285				compatible = "marvell,armada-370-cpu-reset";
286				reg = <0x20800 0x10>;
287			};
288
289			mpcore-soc-ctrl@20d20 {
290				compatible = "marvell,armada-380-mpcore-soc-ctrl";
291				reg = <0x20d20 0x6c>;
292			};
293
294			coherency-fabric@21010 {
295				compatible = "marvell,armada-380-coherency-fabric";
296				reg = <0x21010 0x1c>;
297			};
298
299			pmsu@22000 {
300				compatible = "marvell,armada-380-pmsu";
301				reg = <0x22000 0x1000>;
302			};
303
304			eth1: ethernet@30000 {
305				compatible = "marvell,armada-370-neta";
306				reg = <0x30000 0x4000>;
307				interrupts-extended = <&mpic 10>;
308				clocks = <&gateclk 3>;
309				status = "disabled";
310			};
311
312			eth2: ethernet@34000 {
313				compatible = "marvell,armada-370-neta";
314				reg = <0x34000 0x4000>;
315				interrupts-extended = <&mpic 12>;
316				clocks = <&gateclk 2>;
317				status = "disabled";
318			};
319
320			usb@50000 {
321				compatible = "marvell,orion-ehci";
322				reg = <0x58000 0x500>;
323				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
324				clocks = <&gateclk 18>;
325				status = "disabled";
326			};
327
328			xor@60800 {
329				compatible = "marvell,orion-xor";
330				reg = <0x60800 0x100
331				       0x60a00 0x100>;
332				clocks = <&gateclk 22>;
333				status = "okay";
334
335				xor00 {
336					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
337					dmacap,memcpy;
338					dmacap,xor;
339				};
340				xor01 {
341					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
342					dmacap,memcpy;
343					dmacap,xor;
344					dmacap,memset;
345				};
346			};
347
348			xor@60900 {
349				compatible = "marvell,orion-xor";
350				reg = <0x60900 0x100
351				       0x60b00 0x100>;
352				clocks = <&gateclk 28>;
353				status = "okay";
354
355				xor10 {
356					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
357					dmacap,memcpy;
358					dmacap,xor;
359				};
360				xor11 {
361					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
362					dmacap,memcpy;
363					dmacap,xor;
364					dmacap,memset;
365				};
366			};
367
368			eth0: ethernet@70000 {
369				compatible = "marvell,armada-370-neta";
370				reg = <0x70000 0x4000>;
371				interrupts-extended = <&mpic 8>;
372				clocks = <&gateclk 4>;
373				status = "disabled";
374			};
375
376			mdio {
377				#address-cells = <1>;
378				#size-cells = <0>;
379				compatible = "marvell,orion-mdio";
380				reg = <0x72004 0x4>;
381				clocks = <&gateclk 4>;
382			};
383
384			sata@a8000 {
385				compatible = "marvell,armada-380-ahci";
386				reg = <0xa8000 0x2000>;
387				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
388				clocks = <&gateclk 15>;
389				status = "disabled";
390			};
391
392			sata@e0000 {
393				compatible = "marvell,armada-380-ahci";
394				reg = <0xe0000 0x2000>;
395				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
396				clocks = <&gateclk 30>;
397				status = "disabled";
398			};
399
400			coredivclk: clock@e4250 {
401				compatible = "marvell,armada-380-corediv-clock";
402				reg = <0xe4250 0xc>;
403				#clock-cells = <1>;
404				clocks = <&mainpll>;
405				clock-output-names = "nand";
406			};
407
408			thermal@e8078 {
409				compatible = "marvell,armada380-thermal";
410				reg = <0xe4078 0x4>, <0xe4074 0x4>;
411				status = "okay";
412			};
413
414			flash@d0000 {
415				compatible = "marvell,armada370-nand";
416				reg = <0xd0000 0x54>;
417				#address-cells = <1>;
418				#size-cells = <1>;
419				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
420				clocks = <&coredivclk 0>;
421				status = "disabled";
422			};
423
424			sdhci@d8000 {
425				compatible = "marvell,armada-380-sdhci";
426				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
427				interrupts = <0 25 0x4>;
428				clocks = <&gateclk 17>;
429				mrvl,clk-delay-cycles = <0x1F>;
430				status = "disabled";
431			};
432
433			usb3@f0000 {
434				compatible = "marvell,armada-380-xhci";
435				reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
436				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
437				clocks = <&gateclk 9>;
438				status = "disabled";
439			};
440
441			usb3@f8000 {
442				compatible = "marvell,armada-380-xhci";
443				reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
444				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
445				clocks = <&gateclk 10>;
446				status = "disabled";
447			};
448		};
449	};
450
451	clocks {
452		/* 2 GHz fixed main PLL */
453		mainpll: mainpll {
454			compatible = "fixed-clock";
455			#clock-cells = <0>;
456			clock-frequency = <2000000000>;
457		};
458
459		/* 25 MHz reference crystal */
460		refclk: oscillator {
461			compatible = "fixed-clock";
462			#clock-cells = <0>;
463			clock-frequency = <25000000>;
464		};
465	};
466};
467