1/* 2 * Device Tree Source for OMAP2430 clock data 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11&scrm_clocks { 12 mcbsp3_mux_fck: mcbsp3_mux_fck { 13 #clock-cells = <0>; 14 compatible = "ti,composite-mux-clock"; 15 clocks = <&func_96m_ck>, <&mcbsp_clks>; 16 reg = <0x02e8>; 17 }; 18 19 mcbsp3_fck: mcbsp3_fck { 20 #clock-cells = <0>; 21 compatible = "ti,composite-clock"; 22 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; 23 }; 24 25 mcbsp4_mux_fck: mcbsp4_mux_fck { 26 #clock-cells = <0>; 27 compatible = "ti,composite-mux-clock"; 28 clocks = <&func_96m_ck>, <&mcbsp_clks>; 29 ti,bit-shift = <2>; 30 reg = <0x02e8>; 31 }; 32 33 mcbsp4_fck: mcbsp4_fck { 34 #clock-cells = <0>; 35 compatible = "ti,composite-clock"; 36 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; 37 }; 38 39 mcbsp5_mux_fck: mcbsp5_mux_fck { 40 #clock-cells = <0>; 41 compatible = "ti,composite-mux-clock"; 42 clocks = <&func_96m_ck>, <&mcbsp_clks>; 43 ti,bit-shift = <4>; 44 reg = <0x02e8>; 45 }; 46 47 mcbsp5_fck: mcbsp5_fck { 48 #clock-cells = <0>; 49 compatible = "ti,composite-clock"; 50 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; 51 }; 52}; 53 54&prcm_clocks { 55 iva2_1_gate_ick: iva2_1_gate_ick { 56 #clock-cells = <0>; 57 compatible = "ti,composite-gate-clock"; 58 clocks = <&dsp_fck>; 59 ti,bit-shift = <0>; 60 reg = <0x0800>; 61 }; 62 63 iva2_1_div_ick: iva2_1_div_ick { 64 #clock-cells = <0>; 65 compatible = "ti,composite-divider-clock"; 66 clocks = <&dsp_fck>; 67 ti,bit-shift = <5>; 68 ti,max-div = <3>; 69 reg = <0x0840>; 70 ti,index-starts-at-one; 71 }; 72 73 iva2_1_ick: iva2_1_ick { 74 #clock-cells = <0>; 75 compatible = "ti,composite-clock"; 76 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>; 77 }; 78 79 mdm_gate_ick: mdm_gate_ick { 80 #clock-cells = <0>; 81 compatible = "ti,composite-interface-clock"; 82 clocks = <&core_ck>; 83 ti,bit-shift = <0>; 84 reg = <0x0c10>; 85 }; 86 87 mdm_div_ick: mdm_div_ick { 88 #clock-cells = <0>; 89 compatible = "ti,composite-divider-clock"; 90 clocks = <&core_ck>; 91 reg = <0x0c40>; 92 ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>; 93 }; 94 95 mdm_ick: mdm_ick { 96 #clock-cells = <0>; 97 compatible = "ti,composite-clock"; 98 clocks = <&mdm_gate_ick>, <&mdm_div_ick>; 99 }; 100 101 mdm_osc_ck: mdm_osc_ck { 102 #clock-cells = <0>; 103 compatible = "ti,omap3-interface-clock"; 104 clocks = <&osc_ck>; 105 ti,bit-shift = <1>; 106 reg = <0x0c00>; 107 }; 108 109 mcbsp3_ick: mcbsp3_ick { 110 #clock-cells = <0>; 111 compatible = "ti,omap3-interface-clock"; 112 clocks = <&l4_ck>; 113 ti,bit-shift = <3>; 114 reg = <0x0214>; 115 }; 116 117 mcbsp3_gate_fck: mcbsp3_gate_fck { 118 #clock-cells = <0>; 119 compatible = "ti,composite-gate-clock"; 120 clocks = <&mcbsp_clks>; 121 ti,bit-shift = <3>; 122 reg = <0x0204>; 123 }; 124 125 mcbsp4_ick: mcbsp4_ick { 126 #clock-cells = <0>; 127 compatible = "ti,omap3-interface-clock"; 128 clocks = <&l4_ck>; 129 ti,bit-shift = <4>; 130 reg = <0x0214>; 131 }; 132 133 mcbsp4_gate_fck: mcbsp4_gate_fck { 134 #clock-cells = <0>; 135 compatible = "ti,composite-gate-clock"; 136 clocks = <&mcbsp_clks>; 137 ti,bit-shift = <4>; 138 reg = <0x0204>; 139 }; 140 141 mcbsp5_ick: mcbsp5_ick { 142 #clock-cells = <0>; 143 compatible = "ti,omap3-interface-clock"; 144 clocks = <&l4_ck>; 145 ti,bit-shift = <5>; 146 reg = <0x0214>; 147 }; 148 149 mcbsp5_gate_fck: mcbsp5_gate_fck { 150 #clock-cells = <0>; 151 compatible = "ti,composite-gate-clock"; 152 clocks = <&mcbsp_clks>; 153 ti,bit-shift = <5>; 154 reg = <0x0204>; 155 }; 156 157 mcspi3_ick: mcspi3_ick { 158 #clock-cells = <0>; 159 compatible = "ti,omap3-interface-clock"; 160 clocks = <&l4_ck>; 161 ti,bit-shift = <9>; 162 reg = <0x0214>; 163 }; 164 165 mcspi3_fck: mcspi3_fck { 166 #clock-cells = <0>; 167 compatible = "ti,wait-gate-clock"; 168 clocks = <&func_48m_ck>; 169 ti,bit-shift = <9>; 170 reg = <0x0204>; 171 }; 172 173 icr_ick: icr_ick { 174 #clock-cells = <0>; 175 compatible = "ti,omap3-interface-clock"; 176 clocks = <&sys_ck>; 177 ti,bit-shift = <6>; 178 reg = <0x0410>; 179 }; 180 181 i2chs1_fck: i2chs1_fck { 182 #clock-cells = <0>; 183 compatible = "ti,omap2430-interface-clock"; 184 clocks = <&func_96m_ck>; 185 ti,bit-shift = <19>; 186 reg = <0x0204>; 187 }; 188 189 i2chs2_fck: i2chs2_fck { 190 #clock-cells = <0>; 191 compatible = "ti,omap2430-interface-clock"; 192 clocks = <&func_96m_ck>; 193 ti,bit-shift = <20>; 194 reg = <0x0204>; 195 }; 196 197 usbhs_ick: usbhs_ick { 198 #clock-cells = <0>; 199 compatible = "ti,omap3-interface-clock"; 200 clocks = <&core_l3_ck>; 201 ti,bit-shift = <6>; 202 reg = <0x0214>; 203 }; 204 205 mmchs1_ick: mmchs1_ick { 206 #clock-cells = <0>; 207 compatible = "ti,omap3-interface-clock"; 208 clocks = <&l4_ck>; 209 ti,bit-shift = <7>; 210 reg = <0x0214>; 211 }; 212 213 mmchs1_fck: mmchs1_fck { 214 #clock-cells = <0>; 215 compatible = "ti,wait-gate-clock"; 216 clocks = <&func_96m_ck>; 217 ti,bit-shift = <7>; 218 reg = <0x0204>; 219 }; 220 221 mmchs2_ick: mmchs2_ick { 222 #clock-cells = <0>; 223 compatible = "ti,omap3-interface-clock"; 224 clocks = <&l4_ck>; 225 ti,bit-shift = <8>; 226 reg = <0x0214>; 227 }; 228 229 mmchs2_fck: mmchs2_fck { 230 #clock-cells = <0>; 231 compatible = "ti,wait-gate-clock"; 232 clocks = <&func_96m_ck>; 233 ti,bit-shift = <8>; 234 reg = <0x0204>; 235 }; 236 237 gpio5_ick: gpio5_ick { 238 #clock-cells = <0>; 239 compatible = "ti,omap3-interface-clock"; 240 clocks = <&l4_ck>; 241 ti,bit-shift = <10>; 242 reg = <0x0214>; 243 }; 244 245 gpio5_fck: gpio5_fck { 246 #clock-cells = <0>; 247 compatible = "ti,wait-gate-clock"; 248 clocks = <&func_32k_ck>; 249 ti,bit-shift = <10>; 250 reg = <0x0204>; 251 }; 252 253 mdm_intc_ick: mdm_intc_ick { 254 #clock-cells = <0>; 255 compatible = "ti,omap3-interface-clock"; 256 clocks = <&l4_ck>; 257 ti,bit-shift = <11>; 258 reg = <0x0214>; 259 }; 260 261 mmchsdb1_fck: mmchsdb1_fck { 262 #clock-cells = <0>; 263 compatible = "ti,wait-gate-clock"; 264 clocks = <&func_32k_ck>; 265 ti,bit-shift = <16>; 266 reg = <0x0204>; 267 }; 268 269 mmchsdb2_fck: mmchsdb2_fck { 270 #clock-cells = <0>; 271 compatible = "ti,wait-gate-clock"; 272 clocks = <&func_32k_ck>; 273 ti,bit-shift = <17>; 274 reg = <0x0204>; 275 }; 276}; 277 278&prcm_clockdomains { 279 gfx_clkdm: gfx_clkdm { 280 compatible = "ti,clockdomain"; 281 clocks = <&gfx_ick>; 282 }; 283 284 core_l3_clkdm: core_l3_clkdm { 285 compatible = "ti,clockdomain"; 286 clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>; 287 }; 288 289 wkup_clkdm: wkup_clkdm { 290 compatible = "ti,clockdomain"; 291 clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, 292 <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, 293 <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>, 294 <&icr_ick>; 295 }; 296 297 dss_clkdm: dss_clkdm { 298 compatible = "ti,clockdomain"; 299 clocks = <&dss_ick>, <&dss_54m_fck>; 300 }; 301 302 core_l4_clkdm: core_l4_clkdm { 303 compatible = "ti,clockdomain"; 304 clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, 305 <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, 306 <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, 307 <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, 308 <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>, 309 <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, 310 <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>, 311 <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>, 312 <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>, 313 <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>, 314 <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>, 315 <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>, 316 <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, 317 <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>, 318 <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>, 319 <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>, 320 <&mmchsdb2_fck>; 321 }; 322 323 mdm_clkdm: mdm_clkdm { 324 compatible = "ti,clockdomain"; 325 clocks = <&mdm_osc_ck>; 326 }; 327}; 328 329&func_96m_ck { 330 compatible = "ti,mux-clock"; 331 clocks = <&apll96_ck>, <&alt_ck>; 332 ti,bit-shift = <4>; 333 reg = <0x0540>; 334}; 335 336&dsp_div_fck { 337 ti,max-div = <4>; 338 ti,index-starts-at-one; 339}; 340 341&ssi_ssr_sst_div_fck { 342 ti,max-div = <5>; 343 ti,index-starts-at-one; 344}; 345