sa1111.c revision 36d312130228504a223de44739c807b0353248c1
1/* 2 * linux/arch/arm/common/sa1111.c 3 * 4 * SA1111 support 5 * 6 * Original code by John Dorsey 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This file contains all generic SA1111 support. 13 * 14 * All initialization functions provided here are intended to be called 15 * from machine specific code with proper arguments when required. 16 */ 17#include <linux/module.h> 18#include <linux/init.h> 19#include <linux/irq.h> 20#include <linux/kernel.h> 21#include <linux/delay.h> 22#include <linux/errno.h> 23#include <linux/ioport.h> 24#include <linux/platform_device.h> 25#include <linux/slab.h> 26#include <linux/spinlock.h> 27#include <linux/dma-mapping.h> 28#include <linux/clk.h> 29#include <linux/io.h> 30 31#include <mach/hardware.h> 32#include <asm/mach/irq.h> 33#include <asm/mach-types.h> 34#include <asm/sizes.h> 35 36#include <asm/hardware/sa1111.h> 37 38/* SA1111 IRQs */ 39#define IRQ_GPAIN0 (0) 40#define IRQ_GPAIN1 (1) 41#define IRQ_GPAIN2 (2) 42#define IRQ_GPAIN3 (3) 43#define IRQ_GPBIN0 (4) 44#define IRQ_GPBIN1 (5) 45#define IRQ_GPBIN2 (6) 46#define IRQ_GPBIN3 (7) 47#define IRQ_GPBIN4 (8) 48#define IRQ_GPBIN5 (9) 49#define IRQ_GPCIN0 (10) 50#define IRQ_GPCIN1 (11) 51#define IRQ_GPCIN2 (12) 52#define IRQ_GPCIN3 (13) 53#define IRQ_GPCIN4 (14) 54#define IRQ_GPCIN5 (15) 55#define IRQ_GPCIN6 (16) 56#define IRQ_GPCIN7 (17) 57#define IRQ_MSTXINT (18) 58#define IRQ_MSRXINT (19) 59#define IRQ_MSSTOPERRINT (20) 60#define IRQ_TPTXINT (21) 61#define IRQ_TPRXINT (22) 62#define IRQ_TPSTOPERRINT (23) 63#define SSPXMTINT (24) 64#define SSPRCVINT (25) 65#define SSPROR (26) 66#define AUDXMTDMADONEA (32) 67#define AUDRCVDMADONEA (33) 68#define AUDXMTDMADONEB (34) 69#define AUDRCVDMADONEB (35) 70#define AUDTFSR (36) 71#define AUDRFSR (37) 72#define AUDTUR (38) 73#define AUDROR (39) 74#define AUDDTS (40) 75#define AUDRDD (41) 76#define AUDSTO (42) 77#define IRQ_USBPWR (43) 78#define IRQ_HCIM (44) 79#define IRQ_HCIBUFFACC (45) 80#define IRQ_HCIRMTWKP (46) 81#define IRQ_NHCIMFCIR (47) 82#define IRQ_USB_PORT_RESUME (48) 83#define IRQ_S0_READY_NINT (49) 84#define IRQ_S1_READY_NINT (50) 85#define IRQ_S0_CD_VALID (51) 86#define IRQ_S1_CD_VALID (52) 87#define IRQ_S0_BVD1_STSCHG (53) 88#define IRQ_S1_BVD1_STSCHG (54) 89#define SA1111_IRQ_NR (55) 90 91extern void sa1110_mb_enable(void); 92extern void sa1110_mb_disable(void); 93 94/* 95 * We keep the following data for the overall SA1111. Note that the 96 * struct device and struct resource are "fake"; they should be supplied 97 * by the bus above us. However, in the interests of getting all SA1111 98 * drivers converted over to the device model, we provide this as an 99 * anchor point for all the other drivers. 100 */ 101struct sa1111 { 102 struct device *dev; 103 struct clk *clk; 104 unsigned long phys; 105 int irq; 106 int irq_base; /* base for cascaded on-chip IRQs */ 107 spinlock_t lock; 108 void __iomem *base; 109#ifdef CONFIG_PM 110 void *saved_state; 111#endif 112}; 113 114/* 115 * We _really_ need to eliminate this. Its only users 116 * are the PWM and DMA checking code. 117 */ 118static struct sa1111 *g_sa1111; 119 120struct sa1111_dev_info { 121 unsigned long offset; 122 unsigned long skpcr_mask; 123 unsigned int devid; 124 unsigned int irq[6]; 125}; 126 127static struct sa1111_dev_info sa1111_devices[] = { 128 { 129 .offset = SA1111_USB, 130 .skpcr_mask = SKPCR_UCLKEN, 131 .devid = SA1111_DEVID_USB, 132 .irq = { 133 IRQ_USBPWR, 134 IRQ_HCIM, 135 IRQ_HCIBUFFACC, 136 IRQ_HCIRMTWKP, 137 IRQ_NHCIMFCIR, 138 IRQ_USB_PORT_RESUME 139 }, 140 }, 141 { 142 .offset = 0x0600, 143 .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN, 144 .devid = SA1111_DEVID_SAC, 145 .irq = { 146 AUDXMTDMADONEA, 147 AUDXMTDMADONEB, 148 AUDRCVDMADONEA, 149 AUDRCVDMADONEB 150 }, 151 }, 152 { 153 .offset = 0x0800, 154 .skpcr_mask = SKPCR_SCLKEN, 155 .devid = SA1111_DEVID_SSP, 156 }, 157 { 158 .offset = SA1111_KBD, 159 .skpcr_mask = SKPCR_PTCLKEN, 160 .devid = SA1111_DEVID_PS2, 161 .irq = { 162 IRQ_TPRXINT, 163 IRQ_TPTXINT 164 }, 165 }, 166 { 167 .offset = SA1111_MSE, 168 .skpcr_mask = SKPCR_PMCLKEN, 169 .devid = SA1111_DEVID_PS2, 170 .irq = { 171 IRQ_MSRXINT, 172 IRQ_MSTXINT 173 }, 174 }, 175 { 176 .offset = 0x1800, 177 .skpcr_mask = 0, 178 .devid = SA1111_DEVID_PCMCIA, 179 .irq = { 180 IRQ_S0_READY_NINT, 181 IRQ_S0_CD_VALID, 182 IRQ_S0_BVD1_STSCHG, 183 IRQ_S1_READY_NINT, 184 IRQ_S1_CD_VALID, 185 IRQ_S1_BVD1_STSCHG, 186 }, 187 }, 188}; 189 190/* 191 * SA1111 interrupt support. Since clearing an IRQ while there are 192 * active IRQs causes the interrupt output to pulse, the upper levels 193 * will call us again if there are more interrupts to process. 194 */ 195static void 196sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) 197{ 198 unsigned int stat0, stat1, i; 199 struct sa1111 *sachip = irq_get_handler_data(irq); 200 void __iomem *mapbase = sachip->base + SA1111_INTC; 201 202 stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); 203 stat1 = sa1111_readl(mapbase + SA1111_INTSTATCLR1); 204 205 sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0); 206 207 desc->irq_data.chip->irq_ack(&desc->irq_data); 208 209 sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1); 210 211 if (stat0 == 0 && stat1 == 0) { 212 do_bad_IRQ(irq, desc); 213 return; 214 } 215 216 for (i = 0; stat0; i++, stat0 >>= 1) 217 if (stat0 & 1) 218 generic_handle_irq(i + sachip->irq_base); 219 220 for (i = 32; stat1; i++, stat1 >>= 1) 221 if (stat1 & 1) 222 generic_handle_irq(i + sachip->irq_base); 223 224 /* For level-based interrupts */ 225 desc->irq_data.chip->irq_unmask(&desc->irq_data); 226} 227 228#define SA1111_IRQMASK_LO(x) (1 << (x - sachip->irq_base)) 229#define SA1111_IRQMASK_HI(x) (1 << (x - sachip->irq_base - 32)) 230 231static void sa1111_ack_irq(struct irq_data *d) 232{ 233} 234 235static void sa1111_mask_lowirq(struct irq_data *d) 236{ 237 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 238 void __iomem *mapbase = sachip->base + SA1111_INTC; 239 unsigned long ie0; 240 241 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 242 ie0 &= ~SA1111_IRQMASK_LO(d->irq); 243 writel(ie0, mapbase + SA1111_INTEN0); 244} 245 246static void sa1111_unmask_lowirq(struct irq_data *d) 247{ 248 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 249 void __iomem *mapbase = sachip->base + SA1111_INTC; 250 unsigned long ie0; 251 252 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 253 ie0 |= SA1111_IRQMASK_LO(d->irq); 254 sa1111_writel(ie0, mapbase + SA1111_INTEN0); 255} 256 257/* 258 * Attempt to re-trigger the interrupt. The SA1111 contains a register 259 * (INTSET) which claims to do this. However, in practice no amount of 260 * manipulation of INTEN and INTSET guarantees that the interrupt will 261 * be triggered. In fact, its very difficult, if not impossible to get 262 * INTSET to re-trigger the interrupt. 263 */ 264static int sa1111_retrigger_lowirq(struct irq_data *d) 265{ 266 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 267 void __iomem *mapbase = sachip->base + SA1111_INTC; 268 unsigned int mask = SA1111_IRQMASK_LO(d->irq); 269 unsigned long ip0; 270 int i; 271 272 ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); 273 for (i = 0; i < 8; i++) { 274 sa1111_writel(ip0 ^ mask, mapbase + SA1111_INTPOL0); 275 sa1111_writel(ip0, mapbase + SA1111_INTPOL0); 276 if (sa1111_readl(mapbase + SA1111_INTSTATCLR0) & mask) 277 break; 278 } 279 280 if (i == 8) 281 printk(KERN_ERR "Danger Will Robinson: failed to " 282 "re-trigger IRQ%d\n", d->irq); 283 return i == 8 ? -1 : 0; 284} 285 286static int sa1111_type_lowirq(struct irq_data *d, unsigned int flags) 287{ 288 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 289 void __iomem *mapbase = sachip->base + SA1111_INTC; 290 unsigned int mask = SA1111_IRQMASK_LO(d->irq); 291 unsigned long ip0; 292 293 if (flags == IRQ_TYPE_PROBE) 294 return 0; 295 296 if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) 297 return -EINVAL; 298 299 ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); 300 if (flags & IRQ_TYPE_EDGE_RISING) 301 ip0 &= ~mask; 302 else 303 ip0 |= mask; 304 sa1111_writel(ip0, mapbase + SA1111_INTPOL0); 305 sa1111_writel(ip0, mapbase + SA1111_WAKEPOL0); 306 307 return 0; 308} 309 310static int sa1111_wake_lowirq(struct irq_data *d, unsigned int on) 311{ 312 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 313 void __iomem *mapbase = sachip->base + SA1111_INTC; 314 unsigned int mask = SA1111_IRQMASK_LO(d->irq); 315 unsigned long we0; 316 317 we0 = sa1111_readl(mapbase + SA1111_WAKEEN0); 318 if (on) 319 we0 |= mask; 320 else 321 we0 &= ~mask; 322 sa1111_writel(we0, mapbase + SA1111_WAKEEN0); 323 324 return 0; 325} 326 327static struct irq_chip sa1111_low_chip = { 328 .name = "SA1111-l", 329 .irq_ack = sa1111_ack_irq, 330 .irq_mask = sa1111_mask_lowirq, 331 .irq_unmask = sa1111_unmask_lowirq, 332 .irq_retrigger = sa1111_retrigger_lowirq, 333 .irq_set_type = sa1111_type_lowirq, 334 .irq_set_wake = sa1111_wake_lowirq, 335}; 336 337static void sa1111_mask_highirq(struct irq_data *d) 338{ 339 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 340 void __iomem *mapbase = sachip->base + SA1111_INTC; 341 unsigned long ie1; 342 343 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 344 ie1 &= ~SA1111_IRQMASK_HI(d->irq); 345 sa1111_writel(ie1, mapbase + SA1111_INTEN1); 346} 347 348static void sa1111_unmask_highirq(struct irq_data *d) 349{ 350 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 351 void __iomem *mapbase = sachip->base + SA1111_INTC; 352 unsigned long ie1; 353 354 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 355 ie1 |= SA1111_IRQMASK_HI(d->irq); 356 sa1111_writel(ie1, mapbase + SA1111_INTEN1); 357} 358 359/* 360 * Attempt to re-trigger the interrupt. The SA1111 contains a register 361 * (INTSET) which claims to do this. However, in practice no amount of 362 * manipulation of INTEN and INTSET guarantees that the interrupt will 363 * be triggered. In fact, its very difficult, if not impossible to get 364 * INTSET to re-trigger the interrupt. 365 */ 366static int sa1111_retrigger_highirq(struct irq_data *d) 367{ 368 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 369 void __iomem *mapbase = sachip->base + SA1111_INTC; 370 unsigned int mask = SA1111_IRQMASK_HI(d->irq); 371 unsigned long ip1; 372 int i; 373 374 ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); 375 for (i = 0; i < 8; i++) { 376 sa1111_writel(ip1 ^ mask, mapbase + SA1111_INTPOL1); 377 sa1111_writel(ip1, mapbase + SA1111_INTPOL1); 378 if (sa1111_readl(mapbase + SA1111_INTSTATCLR1) & mask) 379 break; 380 } 381 382 if (i == 8) 383 printk(KERN_ERR "Danger Will Robinson: failed to " 384 "re-trigger IRQ%d\n", d->irq); 385 return i == 8 ? -1 : 0; 386} 387 388static int sa1111_type_highirq(struct irq_data *d, unsigned int flags) 389{ 390 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 391 void __iomem *mapbase = sachip->base + SA1111_INTC; 392 unsigned int mask = SA1111_IRQMASK_HI(d->irq); 393 unsigned long ip1; 394 395 if (flags == IRQ_TYPE_PROBE) 396 return 0; 397 398 if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) 399 return -EINVAL; 400 401 ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); 402 if (flags & IRQ_TYPE_EDGE_RISING) 403 ip1 &= ~mask; 404 else 405 ip1 |= mask; 406 sa1111_writel(ip1, mapbase + SA1111_INTPOL1); 407 sa1111_writel(ip1, mapbase + SA1111_WAKEPOL1); 408 409 return 0; 410} 411 412static int sa1111_wake_highirq(struct irq_data *d, unsigned int on) 413{ 414 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 415 void __iomem *mapbase = sachip->base + SA1111_INTC; 416 unsigned int mask = SA1111_IRQMASK_HI(d->irq); 417 unsigned long we1; 418 419 we1 = sa1111_readl(mapbase + SA1111_WAKEEN1); 420 if (on) 421 we1 |= mask; 422 else 423 we1 &= ~mask; 424 sa1111_writel(we1, mapbase + SA1111_WAKEEN1); 425 426 return 0; 427} 428 429static struct irq_chip sa1111_high_chip = { 430 .name = "SA1111-h", 431 .irq_ack = sa1111_ack_irq, 432 .irq_mask = sa1111_mask_highirq, 433 .irq_unmask = sa1111_unmask_highirq, 434 .irq_retrigger = sa1111_retrigger_highirq, 435 .irq_set_type = sa1111_type_highirq, 436 .irq_set_wake = sa1111_wake_highirq, 437}; 438 439static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) 440{ 441 void __iomem *irqbase = sachip->base + SA1111_INTC; 442 unsigned i, irq; 443 int ret; 444 445 /* 446 * We're guaranteed that this region hasn't been taken. 447 */ 448 request_mem_region(sachip->phys + SA1111_INTC, 512, "irq"); 449 450 ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1); 451 if (ret <= 0) { 452 dev_err(sachip->dev, "unable to allocate %u irqs: %d\n", 453 SA1111_IRQ_NR, ret); 454 if (ret == 0) 455 ret = -EINVAL; 456 return ret; 457 } 458 459 sachip->irq_base = ret; 460 461 /* disable all IRQs */ 462 sa1111_writel(0, irqbase + SA1111_INTEN0); 463 sa1111_writel(0, irqbase + SA1111_INTEN1); 464 sa1111_writel(0, irqbase + SA1111_WAKEEN0); 465 sa1111_writel(0, irqbase + SA1111_WAKEEN1); 466 467 /* 468 * detect on rising edge. Note: Feb 2001 Errata for SA1111 469 * specifies that S0ReadyInt and S1ReadyInt should be '1'. 470 */ 471 sa1111_writel(0, irqbase + SA1111_INTPOL0); 472 sa1111_writel(SA1111_IRQMASK_HI(IRQ_S0_READY_NINT) | 473 SA1111_IRQMASK_HI(IRQ_S1_READY_NINT), 474 irqbase + SA1111_INTPOL1); 475 476 /* clear all IRQs */ 477 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0); 478 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); 479 480 for (i = IRQ_GPAIN0; i <= SSPROR; i++) { 481 irq = sachip->irq_base + i; 482 irq_set_chip_and_handler(irq, &sa1111_low_chip, 483 handle_edge_irq); 484 irq_set_chip_data(irq, sachip); 485 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 486 } 487 488 for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) { 489 irq = sachip->irq_base + i; 490 irq_set_chip_and_handler(irq, &sa1111_high_chip, 491 handle_edge_irq); 492 irq_set_chip_data(irq, sachip); 493 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 494 } 495 496 /* 497 * Register SA1111 interrupt 498 */ 499 irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); 500 irq_set_handler_data(sachip->irq, sachip); 501 irq_set_chained_handler(sachip->irq, sa1111_irq_handler); 502 503 dev_info(sachip->dev, "Providing IRQ%u-%u\n", 504 sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1); 505 506 return 0; 507} 508 509/* 510 * Bring the SA1111 out of reset. This requires a set procedure: 511 * 1. nRESET asserted (by hardware) 512 * 2. CLK turned on from SA1110 513 * 3. nRESET deasserted 514 * 4. VCO turned on, PLL_BYPASS turned off 515 * 5. Wait lock time, then assert RCLKEn 516 * 7. PCR set to allow clocking of individual functions 517 * 518 * Until we've done this, the only registers we can access are: 519 * SBI_SKCR 520 * SBI_SMCR 521 * SBI_SKID 522 */ 523static void sa1111_wake(struct sa1111 *sachip) 524{ 525 unsigned long flags, r; 526 527 spin_lock_irqsave(&sachip->lock, flags); 528 529 clk_enable(sachip->clk); 530 531 /* 532 * Turn VCO on, and disable PLL Bypass. 533 */ 534 r = sa1111_readl(sachip->base + SA1111_SKCR); 535 r &= ~SKCR_VCO_OFF; 536 sa1111_writel(r, sachip->base + SA1111_SKCR); 537 r |= SKCR_PLL_BYPASS | SKCR_OE_EN; 538 sa1111_writel(r, sachip->base + SA1111_SKCR); 539 540 /* 541 * Wait lock time. SA1111 manual _doesn't_ 542 * specify a figure for this! We choose 100us. 543 */ 544 udelay(100); 545 546 /* 547 * Enable RCLK. We also ensure that RDYEN is set. 548 */ 549 r |= SKCR_RCLKEN | SKCR_RDYEN; 550 sa1111_writel(r, sachip->base + SA1111_SKCR); 551 552 /* 553 * Wait 14 RCLK cycles for the chip to finish coming out 554 * of reset. (RCLK=24MHz). This is 590ns. 555 */ 556 udelay(1); 557 558 /* 559 * Ensure all clocks are initially off. 560 */ 561 sa1111_writel(0, sachip->base + SA1111_SKPCR); 562 563 spin_unlock_irqrestore(&sachip->lock, flags); 564} 565 566#ifdef CONFIG_ARCH_SA1100 567 568static u32 sa1111_dma_mask[] = { 569 ~0, 570 ~(1 << 20), 571 ~(1 << 23), 572 ~(1 << 24), 573 ~(1 << 25), 574 ~(1 << 20), 575 ~(1 << 20), 576 0, 577}; 578 579/* 580 * Configure the SA1111 shared memory controller. 581 */ 582void 583sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac, 584 unsigned int cas_latency) 585{ 586 unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC); 587 588 if (cas_latency == 3) 589 smcr |= SMCR_CLAT; 590 591 sa1111_writel(smcr, sachip->base + SA1111_SMCR); 592 593 /* 594 * Now clear the bits in the DMA mask to work around the SA1111 595 * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion 596 * Chip Specification Update, June 2000, Erratum #7). 597 */ 598 if (sachip->dev->dma_mask) 599 *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2]; 600 601 sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2]; 602} 603#endif 604 605#ifdef CONFIG_DMABOUNCE 606/* 607 * According to the "Intel StrongARM SA-1111 Microprocessor Companion 608 * Chip Specification Update" (June 2000), erratum #7, there is a 609 * significant bug in the SA1111 SDRAM shared memory controller. If 610 * an access to a region of memory above 1MB relative to the bank base, 611 * it is important that address bit 10 _NOT_ be asserted. Depending 612 * on the configuration of the RAM, bit 10 may correspond to one 613 * of several different (processor-relative) address bits. 614 * 615 * This routine only identifies whether or not a given DMA address 616 * is susceptible to the bug. 617 * 618 * This should only get called for sa1111_device types due to the 619 * way we configure our device dma_masks. 620 */ 621static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) 622{ 623 /* 624 * Section 4.6 of the "Intel StrongARM SA-1111 Development Module 625 * User's Guide" mentions that jumpers R51 and R52 control the 626 * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or 627 * SDRAM bank 1 on Neponset). The default configuration selects 628 * Assabet, so any address in bank 1 is necessarily invalid. 629 */ 630 return (machine_is_assabet() || machine_is_pfs168()) && 631 (addr >= 0xc8000000 || (addr + size) >= 0xc8000000); 632} 633#endif 634 635static void sa1111_dev_release(struct device *_dev) 636{ 637 struct sa1111_dev *dev = SA1111_DEV(_dev); 638 639 release_resource(&dev->res); 640 kfree(dev); 641} 642 643static int 644sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent, 645 struct sa1111_dev_info *info) 646{ 647 struct sa1111_dev *dev; 648 unsigned i; 649 int ret; 650 651 dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL); 652 if (!dev) { 653 ret = -ENOMEM; 654 goto out; 655 } 656 657 dev_set_name(&dev->dev, "%4.4lx", info->offset); 658 dev->devid = info->devid; 659 dev->dev.parent = sachip->dev; 660 dev->dev.bus = &sa1111_bus_type; 661 dev->dev.release = sa1111_dev_release; 662 dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask; 663 dev->res.start = sachip->phys + info->offset; 664 dev->res.end = dev->res.start + 511; 665 dev->res.name = dev_name(&dev->dev); 666 dev->res.flags = IORESOURCE_MEM; 667 dev->mapbase = sachip->base + info->offset; 668 dev->skpcr_mask = info->skpcr_mask; 669 670 for (i = 0; i < ARRAY_SIZE(info->irq); i++) 671 dev->irq[i] = sachip->irq_base + info->irq[i]; 672 673 ret = request_resource(parent, &dev->res); 674 if (ret) { 675 printk("SA1111: failed to allocate resource for %s\n", 676 dev->res.name); 677 dev_set_name(&dev->dev, NULL); 678 kfree(dev); 679 goto out; 680 } 681 682 683 ret = device_register(&dev->dev); 684 if (ret) { 685 release_resource(&dev->res); 686 kfree(dev); 687 goto out; 688 } 689 690#ifdef CONFIG_DMABOUNCE 691 /* 692 * If the parent device has a DMA mask associated with it, 693 * propagate it down to the children. 694 */ 695 if (sachip->dev->dma_mask) { 696 dev->dma_mask = *sachip->dev->dma_mask; 697 dev->dev.dma_mask = &dev->dma_mask; 698 699 if (dev->dma_mask != 0xffffffffUL) { 700 ret = dmabounce_register_dev(&dev->dev, 1024, 4096, 701 sa1111_needs_bounce); 702 if (ret) { 703 dev_err(&dev->dev, "SA1111: Failed to register" 704 " with dmabounce\n"); 705 device_unregister(&dev->dev); 706 } 707 } 708 } 709#endif 710 711out: 712 return ret; 713} 714 715/** 716 * sa1111_probe - probe for a single SA1111 chip. 717 * @phys_addr: physical address of device. 718 * 719 * Probe for a SA1111 chip. This must be called 720 * before any other SA1111-specific code. 721 * 722 * Returns: 723 * %-ENODEV device not found. 724 * %-EBUSY physical address already marked in-use. 725 * %-EINVAL no platform data passed 726 * %0 successful. 727 */ 728static int __devinit 729__sa1111_probe(struct device *me, struct resource *mem, int irq) 730{ 731 struct sa1111_platform_data *pd = me->platform_data; 732 struct sa1111 *sachip; 733 unsigned long id; 734 unsigned int has_devs; 735 int i, ret = -ENODEV; 736 737 if (!pd) 738 return -EINVAL; 739 740 sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL); 741 if (!sachip) 742 return -ENOMEM; 743 744 sachip->clk = clk_get(me, "SA1111_CLK"); 745 if (IS_ERR(sachip->clk)) { 746 ret = PTR_ERR(sachip->clk); 747 goto err_free; 748 } 749 750 ret = clk_prepare(sachip->clk); 751 if (ret) 752 goto err_clkput; 753 754 spin_lock_init(&sachip->lock); 755 756 sachip->dev = me; 757 dev_set_drvdata(sachip->dev, sachip); 758 759 sachip->phys = mem->start; 760 sachip->irq = irq; 761 762 /* 763 * Map the whole region. This also maps the 764 * registers for our children. 765 */ 766 sachip->base = ioremap(mem->start, PAGE_SIZE * 2); 767 if (!sachip->base) { 768 ret = -ENOMEM; 769 goto err_clk_unprep; 770 } 771 772 /* 773 * Probe for the chip. Only touch the SBI registers. 774 */ 775 id = sa1111_readl(sachip->base + SA1111_SKID); 776 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { 777 printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id); 778 ret = -ENODEV; 779 goto err_unmap; 780 } 781 782 printk(KERN_INFO "SA1111 Microprocessor Companion Chip: " 783 "silicon revision %lx, metal revision %lx\n", 784 (id & SKID_SIREV_MASK)>>4, (id & SKID_MTREV_MASK)); 785 786 /* 787 * We found it. Wake the chip up, and initialise. 788 */ 789 sa1111_wake(sachip); 790 791 /* 792 * The interrupt controller must be initialised before any 793 * other device to ensure that the interrupts are available. 794 */ 795 if (sachip->irq != NO_IRQ) { 796 ret = sa1111_setup_irq(sachip, pd->irq_base); 797 if (ret) 798 goto err_unmap; 799 } 800 801#ifdef CONFIG_ARCH_SA1100 802 { 803 unsigned int val; 804 805 /* 806 * The SDRAM configuration of the SA1110 and the SA1111 must 807 * match. This is very important to ensure that SA1111 accesses 808 * don't corrupt the SDRAM. Note that this ungates the SA1111's 809 * MBGNT signal, so we must have called sa1110_mb_disable() 810 * beforehand. 811 */ 812 sa1111_configure_smc(sachip, 1, 813 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), 814 FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); 815 816 /* 817 * We only need to turn on DCLK whenever we want to use the 818 * DMA. It can otherwise be held firmly in the off position. 819 * (currently, we always enable it.) 820 */ 821 val = sa1111_readl(sachip->base + SA1111_SKPCR); 822 sa1111_writel(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR); 823 824 /* 825 * Enable the SA1110 memory bus request and grant signals. 826 */ 827 sa1110_mb_enable(); 828 } 829#endif 830 831 g_sa1111 = sachip; 832 833 has_devs = ~0; 834 if (machine_is_assabet() || machine_is_jornada720() || 835 machine_is_badge4()) 836 has_devs &= ~(1 << 4); 837 else 838 has_devs &= ~(1 << 1); 839 840 for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++) 841 if (has_devs & (1 << i)) 842 sa1111_init_one_child(sachip, mem, &sa1111_devices[i]); 843 844 return 0; 845 846 err_unmap: 847 iounmap(sachip->base); 848 err_clk_unprep: 849 clk_unprepare(sachip->clk); 850 err_clkput: 851 clk_put(sachip->clk); 852 err_free: 853 kfree(sachip); 854 return ret; 855} 856 857static int sa1111_remove_one(struct device *dev, void *data) 858{ 859 device_unregister(dev); 860 return 0; 861} 862 863static void __sa1111_remove(struct sa1111 *sachip) 864{ 865 void __iomem *irqbase = sachip->base + SA1111_INTC; 866 867 device_for_each_child(sachip->dev, NULL, sa1111_remove_one); 868 869 /* disable all IRQs */ 870 sa1111_writel(0, irqbase + SA1111_INTEN0); 871 sa1111_writel(0, irqbase + SA1111_INTEN1); 872 sa1111_writel(0, irqbase + SA1111_WAKEEN0); 873 sa1111_writel(0, irqbase + SA1111_WAKEEN1); 874 875 clk_disable(sachip->clk); 876 clk_unprepare(sachip->clk); 877 878 if (sachip->irq != NO_IRQ) { 879 irq_set_chained_handler(sachip->irq, NULL); 880 irq_set_handler_data(sachip->irq, NULL); 881 irq_free_descs(sachip->irq_base, SA1111_IRQ_NR); 882 883 release_mem_region(sachip->phys + SA1111_INTC, 512); 884 } 885 886 iounmap(sachip->base); 887 clk_put(sachip->clk); 888 kfree(sachip); 889} 890 891struct sa1111_save_data { 892 unsigned int skcr; 893 unsigned int skpcr; 894 unsigned int skcdr; 895 unsigned char skaud; 896 unsigned char skpwm0; 897 unsigned char skpwm1; 898 899 /* 900 * Interrupt controller 901 */ 902 unsigned int intpol0; 903 unsigned int intpol1; 904 unsigned int inten0; 905 unsigned int inten1; 906 unsigned int wakepol0; 907 unsigned int wakepol1; 908 unsigned int wakeen0; 909 unsigned int wakeen1; 910}; 911 912#ifdef CONFIG_PM 913 914static int sa1111_suspend(struct platform_device *dev, pm_message_t state) 915{ 916 struct sa1111 *sachip = platform_get_drvdata(dev); 917 struct sa1111_save_data *save; 918 unsigned long flags; 919 unsigned int val; 920 void __iomem *base; 921 922 save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL); 923 if (!save) 924 return -ENOMEM; 925 sachip->saved_state = save; 926 927 spin_lock_irqsave(&sachip->lock, flags); 928 929 /* 930 * Save state. 931 */ 932 base = sachip->base; 933 save->skcr = sa1111_readl(base + SA1111_SKCR); 934 save->skpcr = sa1111_readl(base + SA1111_SKPCR); 935 save->skcdr = sa1111_readl(base + SA1111_SKCDR); 936 save->skaud = sa1111_readl(base + SA1111_SKAUD); 937 save->skpwm0 = sa1111_readl(base + SA1111_SKPWM0); 938 save->skpwm1 = sa1111_readl(base + SA1111_SKPWM1); 939 940 sa1111_writel(0, sachip->base + SA1111_SKPWM0); 941 sa1111_writel(0, sachip->base + SA1111_SKPWM1); 942 943 base = sachip->base + SA1111_INTC; 944 save->intpol0 = sa1111_readl(base + SA1111_INTPOL0); 945 save->intpol1 = sa1111_readl(base + SA1111_INTPOL1); 946 save->inten0 = sa1111_readl(base + SA1111_INTEN0); 947 save->inten1 = sa1111_readl(base + SA1111_INTEN1); 948 save->wakepol0 = sa1111_readl(base + SA1111_WAKEPOL0); 949 save->wakepol1 = sa1111_readl(base + SA1111_WAKEPOL1); 950 save->wakeen0 = sa1111_readl(base + SA1111_WAKEEN0); 951 save->wakeen1 = sa1111_readl(base + SA1111_WAKEEN1); 952 953 /* 954 * Disable. 955 */ 956 val = sa1111_readl(sachip->base + SA1111_SKCR); 957 sa1111_writel(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); 958 959 clk_disable(sachip->clk); 960 961 spin_unlock_irqrestore(&sachip->lock, flags); 962 963#ifdef CONFIG_ARCH_SA1100 964 sa1110_mb_disable(); 965#endif 966 967 return 0; 968} 969 970/* 971 * sa1111_resume - Restore the SA1111 device state. 972 * @dev: device to restore 973 * 974 * Restore the general state of the SA1111; clock control and 975 * interrupt controller. Other parts of the SA1111 must be 976 * restored by their respective drivers, and must be called 977 * via LDM after this function. 978 */ 979static int sa1111_resume(struct platform_device *dev) 980{ 981 struct sa1111 *sachip = platform_get_drvdata(dev); 982 struct sa1111_save_data *save; 983 unsigned long flags, id; 984 void __iomem *base; 985 986 save = sachip->saved_state; 987 if (!save) 988 return 0; 989 990 /* 991 * Ensure that the SA1111 is still here. 992 * FIXME: shouldn't do this here. 993 */ 994 id = sa1111_readl(sachip->base + SA1111_SKID); 995 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { 996 __sa1111_remove(sachip); 997 platform_set_drvdata(dev, NULL); 998 kfree(save); 999 return 0; 1000 } 1001 1002 /* 1003 * First of all, wake up the chip. 1004 */ 1005 sa1111_wake(sachip); 1006 1007#ifdef CONFIG_ARCH_SA1100 1008 /* Enable the memory bus request/grant signals */ 1009 sa1110_mb_enable(); 1010#endif 1011 1012 /* 1013 * Only lock for write ops. Also, sa1111_wake must be called with 1014 * released spinlock! 1015 */ 1016 spin_lock_irqsave(&sachip->lock, flags); 1017 1018 sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN0); 1019 sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN1); 1020 1021 base = sachip->base; 1022 sa1111_writel(save->skcr, base + SA1111_SKCR); 1023 sa1111_writel(save->skpcr, base + SA1111_SKPCR); 1024 sa1111_writel(save->skcdr, base + SA1111_SKCDR); 1025 sa1111_writel(save->skaud, base + SA1111_SKAUD); 1026 sa1111_writel(save->skpwm0, base + SA1111_SKPWM0); 1027 sa1111_writel(save->skpwm1, base + SA1111_SKPWM1); 1028 1029 base = sachip->base + SA1111_INTC; 1030 sa1111_writel(save->intpol0, base + SA1111_INTPOL0); 1031 sa1111_writel(save->intpol1, base + SA1111_INTPOL1); 1032 sa1111_writel(save->inten0, base + SA1111_INTEN0); 1033 sa1111_writel(save->inten1, base + SA1111_INTEN1); 1034 sa1111_writel(save->wakepol0, base + SA1111_WAKEPOL0); 1035 sa1111_writel(save->wakepol1, base + SA1111_WAKEPOL1); 1036 sa1111_writel(save->wakeen0, base + SA1111_WAKEEN0); 1037 sa1111_writel(save->wakeen1, base + SA1111_WAKEEN1); 1038 1039 spin_unlock_irqrestore(&sachip->lock, flags); 1040 1041 sachip->saved_state = NULL; 1042 kfree(save); 1043 1044 return 0; 1045} 1046 1047#else 1048#define sa1111_suspend NULL 1049#define sa1111_resume NULL 1050#endif 1051 1052static int __devinit sa1111_probe(struct platform_device *pdev) 1053{ 1054 struct resource *mem; 1055 int irq; 1056 1057 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1058 if (!mem) 1059 return -EINVAL; 1060 irq = platform_get_irq(pdev, 0); 1061 if (irq < 0) 1062 return -ENXIO; 1063 1064 return __sa1111_probe(&pdev->dev, mem, irq); 1065} 1066 1067static int sa1111_remove(struct platform_device *pdev) 1068{ 1069 struct sa1111 *sachip = platform_get_drvdata(pdev); 1070 1071 if (sachip) { 1072#ifdef CONFIG_PM 1073 kfree(sachip->saved_state); 1074 sachip->saved_state = NULL; 1075#endif 1076 __sa1111_remove(sachip); 1077 platform_set_drvdata(pdev, NULL); 1078 } 1079 1080 return 0; 1081} 1082 1083/* 1084 * Not sure if this should be on the system bus or not yet. 1085 * We really want some way to register a system device at 1086 * the per-machine level, and then have this driver pick 1087 * up the registered devices. 1088 * 1089 * We also need to handle the SDRAM configuration for 1090 * PXA250/SA1110 machine classes. 1091 */ 1092static struct platform_driver sa1111_device_driver = { 1093 .probe = sa1111_probe, 1094 .remove = sa1111_remove, 1095 .suspend = sa1111_suspend, 1096 .resume = sa1111_resume, 1097 .driver = { 1098 .name = "sa1111", 1099 .owner = THIS_MODULE, 1100 }, 1101}; 1102 1103/* 1104 * Get the parent device driver (us) structure 1105 * from a child function device 1106 */ 1107static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev) 1108{ 1109 return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent); 1110} 1111 1112/* 1113 * The bits in the opdiv field are non-linear. 1114 */ 1115static unsigned char opdiv_table[] = { 1, 4, 2, 8 }; 1116 1117static unsigned int __sa1111_pll_clock(struct sa1111 *sachip) 1118{ 1119 unsigned int skcdr, fbdiv, ipdiv, opdiv; 1120 1121 skcdr = sa1111_readl(sachip->base + SA1111_SKCDR); 1122 1123 fbdiv = (skcdr & 0x007f) + 2; 1124 ipdiv = ((skcdr & 0x0f80) >> 7) + 2; 1125 opdiv = opdiv_table[(skcdr & 0x3000) >> 12]; 1126 1127 return 3686400 * fbdiv / (ipdiv * opdiv); 1128} 1129 1130/** 1131 * sa1111_pll_clock - return the current PLL clock frequency. 1132 * @sadev: SA1111 function block 1133 * 1134 * BUG: we should look at SKCR. We also blindly believe that 1135 * the chip is being fed with the 3.6864MHz clock. 1136 * 1137 * Returns the PLL clock in Hz. 1138 */ 1139unsigned int sa1111_pll_clock(struct sa1111_dev *sadev) 1140{ 1141 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1142 1143 return __sa1111_pll_clock(sachip); 1144} 1145EXPORT_SYMBOL(sa1111_pll_clock); 1146 1147/** 1148 * sa1111_select_audio_mode - select I2S or AC link mode 1149 * @sadev: SA1111 function block 1150 * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S 1151 * 1152 * Frob the SKCR to select AC Link mode or I2S mode for 1153 * the audio block. 1154 */ 1155void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode) 1156{ 1157 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1158 unsigned long flags; 1159 unsigned int val; 1160 1161 spin_lock_irqsave(&sachip->lock, flags); 1162 1163 val = sa1111_readl(sachip->base + SA1111_SKCR); 1164 if (mode == SA1111_AUDIO_I2S) { 1165 val &= ~SKCR_SELAC; 1166 } else { 1167 val |= SKCR_SELAC; 1168 } 1169 sa1111_writel(val, sachip->base + SA1111_SKCR); 1170 1171 spin_unlock_irqrestore(&sachip->lock, flags); 1172} 1173EXPORT_SYMBOL(sa1111_select_audio_mode); 1174 1175/** 1176 * sa1111_set_audio_rate - set the audio sample rate 1177 * @sadev: SA1111 SAC function block 1178 * @rate: sample rate to select 1179 */ 1180int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate) 1181{ 1182 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1183 unsigned int div; 1184 1185 if (sadev->devid != SA1111_DEVID_SAC) 1186 return -EINVAL; 1187 1188 div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate; 1189 if (div == 0) 1190 div = 1; 1191 if (div > 128) 1192 div = 128; 1193 1194 sa1111_writel(div - 1, sachip->base + SA1111_SKAUD); 1195 1196 return 0; 1197} 1198EXPORT_SYMBOL(sa1111_set_audio_rate); 1199 1200/** 1201 * sa1111_get_audio_rate - get the audio sample rate 1202 * @sadev: SA1111 SAC function block device 1203 */ 1204int sa1111_get_audio_rate(struct sa1111_dev *sadev) 1205{ 1206 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1207 unsigned long div; 1208 1209 if (sadev->devid != SA1111_DEVID_SAC) 1210 return -EINVAL; 1211 1212 div = sa1111_readl(sachip->base + SA1111_SKAUD) + 1; 1213 1214 return __sa1111_pll_clock(sachip) / (256 * div); 1215} 1216EXPORT_SYMBOL(sa1111_get_audio_rate); 1217 1218void sa1111_set_io_dir(struct sa1111_dev *sadev, 1219 unsigned int bits, unsigned int dir, 1220 unsigned int sleep_dir) 1221{ 1222 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1223 unsigned long flags; 1224 unsigned int val; 1225 void __iomem *gpio = sachip->base + SA1111_GPIO; 1226 1227#define MODIFY_BITS(port, mask, dir) \ 1228 if (mask) { \ 1229 val = sa1111_readl(port); \ 1230 val &= ~(mask); \ 1231 val |= (dir) & (mask); \ 1232 sa1111_writel(val, port); \ 1233 } 1234 1235 spin_lock_irqsave(&sachip->lock, flags); 1236 MODIFY_BITS(gpio + SA1111_GPIO_PADDR, bits & 15, dir); 1237 MODIFY_BITS(gpio + SA1111_GPIO_PBDDR, (bits >> 8) & 255, dir >> 8); 1238 MODIFY_BITS(gpio + SA1111_GPIO_PCDDR, (bits >> 16) & 255, dir >> 16); 1239 1240 MODIFY_BITS(gpio + SA1111_GPIO_PASDR, bits & 15, sleep_dir); 1241 MODIFY_BITS(gpio + SA1111_GPIO_PBSDR, (bits >> 8) & 255, sleep_dir >> 8); 1242 MODIFY_BITS(gpio + SA1111_GPIO_PCSDR, (bits >> 16) & 255, sleep_dir >> 16); 1243 spin_unlock_irqrestore(&sachip->lock, flags); 1244} 1245EXPORT_SYMBOL(sa1111_set_io_dir); 1246 1247void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v) 1248{ 1249 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1250 unsigned long flags; 1251 unsigned int val; 1252 void __iomem *gpio = sachip->base + SA1111_GPIO; 1253 1254 spin_lock_irqsave(&sachip->lock, flags); 1255 MODIFY_BITS(gpio + SA1111_GPIO_PADWR, bits & 15, v); 1256 MODIFY_BITS(gpio + SA1111_GPIO_PBDWR, (bits >> 8) & 255, v >> 8); 1257 MODIFY_BITS(gpio + SA1111_GPIO_PCDWR, (bits >> 16) & 255, v >> 16); 1258 spin_unlock_irqrestore(&sachip->lock, flags); 1259} 1260EXPORT_SYMBOL(sa1111_set_io); 1261 1262void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v) 1263{ 1264 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1265 unsigned long flags; 1266 unsigned int val; 1267 void __iomem *gpio = sachip->base + SA1111_GPIO; 1268 1269 spin_lock_irqsave(&sachip->lock, flags); 1270 MODIFY_BITS(gpio + SA1111_GPIO_PASSR, bits & 15, v); 1271 MODIFY_BITS(gpio + SA1111_GPIO_PBSSR, (bits >> 8) & 255, v >> 8); 1272 MODIFY_BITS(gpio + SA1111_GPIO_PCSSR, (bits >> 16) & 255, v >> 16); 1273 spin_unlock_irqrestore(&sachip->lock, flags); 1274} 1275EXPORT_SYMBOL(sa1111_set_sleep_io); 1276 1277/* 1278 * Individual device operations. 1279 */ 1280 1281/** 1282 * sa1111_enable_device - enable an on-chip SA1111 function block 1283 * @sadev: SA1111 function block device to enable 1284 */ 1285void sa1111_enable_device(struct sa1111_dev *sadev) 1286{ 1287 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1288 unsigned long flags; 1289 unsigned int val; 1290 1291 spin_lock_irqsave(&sachip->lock, flags); 1292 val = sa1111_readl(sachip->base + SA1111_SKPCR); 1293 sa1111_writel(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); 1294 spin_unlock_irqrestore(&sachip->lock, flags); 1295} 1296EXPORT_SYMBOL(sa1111_enable_device); 1297 1298/** 1299 * sa1111_disable_device - disable an on-chip SA1111 function block 1300 * @sadev: SA1111 function block device to disable 1301 */ 1302void sa1111_disable_device(struct sa1111_dev *sadev) 1303{ 1304 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1305 unsigned long flags; 1306 unsigned int val; 1307 1308 spin_lock_irqsave(&sachip->lock, flags); 1309 val = sa1111_readl(sachip->base + SA1111_SKPCR); 1310 sa1111_writel(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); 1311 spin_unlock_irqrestore(&sachip->lock, flags); 1312} 1313EXPORT_SYMBOL(sa1111_disable_device); 1314 1315/* 1316 * SA1111 "Register Access Bus." 1317 * 1318 * We model this as a regular bus type, and hang devices directly 1319 * off this. 1320 */ 1321static int sa1111_match(struct device *_dev, struct device_driver *_drv) 1322{ 1323 struct sa1111_dev *dev = SA1111_DEV(_dev); 1324 struct sa1111_driver *drv = SA1111_DRV(_drv); 1325 1326 return dev->devid == drv->devid; 1327} 1328 1329static int sa1111_bus_suspend(struct device *dev, pm_message_t state) 1330{ 1331 struct sa1111_dev *sadev = SA1111_DEV(dev); 1332 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1333 int ret = 0; 1334 1335 if (drv && drv->suspend) 1336 ret = drv->suspend(sadev, state); 1337 return ret; 1338} 1339 1340static int sa1111_bus_resume(struct device *dev) 1341{ 1342 struct sa1111_dev *sadev = SA1111_DEV(dev); 1343 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1344 int ret = 0; 1345 1346 if (drv && drv->resume) 1347 ret = drv->resume(sadev); 1348 return ret; 1349} 1350 1351static int sa1111_bus_probe(struct device *dev) 1352{ 1353 struct sa1111_dev *sadev = SA1111_DEV(dev); 1354 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1355 int ret = -ENODEV; 1356 1357 if (drv->probe) 1358 ret = drv->probe(sadev); 1359 return ret; 1360} 1361 1362static int sa1111_bus_remove(struct device *dev) 1363{ 1364 struct sa1111_dev *sadev = SA1111_DEV(dev); 1365 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1366 int ret = 0; 1367 1368 if (drv->remove) 1369 ret = drv->remove(sadev); 1370 return ret; 1371} 1372 1373struct bus_type sa1111_bus_type = { 1374 .name = "sa1111-rab", 1375 .match = sa1111_match, 1376 .probe = sa1111_bus_probe, 1377 .remove = sa1111_bus_remove, 1378 .suspend = sa1111_bus_suspend, 1379 .resume = sa1111_bus_resume, 1380}; 1381EXPORT_SYMBOL(sa1111_bus_type); 1382 1383int sa1111_driver_register(struct sa1111_driver *driver) 1384{ 1385 driver->drv.bus = &sa1111_bus_type; 1386 return driver_register(&driver->drv); 1387} 1388EXPORT_SYMBOL(sa1111_driver_register); 1389 1390void sa1111_driver_unregister(struct sa1111_driver *driver) 1391{ 1392 driver_unregister(&driver->drv); 1393} 1394EXPORT_SYMBOL(sa1111_driver_unregister); 1395 1396static int __init sa1111_init(void) 1397{ 1398 int ret = bus_register(&sa1111_bus_type); 1399 if (ret == 0) 1400 platform_driver_register(&sa1111_device_driver); 1401 return ret; 1402} 1403 1404static void __exit sa1111_exit(void) 1405{ 1406 platform_driver_unregister(&sa1111_device_driver); 1407 bus_unregister(&sa1111_bus_type); 1408} 1409 1410subsys_initcall(sa1111_init); 1411module_exit(sa1111_exit); 1412 1413MODULE_DESCRIPTION("Intel Corporation SA1111 core driver"); 1414MODULE_LICENSE("GPL"); 1415