sa1111.c revision e5c0fc4185c551c270868dcb6573604db2bc3171
1/* 2 * linux/arch/arm/common/sa1111.c 3 * 4 * SA1111 support 5 * 6 * Original code by John Dorsey 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This file contains all generic SA1111 support. 13 * 14 * All initialization functions provided here are intended to be called 15 * from machine specific code with proper arguments when required. 16 */ 17#include <linux/module.h> 18#include <linux/init.h> 19#include <linux/irq.h> 20#include <linux/kernel.h> 21#include <linux/delay.h> 22#include <linux/errno.h> 23#include <linux/ioport.h> 24#include <linux/platform_device.h> 25#include <linux/slab.h> 26#include <linux/spinlock.h> 27#include <linux/dma-mapping.h> 28#include <linux/clk.h> 29#include <linux/io.h> 30 31#include <mach/hardware.h> 32#include <asm/mach/irq.h> 33#include <asm/mach-types.h> 34#include <asm/sizes.h> 35 36#include <asm/hardware/sa1111.h> 37 38/* SA1111 IRQs */ 39#define IRQ_GPAIN0 (0) 40#define IRQ_GPAIN1 (1) 41#define IRQ_GPAIN2 (2) 42#define IRQ_GPAIN3 (3) 43#define IRQ_GPBIN0 (4) 44#define IRQ_GPBIN1 (5) 45#define IRQ_GPBIN2 (6) 46#define IRQ_GPBIN3 (7) 47#define IRQ_GPBIN4 (8) 48#define IRQ_GPBIN5 (9) 49#define IRQ_GPCIN0 (10) 50#define IRQ_GPCIN1 (11) 51#define IRQ_GPCIN2 (12) 52#define IRQ_GPCIN3 (13) 53#define IRQ_GPCIN4 (14) 54#define IRQ_GPCIN5 (15) 55#define IRQ_GPCIN6 (16) 56#define IRQ_GPCIN7 (17) 57#define IRQ_MSTXINT (18) 58#define IRQ_MSRXINT (19) 59#define IRQ_MSSTOPERRINT (20) 60#define IRQ_TPTXINT (21) 61#define IRQ_TPRXINT (22) 62#define IRQ_TPSTOPERRINT (23) 63#define SSPXMTINT (24) 64#define SSPRCVINT (25) 65#define SSPROR (26) 66#define AUDXMTDMADONEA (32) 67#define AUDRCVDMADONEA (33) 68#define AUDXMTDMADONEB (34) 69#define AUDRCVDMADONEB (35) 70#define AUDTFSR (36) 71#define AUDRFSR (37) 72#define AUDTUR (38) 73#define AUDROR (39) 74#define AUDDTS (40) 75#define AUDRDD (41) 76#define AUDSTO (42) 77#define IRQ_USBPWR (43) 78#define IRQ_HCIM (44) 79#define IRQ_HCIBUFFACC (45) 80#define IRQ_HCIRMTWKP (46) 81#define IRQ_NHCIMFCIR (47) 82#define IRQ_USB_PORT_RESUME (48) 83#define IRQ_S0_READY_NINT (49) 84#define IRQ_S1_READY_NINT (50) 85#define IRQ_S0_CD_VALID (51) 86#define IRQ_S1_CD_VALID (52) 87#define IRQ_S0_BVD1_STSCHG (53) 88#define IRQ_S1_BVD1_STSCHG (54) 89#define SA1111_IRQ_NR (55) 90 91extern void sa1110_mb_enable(void); 92extern void sa1110_mb_disable(void); 93 94/* 95 * We keep the following data for the overall SA1111. Note that the 96 * struct device and struct resource are "fake"; they should be supplied 97 * by the bus above us. However, in the interests of getting all SA1111 98 * drivers converted over to the device model, we provide this as an 99 * anchor point for all the other drivers. 100 */ 101struct sa1111 { 102 struct device *dev; 103 struct clk *clk; 104 unsigned long phys; 105 int irq; 106 int irq_base; /* base for cascaded on-chip IRQs */ 107 spinlock_t lock; 108 void __iomem *base; 109 struct sa1111_platform_data *pdata; 110#ifdef CONFIG_PM 111 void *saved_state; 112#endif 113}; 114 115/* 116 * We _really_ need to eliminate this. Its only users 117 * are the PWM and DMA checking code. 118 */ 119static struct sa1111 *g_sa1111; 120 121struct sa1111_dev_info { 122 unsigned long offset; 123 unsigned long skpcr_mask; 124 unsigned int devid; 125 unsigned int irq[6]; 126}; 127 128static struct sa1111_dev_info sa1111_devices[] = { 129 { 130 .offset = SA1111_USB, 131 .skpcr_mask = SKPCR_UCLKEN, 132 .devid = SA1111_DEVID_USB, 133 .irq = { 134 IRQ_USBPWR, 135 IRQ_HCIM, 136 IRQ_HCIBUFFACC, 137 IRQ_HCIRMTWKP, 138 IRQ_NHCIMFCIR, 139 IRQ_USB_PORT_RESUME 140 }, 141 }, 142 { 143 .offset = 0x0600, 144 .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN, 145 .devid = SA1111_DEVID_SAC, 146 .irq = { 147 AUDXMTDMADONEA, 148 AUDXMTDMADONEB, 149 AUDRCVDMADONEA, 150 AUDRCVDMADONEB 151 }, 152 }, 153 { 154 .offset = 0x0800, 155 .skpcr_mask = SKPCR_SCLKEN, 156 .devid = SA1111_DEVID_SSP, 157 }, 158 { 159 .offset = SA1111_KBD, 160 .skpcr_mask = SKPCR_PTCLKEN, 161 .devid = SA1111_DEVID_PS2_KBD, 162 .irq = { 163 IRQ_TPRXINT, 164 IRQ_TPTXINT 165 }, 166 }, 167 { 168 .offset = SA1111_MSE, 169 .skpcr_mask = SKPCR_PMCLKEN, 170 .devid = SA1111_DEVID_PS2_MSE, 171 .irq = { 172 IRQ_MSRXINT, 173 IRQ_MSTXINT 174 }, 175 }, 176 { 177 .offset = 0x1800, 178 .skpcr_mask = 0, 179 .devid = SA1111_DEVID_PCMCIA, 180 .irq = { 181 IRQ_S0_READY_NINT, 182 IRQ_S0_CD_VALID, 183 IRQ_S0_BVD1_STSCHG, 184 IRQ_S1_READY_NINT, 185 IRQ_S1_CD_VALID, 186 IRQ_S1_BVD1_STSCHG, 187 }, 188 }, 189}; 190 191/* 192 * SA1111 interrupt support. Since clearing an IRQ while there are 193 * active IRQs causes the interrupt output to pulse, the upper levels 194 * will call us again if there are more interrupts to process. 195 */ 196static void 197sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) 198{ 199 unsigned int stat0, stat1, i; 200 struct sa1111 *sachip = irq_get_handler_data(irq); 201 void __iomem *mapbase = sachip->base + SA1111_INTC; 202 203 stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); 204 stat1 = sa1111_readl(mapbase + SA1111_INTSTATCLR1); 205 206 sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0); 207 208 desc->irq_data.chip->irq_ack(&desc->irq_data); 209 210 sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1); 211 212 if (stat0 == 0 && stat1 == 0) { 213 do_bad_IRQ(irq, desc); 214 return; 215 } 216 217 for (i = 0; stat0; i++, stat0 >>= 1) 218 if (stat0 & 1) 219 generic_handle_irq(i + sachip->irq_base); 220 221 for (i = 32; stat1; i++, stat1 >>= 1) 222 if (stat1 & 1) 223 generic_handle_irq(i + sachip->irq_base); 224 225 /* For level-based interrupts */ 226 desc->irq_data.chip->irq_unmask(&desc->irq_data); 227} 228 229#define SA1111_IRQMASK_LO(x) (1 << (x - sachip->irq_base)) 230#define SA1111_IRQMASK_HI(x) (1 << (x - sachip->irq_base - 32)) 231 232static void sa1111_ack_irq(struct irq_data *d) 233{ 234} 235 236static void sa1111_mask_lowirq(struct irq_data *d) 237{ 238 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 239 void __iomem *mapbase = sachip->base + SA1111_INTC; 240 unsigned long ie0; 241 242 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 243 ie0 &= ~SA1111_IRQMASK_LO(d->irq); 244 writel(ie0, mapbase + SA1111_INTEN0); 245} 246 247static void sa1111_unmask_lowirq(struct irq_data *d) 248{ 249 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 250 void __iomem *mapbase = sachip->base + SA1111_INTC; 251 unsigned long ie0; 252 253 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 254 ie0 |= SA1111_IRQMASK_LO(d->irq); 255 sa1111_writel(ie0, mapbase + SA1111_INTEN0); 256} 257 258/* 259 * Attempt to re-trigger the interrupt. The SA1111 contains a register 260 * (INTSET) which claims to do this. However, in practice no amount of 261 * manipulation of INTEN and INTSET guarantees that the interrupt will 262 * be triggered. In fact, its very difficult, if not impossible to get 263 * INTSET to re-trigger the interrupt. 264 */ 265static int sa1111_retrigger_lowirq(struct irq_data *d) 266{ 267 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 268 void __iomem *mapbase = sachip->base + SA1111_INTC; 269 unsigned int mask = SA1111_IRQMASK_LO(d->irq); 270 unsigned long ip0; 271 int i; 272 273 ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); 274 for (i = 0; i < 8; i++) { 275 sa1111_writel(ip0 ^ mask, mapbase + SA1111_INTPOL0); 276 sa1111_writel(ip0, mapbase + SA1111_INTPOL0); 277 if (sa1111_readl(mapbase + SA1111_INTSTATCLR0) & mask) 278 break; 279 } 280 281 if (i == 8) 282 printk(KERN_ERR "Danger Will Robinson: failed to " 283 "re-trigger IRQ%d\n", d->irq); 284 return i == 8 ? -1 : 0; 285} 286 287static int sa1111_type_lowirq(struct irq_data *d, unsigned int flags) 288{ 289 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 290 void __iomem *mapbase = sachip->base + SA1111_INTC; 291 unsigned int mask = SA1111_IRQMASK_LO(d->irq); 292 unsigned long ip0; 293 294 if (flags == IRQ_TYPE_PROBE) 295 return 0; 296 297 if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) 298 return -EINVAL; 299 300 ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); 301 if (flags & IRQ_TYPE_EDGE_RISING) 302 ip0 &= ~mask; 303 else 304 ip0 |= mask; 305 sa1111_writel(ip0, mapbase + SA1111_INTPOL0); 306 sa1111_writel(ip0, mapbase + SA1111_WAKEPOL0); 307 308 return 0; 309} 310 311static int sa1111_wake_lowirq(struct irq_data *d, unsigned int on) 312{ 313 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 314 void __iomem *mapbase = sachip->base + SA1111_INTC; 315 unsigned int mask = SA1111_IRQMASK_LO(d->irq); 316 unsigned long we0; 317 318 we0 = sa1111_readl(mapbase + SA1111_WAKEEN0); 319 if (on) 320 we0 |= mask; 321 else 322 we0 &= ~mask; 323 sa1111_writel(we0, mapbase + SA1111_WAKEEN0); 324 325 return 0; 326} 327 328static struct irq_chip sa1111_low_chip = { 329 .name = "SA1111-l", 330 .irq_ack = sa1111_ack_irq, 331 .irq_mask = sa1111_mask_lowirq, 332 .irq_unmask = sa1111_unmask_lowirq, 333 .irq_retrigger = sa1111_retrigger_lowirq, 334 .irq_set_type = sa1111_type_lowirq, 335 .irq_set_wake = sa1111_wake_lowirq, 336}; 337 338static void sa1111_mask_highirq(struct irq_data *d) 339{ 340 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 341 void __iomem *mapbase = sachip->base + SA1111_INTC; 342 unsigned long ie1; 343 344 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 345 ie1 &= ~SA1111_IRQMASK_HI(d->irq); 346 sa1111_writel(ie1, mapbase + SA1111_INTEN1); 347} 348 349static void sa1111_unmask_highirq(struct irq_data *d) 350{ 351 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 352 void __iomem *mapbase = sachip->base + SA1111_INTC; 353 unsigned long ie1; 354 355 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 356 ie1 |= SA1111_IRQMASK_HI(d->irq); 357 sa1111_writel(ie1, mapbase + SA1111_INTEN1); 358} 359 360/* 361 * Attempt to re-trigger the interrupt. The SA1111 contains a register 362 * (INTSET) which claims to do this. However, in practice no amount of 363 * manipulation of INTEN and INTSET guarantees that the interrupt will 364 * be triggered. In fact, its very difficult, if not impossible to get 365 * INTSET to re-trigger the interrupt. 366 */ 367static int sa1111_retrigger_highirq(struct irq_data *d) 368{ 369 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 370 void __iomem *mapbase = sachip->base + SA1111_INTC; 371 unsigned int mask = SA1111_IRQMASK_HI(d->irq); 372 unsigned long ip1; 373 int i; 374 375 ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); 376 for (i = 0; i < 8; i++) { 377 sa1111_writel(ip1 ^ mask, mapbase + SA1111_INTPOL1); 378 sa1111_writel(ip1, mapbase + SA1111_INTPOL1); 379 if (sa1111_readl(mapbase + SA1111_INTSTATCLR1) & mask) 380 break; 381 } 382 383 if (i == 8) 384 printk(KERN_ERR "Danger Will Robinson: failed to " 385 "re-trigger IRQ%d\n", d->irq); 386 return i == 8 ? -1 : 0; 387} 388 389static int sa1111_type_highirq(struct irq_data *d, unsigned int flags) 390{ 391 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 392 void __iomem *mapbase = sachip->base + SA1111_INTC; 393 unsigned int mask = SA1111_IRQMASK_HI(d->irq); 394 unsigned long ip1; 395 396 if (flags == IRQ_TYPE_PROBE) 397 return 0; 398 399 if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) 400 return -EINVAL; 401 402 ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); 403 if (flags & IRQ_TYPE_EDGE_RISING) 404 ip1 &= ~mask; 405 else 406 ip1 |= mask; 407 sa1111_writel(ip1, mapbase + SA1111_INTPOL1); 408 sa1111_writel(ip1, mapbase + SA1111_WAKEPOL1); 409 410 return 0; 411} 412 413static int sa1111_wake_highirq(struct irq_data *d, unsigned int on) 414{ 415 struct sa1111 *sachip = irq_data_get_irq_chip_data(d); 416 void __iomem *mapbase = sachip->base + SA1111_INTC; 417 unsigned int mask = SA1111_IRQMASK_HI(d->irq); 418 unsigned long we1; 419 420 we1 = sa1111_readl(mapbase + SA1111_WAKEEN1); 421 if (on) 422 we1 |= mask; 423 else 424 we1 &= ~mask; 425 sa1111_writel(we1, mapbase + SA1111_WAKEEN1); 426 427 return 0; 428} 429 430static struct irq_chip sa1111_high_chip = { 431 .name = "SA1111-h", 432 .irq_ack = sa1111_ack_irq, 433 .irq_mask = sa1111_mask_highirq, 434 .irq_unmask = sa1111_unmask_highirq, 435 .irq_retrigger = sa1111_retrigger_highirq, 436 .irq_set_type = sa1111_type_highirq, 437 .irq_set_wake = sa1111_wake_highirq, 438}; 439 440static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) 441{ 442 void __iomem *irqbase = sachip->base + SA1111_INTC; 443 unsigned i, irq; 444 int ret; 445 446 /* 447 * We're guaranteed that this region hasn't been taken. 448 */ 449 request_mem_region(sachip->phys + SA1111_INTC, 512, "irq"); 450 451 ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1); 452 if (ret <= 0) { 453 dev_err(sachip->dev, "unable to allocate %u irqs: %d\n", 454 SA1111_IRQ_NR, ret); 455 if (ret == 0) 456 ret = -EINVAL; 457 return ret; 458 } 459 460 sachip->irq_base = ret; 461 462 /* disable all IRQs */ 463 sa1111_writel(0, irqbase + SA1111_INTEN0); 464 sa1111_writel(0, irqbase + SA1111_INTEN1); 465 sa1111_writel(0, irqbase + SA1111_WAKEEN0); 466 sa1111_writel(0, irqbase + SA1111_WAKEEN1); 467 468 /* 469 * detect on rising edge. Note: Feb 2001 Errata for SA1111 470 * specifies that S0ReadyInt and S1ReadyInt should be '1'. 471 */ 472 sa1111_writel(0, irqbase + SA1111_INTPOL0); 473 sa1111_writel(SA1111_IRQMASK_HI(IRQ_S0_READY_NINT) | 474 SA1111_IRQMASK_HI(IRQ_S1_READY_NINT), 475 irqbase + SA1111_INTPOL1); 476 477 /* clear all IRQs */ 478 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0); 479 sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); 480 481 for (i = IRQ_GPAIN0; i <= SSPROR; i++) { 482 irq = sachip->irq_base + i; 483 irq_set_chip_and_handler(irq, &sa1111_low_chip, 484 handle_edge_irq); 485 irq_set_chip_data(irq, sachip); 486 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 487 } 488 489 for (i = AUDXMTDMADONEA; i <= IRQ_S1_BVD1_STSCHG; i++) { 490 irq = sachip->irq_base + i; 491 irq_set_chip_and_handler(irq, &sa1111_high_chip, 492 handle_edge_irq); 493 irq_set_chip_data(irq, sachip); 494 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 495 } 496 497 /* 498 * Register SA1111 interrupt 499 */ 500 irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); 501 irq_set_handler_data(sachip->irq, sachip); 502 irq_set_chained_handler(sachip->irq, sa1111_irq_handler); 503 504 dev_info(sachip->dev, "Providing IRQ%u-%u\n", 505 sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1); 506 507 return 0; 508} 509 510/* 511 * Bring the SA1111 out of reset. This requires a set procedure: 512 * 1. nRESET asserted (by hardware) 513 * 2. CLK turned on from SA1110 514 * 3. nRESET deasserted 515 * 4. VCO turned on, PLL_BYPASS turned off 516 * 5. Wait lock time, then assert RCLKEn 517 * 7. PCR set to allow clocking of individual functions 518 * 519 * Until we've done this, the only registers we can access are: 520 * SBI_SKCR 521 * SBI_SMCR 522 * SBI_SKID 523 */ 524static void sa1111_wake(struct sa1111 *sachip) 525{ 526 unsigned long flags, r; 527 528 spin_lock_irqsave(&sachip->lock, flags); 529 530 clk_enable(sachip->clk); 531 532 /* 533 * Turn VCO on, and disable PLL Bypass. 534 */ 535 r = sa1111_readl(sachip->base + SA1111_SKCR); 536 r &= ~SKCR_VCO_OFF; 537 sa1111_writel(r, sachip->base + SA1111_SKCR); 538 r |= SKCR_PLL_BYPASS | SKCR_OE_EN; 539 sa1111_writel(r, sachip->base + SA1111_SKCR); 540 541 /* 542 * Wait lock time. SA1111 manual _doesn't_ 543 * specify a figure for this! We choose 100us. 544 */ 545 udelay(100); 546 547 /* 548 * Enable RCLK. We also ensure that RDYEN is set. 549 */ 550 r |= SKCR_RCLKEN | SKCR_RDYEN; 551 sa1111_writel(r, sachip->base + SA1111_SKCR); 552 553 /* 554 * Wait 14 RCLK cycles for the chip to finish coming out 555 * of reset. (RCLK=24MHz). This is 590ns. 556 */ 557 udelay(1); 558 559 /* 560 * Ensure all clocks are initially off. 561 */ 562 sa1111_writel(0, sachip->base + SA1111_SKPCR); 563 564 spin_unlock_irqrestore(&sachip->lock, flags); 565} 566 567#ifdef CONFIG_ARCH_SA1100 568 569static u32 sa1111_dma_mask[] = { 570 ~0, 571 ~(1 << 20), 572 ~(1 << 23), 573 ~(1 << 24), 574 ~(1 << 25), 575 ~(1 << 20), 576 ~(1 << 20), 577 0, 578}; 579 580/* 581 * Configure the SA1111 shared memory controller. 582 */ 583void 584sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac, 585 unsigned int cas_latency) 586{ 587 unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC); 588 589 if (cas_latency == 3) 590 smcr |= SMCR_CLAT; 591 592 sa1111_writel(smcr, sachip->base + SA1111_SMCR); 593 594 /* 595 * Now clear the bits in the DMA mask to work around the SA1111 596 * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion 597 * Chip Specification Update, June 2000, Erratum #7). 598 */ 599 if (sachip->dev->dma_mask) 600 *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2]; 601 602 sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2]; 603} 604#endif 605 606#ifdef CONFIG_DMABOUNCE 607/* 608 * According to the "Intel StrongARM SA-1111 Microprocessor Companion 609 * Chip Specification Update" (June 2000), erratum #7, there is a 610 * significant bug in the SA1111 SDRAM shared memory controller. If 611 * an access to a region of memory above 1MB relative to the bank base, 612 * it is important that address bit 10 _NOT_ be asserted. Depending 613 * on the configuration of the RAM, bit 10 may correspond to one 614 * of several different (processor-relative) address bits. 615 * 616 * This routine only identifies whether or not a given DMA address 617 * is susceptible to the bug. 618 * 619 * This should only get called for sa1111_device types due to the 620 * way we configure our device dma_masks. 621 */ 622static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) 623{ 624 /* 625 * Section 4.6 of the "Intel StrongARM SA-1111 Development Module 626 * User's Guide" mentions that jumpers R51 and R52 control the 627 * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or 628 * SDRAM bank 1 on Neponset). The default configuration selects 629 * Assabet, so any address in bank 1 is necessarily invalid. 630 */ 631 return (machine_is_assabet() || machine_is_pfs168()) && 632 (addr >= 0xc8000000 || (addr + size) >= 0xc8000000); 633} 634#endif 635 636static void sa1111_dev_release(struct device *_dev) 637{ 638 struct sa1111_dev *dev = SA1111_DEV(_dev); 639 640 release_resource(&dev->res); 641 kfree(dev); 642} 643 644static int 645sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent, 646 struct sa1111_dev_info *info) 647{ 648 struct sa1111_dev *dev; 649 unsigned i; 650 int ret; 651 652 dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL); 653 if (!dev) { 654 ret = -ENOMEM; 655 goto out; 656 } 657 658 dev_set_name(&dev->dev, "%4.4lx", info->offset); 659 dev->devid = info->devid; 660 dev->dev.parent = sachip->dev; 661 dev->dev.bus = &sa1111_bus_type; 662 dev->dev.release = sa1111_dev_release; 663 dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask; 664 dev->res.start = sachip->phys + info->offset; 665 dev->res.end = dev->res.start + 511; 666 dev->res.name = dev_name(&dev->dev); 667 dev->res.flags = IORESOURCE_MEM; 668 dev->mapbase = sachip->base + info->offset; 669 dev->skpcr_mask = info->skpcr_mask; 670 671 for (i = 0; i < ARRAY_SIZE(info->irq); i++) 672 dev->irq[i] = sachip->irq_base + info->irq[i]; 673 674 ret = request_resource(parent, &dev->res); 675 if (ret) { 676 printk("SA1111: failed to allocate resource for %s\n", 677 dev->res.name); 678 dev_set_name(&dev->dev, NULL); 679 kfree(dev); 680 goto out; 681 } 682 683 684 ret = device_register(&dev->dev); 685 if (ret) { 686 release_resource(&dev->res); 687 kfree(dev); 688 goto out; 689 } 690 691#ifdef CONFIG_DMABOUNCE 692 /* 693 * If the parent device has a DMA mask associated with it, 694 * propagate it down to the children. 695 */ 696 if (sachip->dev->dma_mask) { 697 dev->dma_mask = *sachip->dev->dma_mask; 698 dev->dev.dma_mask = &dev->dma_mask; 699 700 if (dev->dma_mask != 0xffffffffUL) { 701 ret = dmabounce_register_dev(&dev->dev, 1024, 4096, 702 sa1111_needs_bounce); 703 if (ret) { 704 dev_err(&dev->dev, "SA1111: Failed to register" 705 " with dmabounce\n"); 706 device_unregister(&dev->dev); 707 } 708 } 709 } 710#endif 711 712out: 713 return ret; 714} 715 716/** 717 * sa1111_probe - probe for a single SA1111 chip. 718 * @phys_addr: physical address of device. 719 * 720 * Probe for a SA1111 chip. This must be called 721 * before any other SA1111-specific code. 722 * 723 * Returns: 724 * %-ENODEV device not found. 725 * %-EBUSY physical address already marked in-use. 726 * %-EINVAL no platform data passed 727 * %0 successful. 728 */ 729static int __devinit 730__sa1111_probe(struct device *me, struct resource *mem, int irq) 731{ 732 struct sa1111_platform_data *pd = me->platform_data; 733 struct sa1111 *sachip; 734 unsigned long id; 735 unsigned int has_devs; 736 int i, ret = -ENODEV; 737 738 if (!pd) 739 return -EINVAL; 740 741 sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL); 742 if (!sachip) 743 return -ENOMEM; 744 745 sachip->clk = clk_get(me, "SA1111_CLK"); 746 if (IS_ERR(sachip->clk)) { 747 ret = PTR_ERR(sachip->clk); 748 goto err_free; 749 } 750 751 ret = clk_prepare(sachip->clk); 752 if (ret) 753 goto err_clkput; 754 755 spin_lock_init(&sachip->lock); 756 757 sachip->dev = me; 758 dev_set_drvdata(sachip->dev, sachip); 759 760 sachip->pdata = pd; 761 sachip->phys = mem->start; 762 sachip->irq = irq; 763 764 /* 765 * Map the whole region. This also maps the 766 * registers for our children. 767 */ 768 sachip->base = ioremap(mem->start, PAGE_SIZE * 2); 769 if (!sachip->base) { 770 ret = -ENOMEM; 771 goto err_clk_unprep; 772 } 773 774 /* 775 * Probe for the chip. Only touch the SBI registers. 776 */ 777 id = sa1111_readl(sachip->base + SA1111_SKID); 778 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { 779 printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id); 780 ret = -ENODEV; 781 goto err_unmap; 782 } 783 784 printk(KERN_INFO "SA1111 Microprocessor Companion Chip: " 785 "silicon revision %lx, metal revision %lx\n", 786 (id & SKID_SIREV_MASK)>>4, (id & SKID_MTREV_MASK)); 787 788 /* 789 * We found it. Wake the chip up, and initialise. 790 */ 791 sa1111_wake(sachip); 792 793 /* 794 * The interrupt controller must be initialised before any 795 * other device to ensure that the interrupts are available. 796 */ 797 if (sachip->irq != NO_IRQ) { 798 ret = sa1111_setup_irq(sachip, pd->irq_base); 799 if (ret) 800 goto err_unmap; 801 } 802 803#ifdef CONFIG_ARCH_SA1100 804 { 805 unsigned int val; 806 807 /* 808 * The SDRAM configuration of the SA1110 and the SA1111 must 809 * match. This is very important to ensure that SA1111 accesses 810 * don't corrupt the SDRAM. Note that this ungates the SA1111's 811 * MBGNT signal, so we must have called sa1110_mb_disable() 812 * beforehand. 813 */ 814 sa1111_configure_smc(sachip, 1, 815 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), 816 FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); 817 818 /* 819 * We only need to turn on DCLK whenever we want to use the 820 * DMA. It can otherwise be held firmly in the off position. 821 * (currently, we always enable it.) 822 */ 823 val = sa1111_readl(sachip->base + SA1111_SKPCR); 824 sa1111_writel(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR); 825 826 /* 827 * Enable the SA1110 memory bus request and grant signals. 828 */ 829 sa1110_mb_enable(); 830 } 831#endif 832 833 g_sa1111 = sachip; 834 835 has_devs = ~0; 836 if (machine_is_assabet() || machine_is_jornada720() || 837 machine_is_badge4()) 838 has_devs &= ~SA1111_DEVID_PS2_MSE; 839 else 840 has_devs &= ~SA1111_DEVID_SAC; 841 842 for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++) 843 if (sa1111_devices[i].devid & has_devs) 844 sa1111_init_one_child(sachip, mem, &sa1111_devices[i]); 845 846 return 0; 847 848 err_unmap: 849 iounmap(sachip->base); 850 err_clk_unprep: 851 clk_unprepare(sachip->clk); 852 err_clkput: 853 clk_put(sachip->clk); 854 err_free: 855 kfree(sachip); 856 return ret; 857} 858 859static int sa1111_remove_one(struct device *dev, void *data) 860{ 861 device_unregister(dev); 862 return 0; 863} 864 865static void __sa1111_remove(struct sa1111 *sachip) 866{ 867 void __iomem *irqbase = sachip->base + SA1111_INTC; 868 869 device_for_each_child(sachip->dev, NULL, sa1111_remove_one); 870 871 /* disable all IRQs */ 872 sa1111_writel(0, irqbase + SA1111_INTEN0); 873 sa1111_writel(0, irqbase + SA1111_INTEN1); 874 sa1111_writel(0, irqbase + SA1111_WAKEEN0); 875 sa1111_writel(0, irqbase + SA1111_WAKEEN1); 876 877 clk_disable(sachip->clk); 878 clk_unprepare(sachip->clk); 879 880 if (sachip->irq != NO_IRQ) { 881 irq_set_chained_handler(sachip->irq, NULL); 882 irq_set_handler_data(sachip->irq, NULL); 883 irq_free_descs(sachip->irq_base, SA1111_IRQ_NR); 884 885 release_mem_region(sachip->phys + SA1111_INTC, 512); 886 } 887 888 iounmap(sachip->base); 889 clk_put(sachip->clk); 890 kfree(sachip); 891} 892 893struct sa1111_save_data { 894 unsigned int skcr; 895 unsigned int skpcr; 896 unsigned int skcdr; 897 unsigned char skaud; 898 unsigned char skpwm0; 899 unsigned char skpwm1; 900 901 /* 902 * Interrupt controller 903 */ 904 unsigned int intpol0; 905 unsigned int intpol1; 906 unsigned int inten0; 907 unsigned int inten1; 908 unsigned int wakepol0; 909 unsigned int wakepol1; 910 unsigned int wakeen0; 911 unsigned int wakeen1; 912}; 913 914#ifdef CONFIG_PM 915 916static int sa1111_suspend(struct platform_device *dev, pm_message_t state) 917{ 918 struct sa1111 *sachip = platform_get_drvdata(dev); 919 struct sa1111_save_data *save; 920 unsigned long flags; 921 unsigned int val; 922 void __iomem *base; 923 924 save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL); 925 if (!save) 926 return -ENOMEM; 927 sachip->saved_state = save; 928 929 spin_lock_irqsave(&sachip->lock, flags); 930 931 /* 932 * Save state. 933 */ 934 base = sachip->base; 935 save->skcr = sa1111_readl(base + SA1111_SKCR); 936 save->skpcr = sa1111_readl(base + SA1111_SKPCR); 937 save->skcdr = sa1111_readl(base + SA1111_SKCDR); 938 save->skaud = sa1111_readl(base + SA1111_SKAUD); 939 save->skpwm0 = sa1111_readl(base + SA1111_SKPWM0); 940 save->skpwm1 = sa1111_readl(base + SA1111_SKPWM1); 941 942 sa1111_writel(0, sachip->base + SA1111_SKPWM0); 943 sa1111_writel(0, sachip->base + SA1111_SKPWM1); 944 945 base = sachip->base + SA1111_INTC; 946 save->intpol0 = sa1111_readl(base + SA1111_INTPOL0); 947 save->intpol1 = sa1111_readl(base + SA1111_INTPOL1); 948 save->inten0 = sa1111_readl(base + SA1111_INTEN0); 949 save->inten1 = sa1111_readl(base + SA1111_INTEN1); 950 save->wakepol0 = sa1111_readl(base + SA1111_WAKEPOL0); 951 save->wakepol1 = sa1111_readl(base + SA1111_WAKEPOL1); 952 save->wakeen0 = sa1111_readl(base + SA1111_WAKEEN0); 953 save->wakeen1 = sa1111_readl(base + SA1111_WAKEEN1); 954 955 /* 956 * Disable. 957 */ 958 val = sa1111_readl(sachip->base + SA1111_SKCR); 959 sa1111_writel(val | SKCR_SLEEP, sachip->base + SA1111_SKCR); 960 961 clk_disable(sachip->clk); 962 963 spin_unlock_irqrestore(&sachip->lock, flags); 964 965#ifdef CONFIG_ARCH_SA1100 966 sa1110_mb_disable(); 967#endif 968 969 return 0; 970} 971 972/* 973 * sa1111_resume - Restore the SA1111 device state. 974 * @dev: device to restore 975 * 976 * Restore the general state of the SA1111; clock control and 977 * interrupt controller. Other parts of the SA1111 must be 978 * restored by their respective drivers, and must be called 979 * via LDM after this function. 980 */ 981static int sa1111_resume(struct platform_device *dev) 982{ 983 struct sa1111 *sachip = platform_get_drvdata(dev); 984 struct sa1111_save_data *save; 985 unsigned long flags, id; 986 void __iomem *base; 987 988 save = sachip->saved_state; 989 if (!save) 990 return 0; 991 992 /* 993 * Ensure that the SA1111 is still here. 994 * FIXME: shouldn't do this here. 995 */ 996 id = sa1111_readl(sachip->base + SA1111_SKID); 997 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { 998 __sa1111_remove(sachip); 999 platform_set_drvdata(dev, NULL); 1000 kfree(save); 1001 return 0; 1002 } 1003 1004 /* 1005 * First of all, wake up the chip. 1006 */ 1007 sa1111_wake(sachip); 1008 1009#ifdef CONFIG_ARCH_SA1100 1010 /* Enable the memory bus request/grant signals */ 1011 sa1110_mb_enable(); 1012#endif 1013 1014 /* 1015 * Only lock for write ops. Also, sa1111_wake must be called with 1016 * released spinlock! 1017 */ 1018 spin_lock_irqsave(&sachip->lock, flags); 1019 1020 sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN0); 1021 sa1111_writel(0, sachip->base + SA1111_INTC + SA1111_INTEN1); 1022 1023 base = sachip->base; 1024 sa1111_writel(save->skcr, base + SA1111_SKCR); 1025 sa1111_writel(save->skpcr, base + SA1111_SKPCR); 1026 sa1111_writel(save->skcdr, base + SA1111_SKCDR); 1027 sa1111_writel(save->skaud, base + SA1111_SKAUD); 1028 sa1111_writel(save->skpwm0, base + SA1111_SKPWM0); 1029 sa1111_writel(save->skpwm1, base + SA1111_SKPWM1); 1030 1031 base = sachip->base + SA1111_INTC; 1032 sa1111_writel(save->intpol0, base + SA1111_INTPOL0); 1033 sa1111_writel(save->intpol1, base + SA1111_INTPOL1); 1034 sa1111_writel(save->inten0, base + SA1111_INTEN0); 1035 sa1111_writel(save->inten1, base + SA1111_INTEN1); 1036 sa1111_writel(save->wakepol0, base + SA1111_WAKEPOL0); 1037 sa1111_writel(save->wakepol1, base + SA1111_WAKEPOL1); 1038 sa1111_writel(save->wakeen0, base + SA1111_WAKEEN0); 1039 sa1111_writel(save->wakeen1, base + SA1111_WAKEEN1); 1040 1041 spin_unlock_irqrestore(&sachip->lock, flags); 1042 1043 sachip->saved_state = NULL; 1044 kfree(save); 1045 1046 return 0; 1047} 1048 1049#else 1050#define sa1111_suspend NULL 1051#define sa1111_resume NULL 1052#endif 1053 1054static int __devinit sa1111_probe(struct platform_device *pdev) 1055{ 1056 struct resource *mem; 1057 int irq; 1058 1059 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1060 if (!mem) 1061 return -EINVAL; 1062 irq = platform_get_irq(pdev, 0); 1063 if (irq < 0) 1064 return -ENXIO; 1065 1066 return __sa1111_probe(&pdev->dev, mem, irq); 1067} 1068 1069static int sa1111_remove(struct platform_device *pdev) 1070{ 1071 struct sa1111 *sachip = platform_get_drvdata(pdev); 1072 1073 if (sachip) { 1074#ifdef CONFIG_PM 1075 kfree(sachip->saved_state); 1076 sachip->saved_state = NULL; 1077#endif 1078 __sa1111_remove(sachip); 1079 platform_set_drvdata(pdev, NULL); 1080 } 1081 1082 return 0; 1083} 1084 1085/* 1086 * Not sure if this should be on the system bus or not yet. 1087 * We really want some way to register a system device at 1088 * the per-machine level, and then have this driver pick 1089 * up the registered devices. 1090 * 1091 * We also need to handle the SDRAM configuration for 1092 * PXA250/SA1110 machine classes. 1093 */ 1094static struct platform_driver sa1111_device_driver = { 1095 .probe = sa1111_probe, 1096 .remove = sa1111_remove, 1097 .suspend = sa1111_suspend, 1098 .resume = sa1111_resume, 1099 .driver = { 1100 .name = "sa1111", 1101 .owner = THIS_MODULE, 1102 }, 1103}; 1104 1105/* 1106 * Get the parent device driver (us) structure 1107 * from a child function device 1108 */ 1109static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev) 1110{ 1111 return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent); 1112} 1113 1114/* 1115 * The bits in the opdiv field are non-linear. 1116 */ 1117static unsigned char opdiv_table[] = { 1, 4, 2, 8 }; 1118 1119static unsigned int __sa1111_pll_clock(struct sa1111 *sachip) 1120{ 1121 unsigned int skcdr, fbdiv, ipdiv, opdiv; 1122 1123 skcdr = sa1111_readl(sachip->base + SA1111_SKCDR); 1124 1125 fbdiv = (skcdr & 0x007f) + 2; 1126 ipdiv = ((skcdr & 0x0f80) >> 7) + 2; 1127 opdiv = opdiv_table[(skcdr & 0x3000) >> 12]; 1128 1129 return 3686400 * fbdiv / (ipdiv * opdiv); 1130} 1131 1132/** 1133 * sa1111_pll_clock - return the current PLL clock frequency. 1134 * @sadev: SA1111 function block 1135 * 1136 * BUG: we should look at SKCR. We also blindly believe that 1137 * the chip is being fed with the 3.6864MHz clock. 1138 * 1139 * Returns the PLL clock in Hz. 1140 */ 1141unsigned int sa1111_pll_clock(struct sa1111_dev *sadev) 1142{ 1143 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1144 1145 return __sa1111_pll_clock(sachip); 1146} 1147EXPORT_SYMBOL(sa1111_pll_clock); 1148 1149/** 1150 * sa1111_select_audio_mode - select I2S or AC link mode 1151 * @sadev: SA1111 function block 1152 * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S 1153 * 1154 * Frob the SKCR to select AC Link mode or I2S mode for 1155 * the audio block. 1156 */ 1157void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode) 1158{ 1159 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1160 unsigned long flags; 1161 unsigned int val; 1162 1163 spin_lock_irqsave(&sachip->lock, flags); 1164 1165 val = sa1111_readl(sachip->base + SA1111_SKCR); 1166 if (mode == SA1111_AUDIO_I2S) { 1167 val &= ~SKCR_SELAC; 1168 } else { 1169 val |= SKCR_SELAC; 1170 } 1171 sa1111_writel(val, sachip->base + SA1111_SKCR); 1172 1173 spin_unlock_irqrestore(&sachip->lock, flags); 1174} 1175EXPORT_SYMBOL(sa1111_select_audio_mode); 1176 1177/** 1178 * sa1111_set_audio_rate - set the audio sample rate 1179 * @sadev: SA1111 SAC function block 1180 * @rate: sample rate to select 1181 */ 1182int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate) 1183{ 1184 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1185 unsigned int div; 1186 1187 if (sadev->devid != SA1111_DEVID_SAC) 1188 return -EINVAL; 1189 1190 div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate; 1191 if (div == 0) 1192 div = 1; 1193 if (div > 128) 1194 div = 128; 1195 1196 sa1111_writel(div - 1, sachip->base + SA1111_SKAUD); 1197 1198 return 0; 1199} 1200EXPORT_SYMBOL(sa1111_set_audio_rate); 1201 1202/** 1203 * sa1111_get_audio_rate - get the audio sample rate 1204 * @sadev: SA1111 SAC function block device 1205 */ 1206int sa1111_get_audio_rate(struct sa1111_dev *sadev) 1207{ 1208 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1209 unsigned long div; 1210 1211 if (sadev->devid != SA1111_DEVID_SAC) 1212 return -EINVAL; 1213 1214 div = sa1111_readl(sachip->base + SA1111_SKAUD) + 1; 1215 1216 return __sa1111_pll_clock(sachip) / (256 * div); 1217} 1218EXPORT_SYMBOL(sa1111_get_audio_rate); 1219 1220void sa1111_set_io_dir(struct sa1111_dev *sadev, 1221 unsigned int bits, unsigned int dir, 1222 unsigned int sleep_dir) 1223{ 1224 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1225 unsigned long flags; 1226 unsigned int val; 1227 void __iomem *gpio = sachip->base + SA1111_GPIO; 1228 1229#define MODIFY_BITS(port, mask, dir) \ 1230 if (mask) { \ 1231 val = sa1111_readl(port); \ 1232 val &= ~(mask); \ 1233 val |= (dir) & (mask); \ 1234 sa1111_writel(val, port); \ 1235 } 1236 1237 spin_lock_irqsave(&sachip->lock, flags); 1238 MODIFY_BITS(gpio + SA1111_GPIO_PADDR, bits & 15, dir); 1239 MODIFY_BITS(gpio + SA1111_GPIO_PBDDR, (bits >> 8) & 255, dir >> 8); 1240 MODIFY_BITS(gpio + SA1111_GPIO_PCDDR, (bits >> 16) & 255, dir >> 16); 1241 1242 MODIFY_BITS(gpio + SA1111_GPIO_PASDR, bits & 15, sleep_dir); 1243 MODIFY_BITS(gpio + SA1111_GPIO_PBSDR, (bits >> 8) & 255, sleep_dir >> 8); 1244 MODIFY_BITS(gpio + SA1111_GPIO_PCSDR, (bits >> 16) & 255, sleep_dir >> 16); 1245 spin_unlock_irqrestore(&sachip->lock, flags); 1246} 1247EXPORT_SYMBOL(sa1111_set_io_dir); 1248 1249void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v) 1250{ 1251 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1252 unsigned long flags; 1253 unsigned int val; 1254 void __iomem *gpio = sachip->base + SA1111_GPIO; 1255 1256 spin_lock_irqsave(&sachip->lock, flags); 1257 MODIFY_BITS(gpio + SA1111_GPIO_PADWR, bits & 15, v); 1258 MODIFY_BITS(gpio + SA1111_GPIO_PBDWR, (bits >> 8) & 255, v >> 8); 1259 MODIFY_BITS(gpio + SA1111_GPIO_PCDWR, (bits >> 16) & 255, v >> 16); 1260 spin_unlock_irqrestore(&sachip->lock, flags); 1261} 1262EXPORT_SYMBOL(sa1111_set_io); 1263 1264void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v) 1265{ 1266 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1267 unsigned long flags; 1268 unsigned int val; 1269 void __iomem *gpio = sachip->base + SA1111_GPIO; 1270 1271 spin_lock_irqsave(&sachip->lock, flags); 1272 MODIFY_BITS(gpio + SA1111_GPIO_PASSR, bits & 15, v); 1273 MODIFY_BITS(gpio + SA1111_GPIO_PBSSR, (bits >> 8) & 255, v >> 8); 1274 MODIFY_BITS(gpio + SA1111_GPIO_PCSSR, (bits >> 16) & 255, v >> 16); 1275 spin_unlock_irqrestore(&sachip->lock, flags); 1276} 1277EXPORT_SYMBOL(sa1111_set_sleep_io); 1278 1279/* 1280 * Individual device operations. 1281 */ 1282 1283/** 1284 * sa1111_enable_device - enable an on-chip SA1111 function block 1285 * @sadev: SA1111 function block device to enable 1286 */ 1287int sa1111_enable_device(struct sa1111_dev *sadev) 1288{ 1289 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1290 unsigned long flags; 1291 unsigned int val; 1292 int ret = 0; 1293 1294 if (sachip->pdata && sachip->pdata->enable) 1295 ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid); 1296 1297 if (ret == 0) { 1298 spin_lock_irqsave(&sachip->lock, flags); 1299 val = sa1111_readl(sachip->base + SA1111_SKPCR); 1300 sa1111_writel(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR); 1301 spin_unlock_irqrestore(&sachip->lock, flags); 1302 } 1303 return ret; 1304} 1305EXPORT_SYMBOL(sa1111_enable_device); 1306 1307/** 1308 * sa1111_disable_device - disable an on-chip SA1111 function block 1309 * @sadev: SA1111 function block device to disable 1310 */ 1311void sa1111_disable_device(struct sa1111_dev *sadev) 1312{ 1313 struct sa1111 *sachip = sa1111_chip_driver(sadev); 1314 unsigned long flags; 1315 unsigned int val; 1316 1317 spin_lock_irqsave(&sachip->lock, flags); 1318 val = sa1111_readl(sachip->base + SA1111_SKPCR); 1319 sa1111_writel(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR); 1320 spin_unlock_irqrestore(&sachip->lock, flags); 1321 1322 if (sachip->pdata && sachip->pdata->disable) 1323 sachip->pdata->disable(sachip->pdata->data, sadev->devid); 1324} 1325EXPORT_SYMBOL(sa1111_disable_device); 1326 1327/* 1328 * SA1111 "Register Access Bus." 1329 * 1330 * We model this as a regular bus type, and hang devices directly 1331 * off this. 1332 */ 1333static int sa1111_match(struct device *_dev, struct device_driver *_drv) 1334{ 1335 struct sa1111_dev *dev = SA1111_DEV(_dev); 1336 struct sa1111_driver *drv = SA1111_DRV(_drv); 1337 1338 return dev->devid & drv->devid; 1339} 1340 1341static int sa1111_bus_suspend(struct device *dev, pm_message_t state) 1342{ 1343 struct sa1111_dev *sadev = SA1111_DEV(dev); 1344 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1345 int ret = 0; 1346 1347 if (drv && drv->suspend) 1348 ret = drv->suspend(sadev, state); 1349 return ret; 1350} 1351 1352static int sa1111_bus_resume(struct device *dev) 1353{ 1354 struct sa1111_dev *sadev = SA1111_DEV(dev); 1355 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1356 int ret = 0; 1357 1358 if (drv && drv->resume) 1359 ret = drv->resume(sadev); 1360 return ret; 1361} 1362 1363static void sa1111_bus_shutdown(struct device *dev) 1364{ 1365 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1366 1367 if (drv && drv->shutdown) 1368 drv->shutdown(SA1111_DEV(dev)); 1369} 1370 1371static int sa1111_bus_probe(struct device *dev) 1372{ 1373 struct sa1111_dev *sadev = SA1111_DEV(dev); 1374 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1375 int ret = -ENODEV; 1376 1377 if (drv->probe) 1378 ret = drv->probe(sadev); 1379 return ret; 1380} 1381 1382static int sa1111_bus_remove(struct device *dev) 1383{ 1384 struct sa1111_dev *sadev = SA1111_DEV(dev); 1385 struct sa1111_driver *drv = SA1111_DRV(dev->driver); 1386 int ret = 0; 1387 1388 if (drv->remove) 1389 ret = drv->remove(sadev); 1390 return ret; 1391} 1392 1393struct bus_type sa1111_bus_type = { 1394 .name = "sa1111-rab", 1395 .match = sa1111_match, 1396 .probe = sa1111_bus_probe, 1397 .remove = sa1111_bus_remove, 1398 .suspend = sa1111_bus_suspend, 1399 .resume = sa1111_bus_resume, 1400 .shutdown = sa1111_bus_shutdown, 1401}; 1402EXPORT_SYMBOL(sa1111_bus_type); 1403 1404int sa1111_driver_register(struct sa1111_driver *driver) 1405{ 1406 driver->drv.bus = &sa1111_bus_type; 1407 return driver_register(&driver->drv); 1408} 1409EXPORT_SYMBOL(sa1111_driver_register); 1410 1411void sa1111_driver_unregister(struct sa1111_driver *driver) 1412{ 1413 driver_unregister(&driver->drv); 1414} 1415EXPORT_SYMBOL(sa1111_driver_unregister); 1416 1417static int __init sa1111_init(void) 1418{ 1419 int ret = bus_register(&sa1111_bus_type); 1420 if (ret == 0) 1421 platform_driver_register(&sa1111_device_driver); 1422 return ret; 1423} 1424 1425static void __exit sa1111_exit(void) 1426{ 1427 platform_driver_unregister(&sa1111_device_driver); 1428 bus_unregister(&sa1111_bus_type); 1429} 1430 1431subsys_initcall(sa1111_init); 1432module_exit(sa1111_exit); 1433 1434MODULE_DESCRIPTION("Intel Corporation SA1111 core driver"); 1435MODULE_LICENSE("GPL"); 1436