1749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall/* 2749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * Copyright (C) 2012 - Virtual Open Systems and Columbia University 3749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * Author: Christoffer Dall <c.dall@virtualopensystems.com> 4749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * 5749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * This program is free software; you can redistribute it and/or modify 6749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * it under the terms of the GNU General Public License, version 2, as 7749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * published by the Free Software Foundation. 8749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * 9749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * This program is distributed in the hope that it will be useful, 10749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * but WITHOUT ANY WARRANTY; without even the implied warranty of 11749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * GNU General Public License for more details. 13749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * 14749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * You should have received a copy of the GNU General Public License 15749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * along with this program; if not, write to the Free Software 16749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall */ 18749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall 19749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall#ifndef __ARM_KVM_ARM_H__ 20749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall#define __ARM_KVM_ARM_H__ 21749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall 22749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall#include <linux/types.h> 23749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall 24342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall/* Hyp Configuration Register (HCR) bits */ 25342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TGE (1 << 27) 26342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TVM (1 << 26) 27342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TTLB (1 << 25) 28342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TPU (1 << 24) 29342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TPC (1 << 23) 30342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TSW (1 << 22) 31342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TAC (1 << 21) 32342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TIDCP (1 << 20) 33342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TSC (1 << 19) 34342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TID3 (1 << 18) 35342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TID2 (1 << 17) 36342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TID1 (1 << 16) 37342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TID0 (1 << 15) 38342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TWE (1 << 14) 39342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_TWI (1 << 13) 40342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_DC (1 << 12) 41342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_BSU (3 << 10) 42342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_BSU_IS (1 << 10) 43342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_FB (1 << 9) 44342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_VA (1 << 8) 45342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_VI (1 << 7) 46342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_VF (1 << 6) 47342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_AMO (1 << 5) 48342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_IMO (1 << 4) 49342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_FMO (1 << 3) 50342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_PTW (1 << 2) 51342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_SWIO (1 << 1) 52342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_VM 1 53342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall 54342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall/* 55342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * The bits we set in HCR: 56342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * TAC: Trap ACTLR 57342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * TSC: Trap SMC 588034699a42d68043b495c7e0cfafccd920707ec8Marc Zyngier * TVM: Trap VM ops (until MMU and caches are on) 59342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * TSW: Trap cache operations by set/way 60342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * TWI: Trap WFI 6186ed81aa2e1ce05a4e7f0819f0dfc34e8d8fb910Christoffer Dall * TWE: Trap WFE 62342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * TIDCP: Trap L2CTLR/L2ECTLR 63342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * BSU_IS: Upgrade barriers to the inner shareable domain 64342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * FB: Force broadcast of all maintainance operations 65342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * AMO: Override CPSR.A and enable signaling with VA 66342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * IMO: Override CPSR.I and enable signaling with VI 67342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * FMO: Override CPSR.F and enable signaling with VF 68342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * SWIO: Turn set/way invalidates into set/way clean+invalidate 69342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall */ 70342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \ 71342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \ 728034699a42d68043b495c7e0cfafccd920707ec8Marc Zyngier HCR_TVM | HCR_TWE | HCR_SWIO | HCR_TIDCP) 73342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall 745b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall/* System Control Register (SCTLR) bits */ 755b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall#define SCTLR_TE (1 << 30) 765b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall#define SCTLR_EE (1 << 25) 775b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall#define SCTLR_V (1 << 13) 785b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall 79342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall/* Hyp System Control Register (HSCTLR) bits */ 80342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HSCTLR_TE (1 << 30) 81342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HSCTLR_EE (1 << 25) 82342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HSCTLR_FI (1 << 21) 83342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HSCTLR_WXN (1 << 19) 84342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HSCTLR_I (1 << 12) 85342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HSCTLR_C (1 << 2) 86342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HSCTLR_A (1 << 1) 87342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HSCTLR_M 1 88342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HSCTLR_MASK (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \ 89342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE) 90342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall 91342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall/* TTBCR and HTCR Registers bits */ 92342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_EAE (1 << 31) 93342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_IMP (1 << 30) 94342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_SH1 (3 << 28) 95342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_ORGN1 (3 << 26) 96342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_IRGN1 (3 << 24) 97342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_EPD1 (1 << 23) 98342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_A1 (1 << 22) 995e497046f005528464f9600a4ee04f49df713596Jonathan Austin#define TTBCR_T1SZ (7 << 16) 100342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_SH0 (3 << 12) 101342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_ORGN0 (3 << 10) 102342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_IRGN0 (3 << 8) 103342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define TTBCR_EPD0 (1 << 7) 1045e497046f005528464f9600a4ee04f49df713596Jonathan Austin#define TTBCR_T0SZ (7 << 0) 105342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0) 106342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall 107f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall/* Hyp System Trap Register */ 108f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSTR_T(x) (1 << x) 109f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSTR_TTEE (1 << 16) 110f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSTR_TJDBX (1 << 17) 111f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall 112f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall/* Hyp Coprocessor Trap Register */ 113f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HCPTR_TCP(x) (1 << x) 114f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HCPTR_TCP_MASK (0x3fff) 115f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HCPTR_TASE (1 << 15) 116f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HCPTR_TTA (1 << 20) 117f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HCPTR_TCPAC (1 << 31) 118f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall 119342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall/* Hyp Debug Configuration Register bits */ 120342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HDCR_TDRA (1 << 11) 121342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HDCR_TDOSA (1 << 10) 122342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HDCR_TDA (1 << 9) 123342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HDCR_TDE (1 << 8) 124342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HDCR_HPME (1 << 7) 125342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HDCR_TPM (1 << 6) 126342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HDCR_TPMCR (1 << 5) 127342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define HDCR_HPMN_MASK (0x1F) 128342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall 129342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall/* 130342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * The architecture supports 40-bit IPA as input to the 2nd stage translations 131342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address 132342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall * space. 133342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall */ 134342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define KVM_PHYS_SHIFT (40) 135342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define KVM_PHYS_SIZE (1ULL << KVM_PHYS_SHIFT) 136342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1ULL) 137342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30)) 138342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t)) 139342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall 140342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall/* Virtualization Translation Control Register (VTCR) bits */ 141342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_SH0 (3 << 12) 142342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_ORGN0 (3 << 10) 143342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_IRGN0 (3 << 8) 144342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_SL0 (3 << 6) 145342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_S (1 << 4) 146342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_T0SZ (0xf) 147342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_MASK (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \ 148342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall VTCR_S | VTCR_T0SZ) 149342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_HTCR_SH (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0) 150342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */ 151342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */ 152342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define KVM_VTCR_SL0 VTCR_SL_L1 153342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall/* stage-2 input address range defined as 2^(32-T0SZ) */ 154342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define KVM_T0SZ (32 - KVM_PHYS_SHIFT) 155342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define KVM_VTCR_T0SZ (KVM_T0SZ & VTCR_T0SZ) 156342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define KVM_VTCR_S ((KVM_VTCR_T0SZ << 1) & VTCR_S) 157342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall 158342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall/* Virtualization Translation Table Base Register (VTTBR) bits */ 159342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#if KVM_VTCR_SL0 == VTCR_SL_L2 /* see ARM DDI 0406C: B4-1720 */ 160342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTTBR_X (14 - KVM_T0SZ) 161342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#else 162342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#define VTTBR_X (5 - KVM_T0SZ) 163342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall#endif 164f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define VTTBR_BADDR_SHIFT (VTTBR_X - 1) 165f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define VTTBR_BADDR_MASK (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) 166f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define VTTBR_VMID_SHIFT (48LLU) 167f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define VTTBR_VMID_MASK (0xffLLU << VTTBR_VMID_SHIFT) 168f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall 169f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall/* Hyp Syndrome Register (HSR) bits */ 170f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_SHIFT (26) 171f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC (0x3fU << HSR_EC_SHIFT) 172f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_IL (1U << 25) 173f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_ISS (HSR_IL - 1) 174f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_ISV_SHIFT (24) 175f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_ISV (1U << HSR_ISV_SHIFT) 17645e96ea6b369539a37040a8df9c59a39f073d9d6Christoffer Dall#define HSR_SRT_SHIFT (16) 17745e96ea6b369539a37040a8df9c59a39f073d9d6Christoffer Dall#define HSR_SRT_MASK (0xf << HSR_SRT_SHIFT) 178f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_FSC (0x3f) 179f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_FSC_TYPE (0x3c) 18045e96ea6b369539a37040a8df9c59a39f073d9d6Christoffer Dall#define HSR_SSE (1 << 21) 181f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_WNR (1 << 6) 1825b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall#define HSR_CV_SHIFT (24) 1835b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall#define HSR_CV (1U << HSR_CV_SHIFT) 1845b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall#define HSR_COND_SHIFT (20) 1855b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall#define HSR_COND (0xfU << HSR_COND_SHIFT) 186f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall 187f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define FSC_FAULT (0x04) 188f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define FSC_PERM (0x0c) 189f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall 190f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 191f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HPFAR_MASK (~0xf) 192342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall 193f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_UNKNOWN (0x00) 194f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_WFI (0x01) 195f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_CP15_32 (0x03) 196f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_CP15_64 (0x04) 197f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_CP14_MR (0x05) 198f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_CP14_LS (0x06) 199f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_CP_0_13 (0x07) 200f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_CP10_ID (0x08) 201f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_JAZELLE (0x09) 202f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_BXJ (0x0A) 203f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_CP14_64 (0x0C) 204f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_SVC_HYP (0x11) 205f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_HVC (0x12) 206f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_SMC (0x13) 207f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_IABT (0x20) 208f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_IABT_HYP (0x21) 209f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_DABT (0x24) 210f7ed45be3ba524e06a6d933f0517dc7ad2d06703Christoffer Dall#define HSR_EC_DABT_HYP (0x25) 211342cd0ab0e6ca3fe7c88a78890352748b8e894a9Christoffer Dall 21258d5ec8f8ee318b26b29207874fbaee626973952Marc Zyngier#define HSR_WFI_IS_WFE (1U << 0) 21358d5ec8f8ee318b26b29207874fbaee626973952Marc Zyngier 2145b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall#define HSR_HVC_IMM_MASK ((1UL << 16) - 1) 2155b3e5e5bf230f56309706dfc05fc0cb173cc83aaChristoffer Dall 216b37670b0f37d8015d0d428e6a63bd07397430a2fMarc Zyngier#define HSR_DABT_S1PTW (1U << 7) 21778abfcde49e0e454cabf8e56cd4c1591752e2706Marc Zyngier#define HSR_DABT_CM (1U << 8) 21878abfcde49e0e454cabf8e56cd4c1591752e2706Marc Zyngier#define HSR_DABT_EA (1U << 9) 21978abfcde49e0e454cabf8e56cd4c1591752e2706Marc Zyngier 220749cf76c5a363e1383108a914ea09530bfa0bd43Christoffer Dall#endif /* __ARM_KVM_ARM_H__ */ 221