hw_breakpoint.c revision 7e20269647169e7ea08a62bdc4979a3ba32e615c
1f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 2f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * This program is free software; you can redistribute it and/or modify 3f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * it under the terms of the GNU General Public License version 2 as 4f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * published by the Free Software Foundation. 5f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * 6f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * This program is distributed in the hope that it will be useful, 7f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * but WITHOUT ANY WARRANTY; without even the implied warranty of 8f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * GNU General Public License for more details. 10f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * 11f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * You should have received a copy of the GNU General Public License 12f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * along with this program; if not, write to the Free Software 13f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 14f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * 15f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Copyright (C) 2009, 2010 ARM Limited 16f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * 17f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Author: Will Deacon <will.deacon@arm.com> 18f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 19f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 20f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 21f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, 22f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * using the CPU's debug registers. 23f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 24f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#define pr_fmt(fmt) "hw-breakpoint: " fmt 25f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 26f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <linux/errno.h> 277e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon#include <linux/hardirq.h> 28f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <linux/perf_event.h> 29f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <linux/hw_breakpoint.h> 30f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <linux/smp.h> 31f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 32f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <asm/cacheflush.h> 33f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <asm/cputype.h> 34f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <asm/current.h> 35f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <asm/hw_breakpoint.h> 36f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <asm/kdebug.h> 37f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <asm/system.h> 38f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#include <asm/traps.h> 39f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 40f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* Breakpoint currently in use for each BRP. */ 41f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); 42f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 43f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* Watchpoint currently in use for each WRP. */ 44f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); 45f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 46f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* Number of BRP/WRP registers on this CPU. */ 47f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int core_num_brps; 48f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int core_num_wrps; 49f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 50f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* Debug architecture version. */ 51f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic u8 debug_arch; 52f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 53f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* Maximum supported watchpoint length. */ 54f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic u8 max_watchpoint_len; 55f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 56f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* Determine number of BRP registers available. */ 57f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int get_num_brps(void) 58f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 59f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u32 didr; 60f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_READ(c0, 0, didr); 61f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return ((didr >> 24) & 0xf) + 1; 62f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 63f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 64f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* Determine number of WRP registers available. */ 65f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int get_num_wrps(void) 66f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 67f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* 68f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * FIXME: When a watchpoint fires, the only way to work out which 69f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * watchpoint it was is by disassembling the faulting instruction 70f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * and working out the address of the memory access. 71f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * 72f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Furthermore, we can only do this if the watchpoint was precise 73f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * since imprecise watchpoints prevent us from calculating register 74f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * based addresses. 75f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * 76f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * For the time being, we only report 1 watchpoint register so we 77f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * always know which watchpoint fired. In the future we can either 78f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * add a disassembler and address generation emulator, or we can 79f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * insert a check to see if the DFAR is set on watchpoint exception 80f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * entry [the ARM ARM states that the DFAR is UNKNOWN, but 81f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * experience shows that it is set on some implementations]. 82f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 83f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 84f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#if 0 85f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u32 didr, wrps; 86f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_READ(c0, 0, didr); 87f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return ((didr >> 28) & 0xf) + 1; 88f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#endif 89f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 90f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return 1; 91f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 92f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 93f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconint hw_breakpoint_slots(int type) 94f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 95f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* 96f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * We can be called early, so don't rely on 97f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * our static variables being initialised. 98f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 99f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (type) { 100f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case TYPE_INST: 101f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return get_num_brps(); 102f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case TYPE_DATA: 103f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return get_num_wrps(); 104f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon default: 105f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_warning("unknown slot type: %d\n", type); 106f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return 0; 107f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 108f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 109f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 110f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* Determine debug architecture. */ 111f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic u8 get_debug_arch(void) 112f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 113f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u32 didr; 114f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 115f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Do we implement the extended CPUID interface? */ 116f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { 117f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_warning("CPUID feature registers not supported. " 118f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon "Assuming v6 debug is present.\n"); 119f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return ARM_DEBUG_ARCH_V6; 120f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 121f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 122f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_READ(c0, 0, didr); 123f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return (didr >> 16) & 0xf; 124f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 125f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 126f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* Does this core support mismatch breakpoints? */ 127f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int core_has_mismatch_bps(void) 128f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 129f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return debug_arch >= ARM_DEBUG_ARCH_V7_ECP14 && core_num_brps > 1; 130f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 131f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 132f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconu8 arch_get_debug_arch(void) 133f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 134f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return debug_arch; 135f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 136f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 137f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#define READ_WB_REG_CASE(OP2, M, VAL) \ 138f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ((OP2 << 4) + M): \ 139f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_READ(c ## M, OP2, VAL); \ 140f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break 141f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 142f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#define WRITE_WB_REG_CASE(OP2, M, VAL) \ 143f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ((OP2 << 4) + M): \ 144f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_WRITE(c ## M, OP2, VAL);\ 145f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break 146f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 147f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#define GEN_READ_WB_REG_CASES(OP2, VAL) \ 148f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 0, VAL); \ 149f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 1, VAL); \ 150f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 2, VAL); \ 151f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 3, VAL); \ 152f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 4, VAL); \ 153f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 5, VAL); \ 154f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 6, VAL); \ 155f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 7, VAL); \ 156f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 8, VAL); \ 157f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 9, VAL); \ 158f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 10, VAL); \ 159f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 11, VAL); \ 160f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 12, VAL); \ 161f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 13, VAL); \ 162f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 14, VAL); \ 163f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon READ_WB_REG_CASE(OP2, 15, VAL) 164f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 165f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ 166f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 0, VAL); \ 167f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 1, VAL); \ 168f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 2, VAL); \ 169f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 3, VAL); \ 170f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 4, VAL); \ 171f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 5, VAL); \ 172f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 6, VAL); \ 173f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 7, VAL); \ 174f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 8, VAL); \ 175f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 9, VAL); \ 176f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 10, VAL); \ 177f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 11, VAL); \ 178f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 12, VAL); \ 179f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 13, VAL); \ 180f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 14, VAL); \ 181f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon WRITE_WB_REG_CASE(OP2, 15, VAL) 182f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 183f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic u32 read_wb_reg(int n) 184f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 185f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u32 val = 0; 186f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 187f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (n) { 188f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); 189f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); 190f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); 191f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); 192f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon default: 193f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_warning("attempt to read from unknown breakpoint " 194f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon "register %d\n", n); 195f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 196f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 197f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return val; 198f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 199f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 200f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic void write_wb_reg(int n, u32 val) 201f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 202f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (n) { 203f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val); 204f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val); 205f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); 206f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); 207f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon default: 208f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_warning("attempt to write to unknown breakpoint " 209f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon "register %d\n", n); 210f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 211f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon isb(); 212f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 213f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 214f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 215f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * In order to access the breakpoint/watchpoint control registers, 216f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * we must be running in debug monitor mode. Unfortunately, we can 217f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * be put into halting debug mode at any time by an external debugger 218f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * but there is nothing we can do to prevent that. 219f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 220f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int enable_monitor_mode(void) 221f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 222f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u32 dscr; 223f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int ret = 0; 224f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 225f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_READ(c1, 0, dscr); 226f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 227f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Ensure that halting mode is disabled. */ 228f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled." 229f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon "Unable to access hardware resources.")) { 230f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ret = -EPERM; 231f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto out; 232f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 233f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 234f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Write to the corresponding DSCR. */ 235f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (debug_arch) { 236f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_DEBUG_ARCH_V6: 237f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_DEBUG_ARCH_V6_1: 238f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); 239f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 240f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_DEBUG_ARCH_V7_ECP14: 241f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); 242f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 243f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon default: 244f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ret = -ENODEV; 245f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto out; 246f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 247f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 248f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Check that the write made it through. */ 249f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_READ(c1, 0, dscr); 250f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN), 251f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon "failed to enable monitor mode.")) { 252f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ret = -EPERM; 253f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 254f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 255f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconout: 256f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return ret; 257f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 258f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 259f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 260f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Check if 8-bit byte-address select is available. 261f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * This clobbers WRP 0. 262f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 263f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic u8 get_max_wp_len(void) 264f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 265f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u32 ctrl_reg; 266f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint_ctrl ctrl; 267f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u8 size = 4; 268f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 269f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) 270f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto out; 271f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 272f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (enable_monitor_mode()) 273f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto out; 274f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 275f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon memset(&ctrl, 0, sizeof(ctrl)); 276f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ctrl.len = ARM_BREAKPOINT_LEN_8; 277f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ctrl_reg = encode_ctrl_reg(ctrl); 278f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 279f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(ARM_BASE_WVR, 0); 280f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(ARM_BASE_WCR, ctrl_reg); 281f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) 282f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon size = 8; 283f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 284f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconout: 285f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return size; 286f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 287f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 288f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconu8 arch_get_max_wp_len(void) 289f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 290f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return max_watchpoint_len; 291f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 292f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 293f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 294f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Handler for reactivating a suspended watchpoint when the single 295f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * step `mismatch' breakpoint is triggered. 296f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 297f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic void wp_single_step_handler(struct perf_event *bp, int unused, 298f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct perf_sample_data *data, 299f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct pt_regs *regs) 300f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 301f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon perf_event_enable(counter_arch_bp(bp)->suspended_wp); 302f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon unregister_hw_breakpoint(bp); 303f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 304f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 305f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int bp_is_single_step(struct perf_event *bp) 306f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 307f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return bp->overflow_handler == wp_single_step_handler; 308f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 309f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 310f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 311f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Install a perf counter breakpoint. 312f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 313f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconint arch_install_hw_breakpoint(struct perf_event *bp) 314f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 315f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 316f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct perf_event **slot, **slots; 317f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int i, max_slots, ctrl_base, val_base, ret = 0; 318f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 319f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Ensure that we are in monitor mode and halting mode is disabled. */ 320f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ret = enable_monitor_mode(); 321f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (ret) 322f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto out; 323f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 324f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 325f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Breakpoint */ 326f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ctrl_base = ARM_BASE_BCR; 327f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon val_base = ARM_BASE_BVR; 328f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon slots = __get_cpu_var(bp_on_reg); 329f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon max_slots = core_num_brps - 1; 330f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 331f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (bp_is_single_step(bp)) { 332f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.mismatch = 1; 333f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon i = max_slots; 334f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon slots[i] = bp; 335f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto setup; 336f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 337f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } else { 338f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Watchpoint */ 339f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ctrl_base = ARM_BASE_WCR; 340f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon val_base = ARM_BASE_WVR; 341f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon slots = __get_cpu_var(wp_on_reg); 342f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon max_slots = core_num_wrps; 343f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 344f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 345f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon for (i = 0; i < max_slots; ++i) { 346f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon slot = &slots[i]; 347f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 348f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (!*slot) { 349f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *slot = bp; 350f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 351f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 352f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 353f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 354f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) { 355f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ret = -EBUSY; 356f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto out; 357f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 358f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 359f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconsetup: 360f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Setup the address register. */ 361f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(val_base + i, info->address); 362f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 363f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Setup the control register. */ 364f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1); 365f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 366f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconout: 367f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return ret; 368f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 369f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 370f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconvoid arch_uninstall_hw_breakpoint(struct perf_event *bp) 371f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 372f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 373f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct perf_event **slot, **slots; 374f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int i, max_slots, base; 375f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 376f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 377f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Breakpoint */ 378f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon base = ARM_BASE_BCR; 379f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon slots = __get_cpu_var(bp_on_reg); 380f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon max_slots = core_num_brps - 1; 381f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 382f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (bp_is_single_step(bp)) { 383f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon i = max_slots; 384f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon slots[i] = NULL; 385f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto reset; 386f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 387f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } else { 388f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Watchpoint */ 389f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon base = ARM_BASE_WCR; 390f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon slots = __get_cpu_var(wp_on_reg); 391f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon max_slots = core_num_wrps; 392f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 393f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 394f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Remove the breakpoint. */ 395f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon for (i = 0; i < max_slots; ++i) { 396f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon slot = &slots[i]; 397f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 398f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (*slot == bp) { 399f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *slot = NULL; 400f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 401f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 402f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 403f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 404f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) 405f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return; 406f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 407f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconreset: 408f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Reset the control register. */ 409f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(base + i, 0); 410f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 411f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 412f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int get_hbp_len(u8 hbp_len) 413f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 414f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon unsigned int len_in_bytes = 0; 415f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 416f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (hbp_len) { 417f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LEN_1: 418f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon len_in_bytes = 1; 419f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 420f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LEN_2: 421f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon len_in_bytes = 2; 422f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 423f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LEN_4: 424f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon len_in_bytes = 4; 425f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 426f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LEN_8: 427f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon len_in_bytes = 8; 428f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 429f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 430f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 431f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return len_in_bytes; 432f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 433f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 434f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 435f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Check whether bp virtual address is in kernel space. 436f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 437f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconint arch_check_bp_in_kernelspace(struct perf_event *bp) 438f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 439f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon unsigned int len; 440f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon unsigned long va; 441f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 442f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 443f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon va = info->address; 444f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon len = get_hbp_len(info->ctrl.len); 445f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 446f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); 447f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 448f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 449f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 450f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. 451f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Hopefully this will disappear when ptrace can bypass the conversion 452f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * to generic breakpoint descriptions. 453f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 454f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconint arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, 455f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int *gen_len, int *gen_type) 456f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 457f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Type */ 458f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (ctrl.type) { 459f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_EXECUTE: 460f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *gen_type = HW_BREAKPOINT_X; 461f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 462f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LOAD: 463f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *gen_type = HW_BREAKPOINT_R; 464f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 465f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_STORE: 466f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *gen_type = HW_BREAKPOINT_W; 467f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 468f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: 469f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *gen_type = HW_BREAKPOINT_RW; 470f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 471f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon default: 472f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return -EINVAL; 473f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 474f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 475f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Len */ 476f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (ctrl.len) { 477f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LEN_1: 478f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *gen_len = HW_BREAKPOINT_LEN_1; 479f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 480f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LEN_2: 481f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *gen_len = HW_BREAKPOINT_LEN_2; 482f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 483f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LEN_4: 484f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *gen_len = HW_BREAKPOINT_LEN_4; 485f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 486f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_BREAKPOINT_LEN_8: 487f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon *gen_len = HW_BREAKPOINT_LEN_8; 488f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 489f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon default: 490f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return -EINVAL; 491f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 492f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 493f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return 0; 494f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 495f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 496f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 497f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Construct an arch_hw_breakpoint from a perf_event. 498f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 499f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int arch_build_bp_info(struct perf_event *bp) 500f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 501f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 502f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 503f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Type */ 504f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (bp->attr.bp_type) { 505f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case HW_BREAKPOINT_X: 506f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.type = ARM_BREAKPOINT_EXECUTE; 507f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 508f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case HW_BREAKPOINT_R: 509f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.type = ARM_BREAKPOINT_LOAD; 510f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 511f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case HW_BREAKPOINT_W: 512f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.type = ARM_BREAKPOINT_STORE; 513f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 514f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case HW_BREAKPOINT_RW: 515f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; 516f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 517f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon default: 518f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return -EINVAL; 519f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 520f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 521f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Len */ 522f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (bp->attr.bp_len) { 523f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case HW_BREAKPOINT_LEN_1: 524f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.len = ARM_BREAKPOINT_LEN_1; 525f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 526f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case HW_BREAKPOINT_LEN_2: 527f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.len = ARM_BREAKPOINT_LEN_2; 528f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 529f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case HW_BREAKPOINT_LEN_4: 530f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.len = ARM_BREAKPOINT_LEN_4; 531f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 532f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case HW_BREAKPOINT_LEN_8: 533f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.len = ARM_BREAKPOINT_LEN_8; 534f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE) 535f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon && max_watchpoint_len >= 8) 536f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 537f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon default: 538f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return -EINVAL; 539f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 540f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 5416ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon /* 5426ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes. 5436ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported 5446ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon * by the hardware and must be aligned to the appropriate number of 5456ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon * bytes. 5466ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon */ 5476ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE && 5486ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon info->ctrl.len != ARM_BREAKPOINT_LEN_2 && 5496ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon info->ctrl.len != ARM_BREAKPOINT_LEN_4) 5506ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon return -EINVAL; 5516ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon 552f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Address */ 553f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->address = bp->attr.bp_addr; 554f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 555f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Privilege */ 556f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.privilege = ARM_BREAKPOINT_USER; 557f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp)) 558f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; 559f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 560f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Enabled? */ 561f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.enabled = !bp->attr.disabled; 562f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 563f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Mismatch */ 564f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.mismatch = 0; 565f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 566f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return 0; 567f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 568f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 569f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 570f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Validate the arch-specific HW Breakpoint register settings. 571f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 572f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconint arch_validate_hwbkpt_settings(struct perf_event *bp) 573f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 574f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 575f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int ret = 0; 5766ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon u32 offset, alignment_mask = 0x3; 577f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 578f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Build the arch_hw_breakpoint. */ 579f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ret = arch_build_bp_info(bp); 580f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (ret) 581f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto out; 582f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 583f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Check address alignment. */ 584f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) 585f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon alignment_mask = 0x7; 5866ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon offset = info->address & alignment_mask; 5876ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon switch (offset) { 5886ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon case 0: 5896ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon /* Aligned */ 5906ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon break; 5916ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon case 1: 5926ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon /* Allow single byte watchpoint. */ 5936ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) 5946ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon break; 5956ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon case 2: 5966ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon /* Allow halfword watchpoints and breakpoints. */ 5976ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) 5986ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon break; 5996ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon default: 6006ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon ret = -EINVAL; 6016ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon goto out; 602f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 603f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 6046ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon info->address &= ~alignment_mask; 6056ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon info->ctrl.len <<= offset; 6066ee33c2712fcdff2568d9bbadb25c8e5a7c36212Will Deacon 607f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* 608f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Currently we rely on an overflow handler to take 609f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * care of single-stepping the breakpoint when it fires. 610f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * In the case of userspace breakpoints on a core with V7 debug, 611f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * we can use the mismatch feature as a poor-man's hardware single-step. 612f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 613f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (WARN_ONCE(!bp->overflow_handler && 614f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_bps()), 615f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon "overflow handler required but none found")) { 616f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ret = -EINVAL; 617f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 618f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconout: 619f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return ret; 620f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 621f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 622f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic void update_mismatch_flag(int idx, int flag) 623f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 624f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]); 625f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint *info; 626f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 627f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (bp == NULL) 628f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return; 629f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 630f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info = counter_arch_bp(bp); 631f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 632f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Update the mismatch field to enter/exit `single-step' mode */ 633f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (!bp->overflow_handler && info->ctrl.mismatch != flag) { 634f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->ctrl.mismatch = flag; 635f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1); 636f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 637f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 638f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 639f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) 640f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 641f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int i; 642f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg); 643f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint *info; 644f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct perf_event_attr attr; 645f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 646f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Without a disassembler, we can only handle 1 watchpoint. */ 647f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon BUG_ON(core_num_wrps > 1); 648f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 649f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon hw_breakpoint_init(&attr); 650f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon attr.bp_addr = regs->ARM_pc & ~0x3; 651f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon attr.bp_len = HW_BREAKPOINT_LEN_4; 652f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon attr.bp_type = HW_BREAKPOINT_X; 653f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 654f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon for (i = 0; i < core_num_wrps; ++i) { 655f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon rcu_read_lock(); 656f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 657f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (slots[i] == NULL) { 658f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon rcu_read_unlock(); 659f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon continue; 660f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 661f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 662f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* 663f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * The DFAR is an unknown value. Since we only allow a 664f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * single watchpoint, we can set the trigger to the lowest 665f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * possible faulting address. 666f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 667f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info = counter_arch_bp(slots[i]); 668f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->trigger = slots[i]->attr.bp_addr; 669f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); 670f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon perf_bp_event(slots[i], regs); 671f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 672f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* 673f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * If no overflow handler is present, insert a temporary 674f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * mismatch breakpoint so we can single-step over the 675f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * watchpoint trigger. 676f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 677f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (!slots[i]->overflow_handler) { 678f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon bp = register_user_hw_breakpoint(&attr, 679f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon wp_single_step_handler, 680f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon current); 681f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon counter_arch_bp(bp)->suspended_wp = slots[i]; 682f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon perf_event_disable(slots[i]); 683f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 684f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 685f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon rcu_read_unlock(); 686f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 687f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 688f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 689f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) 690f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 691f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int i; 692f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int mismatch; 693f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u32 ctrl_reg, val, addr; 694f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg); 695f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint *info; 696f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct arch_hw_breakpoint_ctrl ctrl; 697f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 698f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* The exception entry code places the amended lr in the PC. */ 699f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon addr = regs->ARM_pc; 700f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 701f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon for (i = 0; i < core_num_brps; ++i) { 702f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon rcu_read_lock(); 703f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 704f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon bp = slots[i]; 705f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 706f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (bp == NULL) { 707f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon rcu_read_unlock(); 708f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon continue; 709f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 710f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 711f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon mismatch = 0; 712f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 713f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Check if the breakpoint value matches. */ 714f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon val = read_wb_reg(ARM_BASE_BVR + i); 715f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (val != (addr & ~0x3)) 716f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto unlock; 717f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 718f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Possible match, check the byte address select to confirm. */ 719f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); 720f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon decode_ctrl_reg(ctrl_reg, &ctrl); 721f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if ((1 << (addr & 0x3)) & ctrl.len) { 722f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon mismatch = 1; 723f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info = counter_arch_bp(bp); 724f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon info->trigger = addr; 725f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 726f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 727f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconunlock: 728f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) { 729f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_debug("breakpoint fired: address = 0x%x\n", addr); 730f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon perf_bp_event(bp, regs); 731f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 732f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 733f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon update_mismatch_flag(i, mismatch); 734f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon rcu_read_unlock(); 735f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 736f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 737f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 738f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 739f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Called from either the Data Abort Handler [watchpoint] or the 7407e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon * Prefetch Abort Handler [breakpoint] with preemption disabled. 741f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 742f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, 743f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon struct pt_regs *regs) 744f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 7457e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon int ret = 0; 746f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u32 dscr; 747f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 7487e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon /* We must be called with preemption disabled. */ 7497e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon WARN_ON(preemptible()); 7507e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon 751f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* We only handle watchpoints and hardware breakpoints. */ 752f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_READ(c1, 0, dscr); 753f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 754f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Perform perf callbacks. */ 755f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon switch (ARM_DSCR_MOE(dscr)) { 756f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_ENTRY_BREAKPOINT: 757f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon breakpoint_handler(addr, regs); 758f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 759f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_ENTRY_ASYNC_WATCHPOINT: 760235584b6f3b71bc1381be13a963a16f7107650cfJoe Perches WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); 761f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon case ARM_ENTRY_SYNC_WATCHPOINT: 762f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon watchpoint_handler(addr, regs); 763f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon break; 764f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon default: 7657e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon ret = 1; /* Unhandled fault. */ 766f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 767f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 7687e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon /* 7697e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon * Re-enable preemption after it was disabled in the 7707e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon * low-level exception handling code. 7717e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon */ 7727e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon preempt_enable(); 7737e20269647169e7ea08a62bdc4979a3ba32e615cWill Deacon 774f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return ret; 775f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 776f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 777f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 778f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * One-time initialisation. 779f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 7807d99331e4793b52d488e911876ef11d843c6c8c9Will Deaconstatic void reset_ctrl_regs(void *unused) 781f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 782f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int i; 783f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 784ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon /* 785ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon * v7 debug contains save and restore registers so that debug state 786ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon * can be maintained across low-power modes without leaving 787ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon * the debug logic powered up. It is IMPLEMENTATION DEFINED whether 788ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon * we can write to the debug registers out of reset, so we must 789ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon * unlock the OS Lock Access Register to avoid taking undefined 790ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon * instruction exceptions later on. 791ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon */ 792ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) { 793ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon /* 794ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon * Unconditionally clear the lock by writing a value 795ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon * other than 0xC5ACCE55 to the access register. 796ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon */ 797ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); 798ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon isb(); 799ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon } 800ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon 801f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (enable_monitor_mode()) 802f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return; 803f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 804f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon for (i = 0; i < core_num_brps; ++i) { 805f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(ARM_BASE_BCR + i, 0UL); 806f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(ARM_BASE_BVR + i, 0UL); 807f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 808f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 809f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon for (i = 0; i < core_num_wrps; ++i) { 810f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(ARM_BASE_WCR + i, 0UL); 811f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon write_wb_reg(ARM_BASE_WVR + i, 0UL); 812f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 813f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 814f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 8157d99331e4793b52d488e911876ef11d843c6c8c9Will Deaconstatic int __cpuinit dbg_reset_notify(struct notifier_block *self, 8167d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon unsigned long action, void *cpu) 8177d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon{ 8187d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon if (action == CPU_ONLINE) 8197d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); 8207d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon return NOTIFY_OK; 8217d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon} 8227d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon 8237d99331e4793b52d488e911876ef11d843c6c8c9Will Deaconstatic struct notifier_block __cpuinitdata dbg_reset_nb = { 8247d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon .notifier_call = dbg_reset_notify, 8257d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon}; 8267d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon 827f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconstatic int __init arch_hw_breakpoint_init(void) 828f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 829f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon int ret = 0; 830f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon u32 dscr; 831f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 832f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon debug_arch = get_debug_arch(); 833f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 834f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) { 835f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_info("debug architecture 0x%x unsupported.\n", debug_arch); 836f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ret = -ENODEV; 837f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon goto out; 838f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 839f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 840f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Determine how many BRPs/WRPs are available. */ 841f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon core_num_brps = get_num_brps(); 842f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon core_num_wrps = get_num_wrps(); 843f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 844f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_info("found %d breakpoint and %d watchpoint registers.\n", 845f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon core_num_brps, core_num_wrps); 846f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 847f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (core_has_mismatch_bps()) 848f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_info("1 breakpoint reserved for watchpoint single-step.\n"); 849f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 850f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon ARM_DBG_READ(c1, 0, dscr); 851f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon if (dscr & ARM_DSCR_HDBGEN) { 852f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon pr_warning("halting debug mode enabled. Assuming maximum " 853f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon "watchpoint size of 4 bytes."); 854f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } else { 855f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* 856f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Reset the breakpoint resources. We assume that a halting 857f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * debugger will leave the world in a nice state for us. 858f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 859f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon smp_call_function(reset_ctrl_regs, NULL, 1); 860f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon reset_ctrl_regs(NULL); 861ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon 862ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon /* Work out the maximum supported watchpoint length. */ 863ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon max_watchpoint_len = get_max_wp_len(); 864ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon pr_info("maximum watchpoint size is %u bytes.\n", 865ac88e07122fc0eb5cbad403be97ef02c317a06b7Will Deacon max_watchpoint_len); 866f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon } 867f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 868f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon /* Register debug fault handler. */ 869f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, 870f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon "watchpoint debug exception"); 871f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, 872f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon "breakpoint debug exception"); 873f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 8747d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon /* Register hotplug notifier. */ 8757d99331e4793b52d488e911876ef11d843c6c8c9Will Deacon register_cpu_notifier(&dbg_reset_nb); 876f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconout: 877f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return ret; 878f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 879f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconarch_initcall(arch_hw_breakpoint_init); 880f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 881f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconvoid hw_breakpoint_pmu_read(struct perf_event *bp) 882f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 883f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 884f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon 885f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon/* 886f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon * Dummy function to register with die_notifier. 887f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon */ 888f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deaconint hw_breakpoint_exceptions_notify(struct notifier_block *unused, 889f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon unsigned long val, void *data) 890f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon{ 891f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon return NOTIFY_DONE; 892f81ef4a920c8e1af75adf9f15042c2daa49d3cb3Will Deacon} 893