hw_breakpoint.c revision c512de955f0982aafa49d3f00d5643052a6790e5
1/* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License version 2 as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 14 * 15 * Copyright (C) 2009, 2010 ARM Limited 16 * 17 * Author: Will Deacon <will.deacon@arm.com> 18 */ 19 20/* 21 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, 22 * using the CPU's debug registers. 23 */ 24#define pr_fmt(fmt) "hw-breakpoint: " fmt 25 26#include <linux/errno.h> 27#include <linux/hardirq.h> 28#include <linux/perf_event.h> 29#include <linux/hw_breakpoint.h> 30#include <linux/smp.h> 31 32#include <asm/cacheflush.h> 33#include <asm/cputype.h> 34#include <asm/current.h> 35#include <asm/hw_breakpoint.h> 36#include <asm/kdebug.h> 37#include <asm/system.h> 38#include <asm/traps.h> 39 40/* Breakpoint currently in use for each BRP. */ 41static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); 42 43/* Watchpoint currently in use for each WRP. */ 44static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); 45 46/* Number of BRP/WRP registers on this CPU. */ 47static int core_num_brps; 48static int core_num_wrps; 49 50/* Debug architecture version. */ 51static u8 debug_arch; 52 53/* Maximum supported watchpoint length. */ 54static u8 max_watchpoint_len; 55 56#define READ_WB_REG_CASE(OP2, M, VAL) \ 57 case ((OP2 << 4) + M): \ 58 ARM_DBG_READ(c ## M, OP2, VAL); \ 59 break 60 61#define WRITE_WB_REG_CASE(OP2, M, VAL) \ 62 case ((OP2 << 4) + M): \ 63 ARM_DBG_WRITE(c ## M, OP2, VAL);\ 64 break 65 66#define GEN_READ_WB_REG_CASES(OP2, VAL) \ 67 READ_WB_REG_CASE(OP2, 0, VAL); \ 68 READ_WB_REG_CASE(OP2, 1, VAL); \ 69 READ_WB_REG_CASE(OP2, 2, VAL); \ 70 READ_WB_REG_CASE(OP2, 3, VAL); \ 71 READ_WB_REG_CASE(OP2, 4, VAL); \ 72 READ_WB_REG_CASE(OP2, 5, VAL); \ 73 READ_WB_REG_CASE(OP2, 6, VAL); \ 74 READ_WB_REG_CASE(OP2, 7, VAL); \ 75 READ_WB_REG_CASE(OP2, 8, VAL); \ 76 READ_WB_REG_CASE(OP2, 9, VAL); \ 77 READ_WB_REG_CASE(OP2, 10, VAL); \ 78 READ_WB_REG_CASE(OP2, 11, VAL); \ 79 READ_WB_REG_CASE(OP2, 12, VAL); \ 80 READ_WB_REG_CASE(OP2, 13, VAL); \ 81 READ_WB_REG_CASE(OP2, 14, VAL); \ 82 READ_WB_REG_CASE(OP2, 15, VAL) 83 84#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ 85 WRITE_WB_REG_CASE(OP2, 0, VAL); \ 86 WRITE_WB_REG_CASE(OP2, 1, VAL); \ 87 WRITE_WB_REG_CASE(OP2, 2, VAL); \ 88 WRITE_WB_REG_CASE(OP2, 3, VAL); \ 89 WRITE_WB_REG_CASE(OP2, 4, VAL); \ 90 WRITE_WB_REG_CASE(OP2, 5, VAL); \ 91 WRITE_WB_REG_CASE(OP2, 6, VAL); \ 92 WRITE_WB_REG_CASE(OP2, 7, VAL); \ 93 WRITE_WB_REG_CASE(OP2, 8, VAL); \ 94 WRITE_WB_REG_CASE(OP2, 9, VAL); \ 95 WRITE_WB_REG_CASE(OP2, 10, VAL); \ 96 WRITE_WB_REG_CASE(OP2, 11, VAL); \ 97 WRITE_WB_REG_CASE(OP2, 12, VAL); \ 98 WRITE_WB_REG_CASE(OP2, 13, VAL); \ 99 WRITE_WB_REG_CASE(OP2, 14, VAL); \ 100 WRITE_WB_REG_CASE(OP2, 15, VAL) 101 102static u32 read_wb_reg(int n) 103{ 104 u32 val = 0; 105 106 switch (n) { 107 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); 108 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); 109 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); 110 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); 111 default: 112 pr_warning("attempt to read from unknown breakpoint " 113 "register %d\n", n); 114 } 115 116 return val; 117} 118 119static void write_wb_reg(int n, u32 val) 120{ 121 switch (n) { 122 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val); 123 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val); 124 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); 125 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); 126 default: 127 pr_warning("attempt to write to unknown breakpoint " 128 "register %d\n", n); 129 } 130 isb(); 131} 132 133/* Determine debug architecture. */ 134static u8 get_debug_arch(void) 135{ 136 u32 didr; 137 138 /* Do we implement the extended CPUID interface? */ 139 if (WARN_ONCE((((read_cpuid_id() >> 16) & 0xf) != 0xf), 140 "CPUID feature registers not supported. " 141 "Assuming v6 debug is present.\n")) 142 return ARM_DEBUG_ARCH_V6; 143 144 ARM_DBG_READ(c0, 0, didr); 145 return (didr >> 16) & 0xf; 146} 147 148u8 arch_get_debug_arch(void) 149{ 150 return debug_arch; 151} 152 153static int debug_arch_supported(void) 154{ 155 u8 arch = get_debug_arch(); 156 157 /* We don't support the memory-mapped interface. */ 158 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) || 159 arch >= ARM_DEBUG_ARCH_V7_1; 160} 161 162/* Determine number of WRP registers available. */ 163static int get_num_wrp_resources(void) 164{ 165 u32 didr; 166 ARM_DBG_READ(c0, 0, didr); 167 return ((didr >> 28) & 0xf) + 1; 168} 169 170/* Determine number of BRP registers available. */ 171static int get_num_brp_resources(void) 172{ 173 u32 didr; 174 ARM_DBG_READ(c0, 0, didr); 175 return ((didr >> 24) & 0xf) + 1; 176} 177 178/* Does this core support mismatch breakpoints? */ 179static int core_has_mismatch_brps(void) 180{ 181 return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 && 182 get_num_brp_resources() > 1); 183} 184 185/* Determine number of usable WRPs available. */ 186static int get_num_wrps(void) 187{ 188 /* 189 * On debug architectures prior to 7.1, when a watchpoint fires, the 190 * only way to work out which watchpoint it was is by disassembling 191 * the faulting instruction and working out the address of the memory 192 * access. 193 * 194 * Furthermore, we can only do this if the watchpoint was precise 195 * since imprecise watchpoints prevent us from calculating register 196 * based addresses. 197 * 198 * Providing we have more than 1 breakpoint register, we only report 199 * a single watchpoint register for the time being. This way, we always 200 * know which watchpoint fired. In the future we can either add a 201 * disassembler and address generation emulator, or we can insert a 202 * check to see if the DFAR is set on watchpoint exception entry 203 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows 204 * that it is set on some implementations]. 205 */ 206 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1) 207 return 1; 208 209 return get_num_wrp_resources(); 210} 211 212/* Determine number of usable BRPs available. */ 213static int get_num_brps(void) 214{ 215 int brps = get_num_brp_resources(); 216 return core_has_mismatch_brps() ? brps - 1 : brps; 217} 218 219/* 220 * In order to access the breakpoint/watchpoint control registers, 221 * we must be running in debug monitor mode. Unfortunately, we can 222 * be put into halting debug mode at any time by an external debugger 223 * but there is nothing we can do to prevent that. 224 */ 225static int enable_monitor_mode(void) 226{ 227 u32 dscr; 228 int ret = 0; 229 230 ARM_DBG_READ(c1, 0, dscr); 231 232 /* Ensure that halting mode is disabled. */ 233 if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, 234 "halting debug mode enabled. Unable to access hardware resources.\n")) { 235 ret = -EPERM; 236 goto out; 237 } 238 239 /* If monitor mode is already enabled, just return. */ 240 if (dscr & ARM_DSCR_MDBGEN) 241 goto out; 242 243 /* Write to the corresponding DSCR. */ 244 switch (get_debug_arch()) { 245 case ARM_DEBUG_ARCH_V6: 246 case ARM_DEBUG_ARCH_V6_1: 247 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); 248 break; 249 case ARM_DEBUG_ARCH_V7_ECP14: 250 case ARM_DEBUG_ARCH_V7_1: 251 ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); 252 break; 253 default: 254 ret = -ENODEV; 255 goto out; 256 } 257 258 /* Check that the write made it through. */ 259 ARM_DBG_READ(c1, 0, dscr); 260 if (!(dscr & ARM_DSCR_MDBGEN)) 261 ret = -EPERM; 262 263out: 264 return ret; 265} 266 267int hw_breakpoint_slots(int type) 268{ 269 if (!debug_arch_supported()) 270 return 0; 271 272 /* 273 * We can be called early, so don't rely on 274 * our static variables being initialised. 275 */ 276 switch (type) { 277 case TYPE_INST: 278 return get_num_brps(); 279 case TYPE_DATA: 280 return get_num_wrps(); 281 default: 282 pr_warning("unknown slot type: %d\n", type); 283 return 0; 284 } 285} 286 287/* 288 * Check if 8-bit byte-address select is available. 289 * This clobbers WRP 0. 290 */ 291static u8 get_max_wp_len(void) 292{ 293 u32 ctrl_reg; 294 struct arch_hw_breakpoint_ctrl ctrl; 295 u8 size = 4; 296 297 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) 298 goto out; 299 300 memset(&ctrl, 0, sizeof(ctrl)); 301 ctrl.len = ARM_BREAKPOINT_LEN_8; 302 ctrl_reg = encode_ctrl_reg(ctrl); 303 304 write_wb_reg(ARM_BASE_WVR, 0); 305 write_wb_reg(ARM_BASE_WCR, ctrl_reg); 306 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) 307 size = 8; 308 309out: 310 return size; 311} 312 313u8 arch_get_max_wp_len(void) 314{ 315 return max_watchpoint_len; 316} 317 318/* 319 * Install a perf counter breakpoint. 320 */ 321int arch_install_hw_breakpoint(struct perf_event *bp) 322{ 323 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 324 struct perf_event **slot, **slots; 325 int i, max_slots, ctrl_base, val_base, ret = 0; 326 u32 addr, ctrl; 327 328 /* Ensure that we are in monitor mode and halting mode is disabled. */ 329 ret = enable_monitor_mode(); 330 if (ret) 331 goto out; 332 333 addr = info->address; 334 ctrl = encode_ctrl_reg(info->ctrl) | 0x1; 335 336 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 337 /* Breakpoint */ 338 ctrl_base = ARM_BASE_BCR; 339 val_base = ARM_BASE_BVR; 340 slots = (struct perf_event **)__get_cpu_var(bp_on_reg); 341 max_slots = core_num_brps; 342 if (info->step_ctrl.enabled) { 343 /* Override the breakpoint data with the step data. */ 344 addr = info->trigger & ~0x3; 345 ctrl = encode_ctrl_reg(info->step_ctrl); 346 } 347 } else { 348 /* Watchpoint */ 349 if (info->step_ctrl.enabled) { 350 /* Install into the reserved breakpoint region. */ 351 ctrl_base = ARM_BASE_BCR + core_num_brps; 352 val_base = ARM_BASE_BVR + core_num_brps; 353 /* Override the watchpoint data with the step data. */ 354 addr = info->trigger & ~0x3; 355 ctrl = encode_ctrl_reg(info->step_ctrl); 356 } else { 357 ctrl_base = ARM_BASE_WCR; 358 val_base = ARM_BASE_WVR; 359 } 360 slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 361 max_slots = core_num_wrps; 362 } 363 364 for (i = 0; i < max_slots; ++i) { 365 slot = &slots[i]; 366 367 if (!*slot) { 368 *slot = bp; 369 break; 370 } 371 } 372 373 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) { 374 ret = -EBUSY; 375 goto out; 376 } 377 378 /* Setup the address register. */ 379 write_wb_reg(val_base + i, addr); 380 381 /* Setup the control register. */ 382 write_wb_reg(ctrl_base + i, ctrl); 383 384out: 385 return ret; 386} 387 388void arch_uninstall_hw_breakpoint(struct perf_event *bp) 389{ 390 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 391 struct perf_event **slot, **slots; 392 int i, max_slots, base; 393 394 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 395 /* Breakpoint */ 396 base = ARM_BASE_BCR; 397 slots = (struct perf_event **)__get_cpu_var(bp_on_reg); 398 max_slots = core_num_brps; 399 } else { 400 /* Watchpoint */ 401 if (info->step_ctrl.enabled) 402 base = ARM_BASE_BCR + core_num_brps; 403 else 404 base = ARM_BASE_WCR; 405 slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 406 max_slots = core_num_wrps; 407 } 408 409 /* Remove the breakpoint. */ 410 for (i = 0; i < max_slots; ++i) { 411 slot = &slots[i]; 412 413 if (*slot == bp) { 414 *slot = NULL; 415 break; 416 } 417 } 418 419 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) 420 return; 421 422 /* Reset the control register. */ 423 write_wb_reg(base + i, 0); 424} 425 426static int get_hbp_len(u8 hbp_len) 427{ 428 unsigned int len_in_bytes = 0; 429 430 switch (hbp_len) { 431 case ARM_BREAKPOINT_LEN_1: 432 len_in_bytes = 1; 433 break; 434 case ARM_BREAKPOINT_LEN_2: 435 len_in_bytes = 2; 436 break; 437 case ARM_BREAKPOINT_LEN_4: 438 len_in_bytes = 4; 439 break; 440 case ARM_BREAKPOINT_LEN_8: 441 len_in_bytes = 8; 442 break; 443 } 444 445 return len_in_bytes; 446} 447 448/* 449 * Check whether bp virtual address is in kernel space. 450 */ 451int arch_check_bp_in_kernelspace(struct perf_event *bp) 452{ 453 unsigned int len; 454 unsigned long va; 455 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 456 457 va = info->address; 458 len = get_hbp_len(info->ctrl.len); 459 460 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); 461} 462 463/* 464 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. 465 * Hopefully this will disappear when ptrace can bypass the conversion 466 * to generic breakpoint descriptions. 467 */ 468int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, 469 int *gen_len, int *gen_type) 470{ 471 /* Type */ 472 switch (ctrl.type) { 473 case ARM_BREAKPOINT_EXECUTE: 474 *gen_type = HW_BREAKPOINT_X; 475 break; 476 case ARM_BREAKPOINT_LOAD: 477 *gen_type = HW_BREAKPOINT_R; 478 break; 479 case ARM_BREAKPOINT_STORE: 480 *gen_type = HW_BREAKPOINT_W; 481 break; 482 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: 483 *gen_type = HW_BREAKPOINT_RW; 484 break; 485 default: 486 return -EINVAL; 487 } 488 489 /* Len */ 490 switch (ctrl.len) { 491 case ARM_BREAKPOINT_LEN_1: 492 *gen_len = HW_BREAKPOINT_LEN_1; 493 break; 494 case ARM_BREAKPOINT_LEN_2: 495 *gen_len = HW_BREAKPOINT_LEN_2; 496 break; 497 case ARM_BREAKPOINT_LEN_4: 498 *gen_len = HW_BREAKPOINT_LEN_4; 499 break; 500 case ARM_BREAKPOINT_LEN_8: 501 *gen_len = HW_BREAKPOINT_LEN_8; 502 break; 503 default: 504 return -EINVAL; 505 } 506 507 return 0; 508} 509 510/* 511 * Construct an arch_hw_breakpoint from a perf_event. 512 */ 513static int arch_build_bp_info(struct perf_event *bp) 514{ 515 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 516 517 /* Type */ 518 switch (bp->attr.bp_type) { 519 case HW_BREAKPOINT_X: 520 info->ctrl.type = ARM_BREAKPOINT_EXECUTE; 521 break; 522 case HW_BREAKPOINT_R: 523 info->ctrl.type = ARM_BREAKPOINT_LOAD; 524 break; 525 case HW_BREAKPOINT_W: 526 info->ctrl.type = ARM_BREAKPOINT_STORE; 527 break; 528 case HW_BREAKPOINT_RW: 529 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; 530 break; 531 default: 532 return -EINVAL; 533 } 534 535 /* Len */ 536 switch (bp->attr.bp_len) { 537 case HW_BREAKPOINT_LEN_1: 538 info->ctrl.len = ARM_BREAKPOINT_LEN_1; 539 break; 540 case HW_BREAKPOINT_LEN_2: 541 info->ctrl.len = ARM_BREAKPOINT_LEN_2; 542 break; 543 case HW_BREAKPOINT_LEN_4: 544 info->ctrl.len = ARM_BREAKPOINT_LEN_4; 545 break; 546 case HW_BREAKPOINT_LEN_8: 547 info->ctrl.len = ARM_BREAKPOINT_LEN_8; 548 if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE) 549 && max_watchpoint_len >= 8) 550 break; 551 default: 552 return -EINVAL; 553 } 554 555 /* 556 * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes. 557 * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported 558 * by the hardware and must be aligned to the appropriate number of 559 * bytes. 560 */ 561 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE && 562 info->ctrl.len != ARM_BREAKPOINT_LEN_2 && 563 info->ctrl.len != ARM_BREAKPOINT_LEN_4) 564 return -EINVAL; 565 566 /* Address */ 567 info->address = bp->attr.bp_addr; 568 569 /* Privilege */ 570 info->ctrl.privilege = ARM_BREAKPOINT_USER; 571 if (arch_check_bp_in_kernelspace(bp)) 572 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; 573 574 /* Enabled? */ 575 info->ctrl.enabled = !bp->attr.disabled; 576 577 /* Mismatch */ 578 info->ctrl.mismatch = 0; 579 580 return 0; 581} 582 583/* 584 * Validate the arch-specific HW Breakpoint register settings. 585 */ 586int arch_validate_hwbkpt_settings(struct perf_event *bp) 587{ 588 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 589 int ret = 0; 590 u32 offset, alignment_mask = 0x3; 591 592 /* Build the arch_hw_breakpoint. */ 593 ret = arch_build_bp_info(bp); 594 if (ret) 595 goto out; 596 597 /* Check address alignment. */ 598 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) 599 alignment_mask = 0x7; 600 offset = info->address & alignment_mask; 601 switch (offset) { 602 case 0: 603 /* Aligned */ 604 break; 605 case 1: 606 /* Allow single byte watchpoint. */ 607 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) 608 break; 609 case 2: 610 /* Allow halfword watchpoints and breakpoints. */ 611 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) 612 break; 613 default: 614 ret = -EINVAL; 615 goto out; 616 } 617 618 info->address &= ~alignment_mask; 619 info->ctrl.len <<= offset; 620 621 /* 622 * Currently we rely on an overflow handler to take 623 * care of single-stepping the breakpoint when it fires. 624 * In the case of userspace breakpoints on a core with V7 debug, 625 * we can use the mismatch feature as a poor-man's hardware 626 * single-step, but this only works for per-task breakpoints. 627 */ 628 if (WARN_ONCE(!bp->overflow_handler && 629 (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps() 630 || !bp->hw.bp_target), 631 "overflow handler required but none found\n")) { 632 ret = -EINVAL; 633 } 634out: 635 return ret; 636} 637 638/* 639 * Enable/disable single-stepping over the breakpoint bp at address addr. 640 */ 641static void enable_single_step(struct perf_event *bp, u32 addr) 642{ 643 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 644 645 arch_uninstall_hw_breakpoint(bp); 646 info->step_ctrl.mismatch = 1; 647 info->step_ctrl.len = ARM_BREAKPOINT_LEN_4; 648 info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE; 649 info->step_ctrl.privilege = info->ctrl.privilege; 650 info->step_ctrl.enabled = 1; 651 info->trigger = addr; 652 arch_install_hw_breakpoint(bp); 653} 654 655static void disable_single_step(struct perf_event *bp) 656{ 657 arch_uninstall_hw_breakpoint(bp); 658 counter_arch_bp(bp)->step_ctrl.enabled = 0; 659 arch_install_hw_breakpoint(bp); 660} 661 662static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) 663{ 664 int i; 665 struct perf_event *wp, **slots; 666 struct arch_hw_breakpoint *info; 667 668 slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 669 670 /* Without a disassembler, we can only handle 1 watchpoint. */ 671 BUG_ON(core_num_wrps > 1); 672 673 for (i = 0; i < core_num_wrps; ++i) { 674 rcu_read_lock(); 675 676 wp = slots[i]; 677 678 if (wp == NULL) { 679 rcu_read_unlock(); 680 continue; 681 } 682 683 /* 684 * The DFAR is an unknown value. Since we only allow a 685 * single watchpoint, we can set the trigger to the lowest 686 * possible faulting address. 687 */ 688 info = counter_arch_bp(wp); 689 info->trigger = wp->attr.bp_addr; 690 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); 691 perf_bp_event(wp, regs); 692 693 /* 694 * If no overflow handler is present, insert a temporary 695 * mismatch breakpoint so we can single-step over the 696 * watchpoint trigger. 697 */ 698 if (!wp->overflow_handler) 699 enable_single_step(wp, instruction_pointer(regs)); 700 701 rcu_read_unlock(); 702 } 703} 704 705static void watchpoint_single_step_handler(unsigned long pc) 706{ 707 int i; 708 struct perf_event *wp, **slots; 709 struct arch_hw_breakpoint *info; 710 711 slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 712 713 for (i = 0; i < core_num_wrps; ++i) { 714 rcu_read_lock(); 715 716 wp = slots[i]; 717 718 if (wp == NULL) 719 goto unlock; 720 721 info = counter_arch_bp(wp); 722 if (!info->step_ctrl.enabled) 723 goto unlock; 724 725 /* 726 * Restore the original watchpoint if we've completed the 727 * single-step. 728 */ 729 if (info->trigger != pc) 730 disable_single_step(wp); 731 732unlock: 733 rcu_read_unlock(); 734 } 735} 736 737static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) 738{ 739 int i; 740 u32 ctrl_reg, val, addr; 741 struct perf_event *bp, **slots; 742 struct arch_hw_breakpoint *info; 743 struct arch_hw_breakpoint_ctrl ctrl; 744 745 slots = (struct perf_event **)__get_cpu_var(bp_on_reg); 746 747 /* The exception entry code places the amended lr in the PC. */ 748 addr = regs->ARM_pc; 749 750 /* Check the currently installed breakpoints first. */ 751 for (i = 0; i < core_num_brps; ++i) { 752 rcu_read_lock(); 753 754 bp = slots[i]; 755 756 if (bp == NULL) 757 goto unlock; 758 759 info = counter_arch_bp(bp); 760 761 /* Check if the breakpoint value matches. */ 762 val = read_wb_reg(ARM_BASE_BVR + i); 763 if (val != (addr & ~0x3)) 764 goto mismatch; 765 766 /* Possible match, check the byte address select to confirm. */ 767 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); 768 decode_ctrl_reg(ctrl_reg, &ctrl); 769 if ((1 << (addr & 0x3)) & ctrl.len) { 770 info->trigger = addr; 771 pr_debug("breakpoint fired: address = 0x%x\n", addr); 772 perf_bp_event(bp, regs); 773 if (!bp->overflow_handler) 774 enable_single_step(bp, addr); 775 goto unlock; 776 } 777 778mismatch: 779 /* If we're stepping a breakpoint, it can now be restored. */ 780 if (info->step_ctrl.enabled) 781 disable_single_step(bp); 782unlock: 783 rcu_read_unlock(); 784 } 785 786 /* Handle any pending watchpoint single-step breakpoints. */ 787 watchpoint_single_step_handler(addr); 788} 789 790/* 791 * Called from either the Data Abort Handler [watchpoint] or the 792 * Prefetch Abort Handler [breakpoint] with interrupts disabled. 793 */ 794static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, 795 struct pt_regs *regs) 796{ 797 int ret = 0; 798 u32 dscr; 799 800 preempt_disable(); 801 802 if (interrupts_enabled(regs)) 803 local_irq_enable(); 804 805 /* We only handle watchpoints and hardware breakpoints. */ 806 ARM_DBG_READ(c1, 0, dscr); 807 808 /* Perform perf callbacks. */ 809 switch (ARM_DSCR_MOE(dscr)) { 810 case ARM_ENTRY_BREAKPOINT: 811 breakpoint_handler(addr, regs); 812 break; 813 case ARM_ENTRY_ASYNC_WATCHPOINT: 814 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); 815 case ARM_ENTRY_SYNC_WATCHPOINT: 816 watchpoint_handler(addr, regs); 817 break; 818 default: 819 ret = 1; /* Unhandled fault. */ 820 } 821 822 preempt_enable(); 823 824 return ret; 825} 826 827/* 828 * One-time initialisation. 829 */ 830static void reset_ctrl_regs(void *info) 831{ 832 int i, raw_num_brps, err = 0, cpu = smp_processor_id(); 833 u32 dbg_power; 834 cpumask_t *cpumask = info; 835 836 /* 837 * v7 debug contains save and restore registers so that debug state 838 * can be maintained across low-power modes without leaving the debug 839 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access 840 * the debug registers out of reset, so we must unlock the OS Lock 841 * Access Register to avoid taking undefined instruction exceptions 842 * later on. 843 */ 844 switch (debug_arch) { 845 case ARM_DEBUG_ARCH_V7_ECP14: 846 /* 847 * Ensure sticky power-down is clear (i.e. debug logic is 848 * powered up). 849 */ 850 asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power)); 851 if ((dbg_power & 0x1) == 0) 852 err = -EPERM; 853 break; 854 case ARM_DEBUG_ARCH_V7_1: 855 /* 856 * Ensure the OS double lock is clear. 857 */ 858 asm volatile("mrc p14, 0, %0, c1, c3, 4" : "=r" (dbg_power)); 859 if ((dbg_power & 0x1) == 1) 860 err = -EPERM; 861 break; 862 } 863 864 if (err) { 865 pr_warning("CPU %d debug is powered down!\n", cpu); 866 cpumask_or(cpumask, cpumask, cpumask_of(cpu)); 867 return; 868 } 869 870 /* 871 * Unconditionally clear the lock by writing a value 872 * other than 0xC5ACCE55 to the access register. 873 */ 874 asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); 875 isb(); 876 877 /* 878 * Clear any configured vector-catch events before 879 * enabling monitor mode. 880 */ 881 asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0)); 882 isb(); 883 884 if (enable_monitor_mode()) 885 return; 886 887 /* We must also reset any reserved registers. */ 888 raw_num_brps = get_num_brp_resources(); 889 for (i = 0; i < raw_num_brps; ++i) { 890 write_wb_reg(ARM_BASE_BCR + i, 0UL); 891 write_wb_reg(ARM_BASE_BVR + i, 0UL); 892 } 893 894 for (i = 0; i < core_num_wrps; ++i) { 895 write_wb_reg(ARM_BASE_WCR + i, 0UL); 896 write_wb_reg(ARM_BASE_WVR + i, 0UL); 897 } 898} 899 900static int __cpuinit dbg_reset_notify(struct notifier_block *self, 901 unsigned long action, void *cpu) 902{ 903 if (action == CPU_ONLINE) 904 smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); 905 return NOTIFY_OK; 906} 907 908static struct notifier_block __cpuinitdata dbg_reset_nb = { 909 .notifier_call = dbg_reset_notify, 910}; 911 912static int __init arch_hw_breakpoint_init(void) 913{ 914 u32 dscr; 915 cpumask_t cpumask = { CPU_BITS_NONE }; 916 917 debug_arch = get_debug_arch(); 918 919 if (!debug_arch_supported()) { 920 pr_info("debug architecture 0x%x unsupported.\n", debug_arch); 921 return 0; 922 } 923 924 /* Determine how many BRPs/WRPs are available. */ 925 core_num_brps = get_num_brps(); 926 core_num_wrps = get_num_wrps(); 927 928 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n", 929 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " : 930 "", core_num_wrps); 931 932 /* 933 * Reset the breakpoint resources. We assume that a halting 934 * debugger will leave the world in a nice state for us. 935 */ 936 on_each_cpu(reset_ctrl_regs, &cpumask, 1); 937 if (!cpumask_empty(&cpumask)) { 938 core_num_brps = 0; 939 core_num_wrps = 0; 940 return 0; 941 } 942 943 ARM_DBG_READ(c1, 0, dscr); 944 if (dscr & ARM_DSCR_HDBGEN) { 945 max_watchpoint_len = 4; 946 pr_warning("halting debug mode enabled. Assuming maximum watchpoint size of %u bytes.\n", 947 max_watchpoint_len); 948 } else { 949 /* Work out the maximum supported watchpoint length. */ 950 max_watchpoint_len = get_max_wp_len(); 951 pr_info("maximum watchpoint size is %u bytes.\n", 952 max_watchpoint_len); 953 } 954 955 /* Register debug fault handler. */ 956 hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, 957 "watchpoint debug exception"); 958 hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, 959 "breakpoint debug exception"); 960 961 /* Register hotplug notifier. */ 962 register_cpu_notifier(&dbg_reset_nb); 963 return 0; 964} 965arch_initcall(arch_hw_breakpoint_init); 966 967void hw_breakpoint_pmu_read(struct perf_event *bp) 968{ 969} 970 971/* 972 * Dummy function to register with die_notifier. 973 */ 974int hw_breakpoint_exceptions_notify(struct notifier_block *unused, 975 unsigned long val, void *data) 976{ 977 return NOTIFY_DONE; 978} 979