clock.c revision 1c8daabe1dafc30fcc1d929e620269ffe99b6f8a 
1/*
2 * arch/arm/mach-ep93xx/clock.c
3 * Clock control for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/clk.h>
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/string.h>
18#include <linux/io.h>
19
20#include <asm/clkdev.h>
21#include <asm/div64.h>
22#include <mach/hardware.h>
23
24struct clk {
25	unsigned long	rate;
26	int		users;
27	u32		enable_reg;
28	u32		enable_mask;
29};
30
31static struct clk clk_uart = {
32	.rate		= 14745600,
33};
34static struct clk clk_pll1;
35static struct clk clk_f;
36static struct clk clk_h;
37static struct clk clk_p;
38static struct clk clk_pll2;
39static struct clk clk_usb_host = {
40	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
41	.enable_mask	= EP93XX_SYSCON_CLOCK_USH_EN,
42};
43
44/* DMA Clocks */
45static struct clk clk_m2p0 = {
46	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
47	.enable_mask	= 0x00020000,
48};
49static struct clk clk_m2p1 = {
50	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
51	.enable_mask	= 0x00010000,
52};
53static struct clk clk_m2p2 = {
54	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
55	.enable_mask	= 0x00080000,
56};
57static struct clk clk_m2p3 = {
58	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
59	.enable_mask	= 0x00040000,
60};
61static struct clk clk_m2p4 = {
62	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
63	.enable_mask	= 0x00200000,
64};
65static struct clk clk_m2p5 = {
66	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
67	.enable_mask	= 0x00100000,
68};
69static struct clk clk_m2p6 = {
70	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
71	.enable_mask	= 0x00800000,
72};
73static struct clk clk_m2p7 = {
74	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
75	.enable_mask	= 0x00400000,
76};
77static struct clk clk_m2p8 = {
78	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
79	.enable_mask	= 0x02000000,
80};
81static struct clk clk_m2p9 = {
82	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
83	.enable_mask	= 0x01000000,
84};
85static struct clk clk_m2m0 = {
86	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
87	.enable_mask	= 0x04000000,
88};
89static struct clk clk_m2m1 = {
90	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
91	.enable_mask	= 0x08000000,
92};
93
94#define INIT_CK(dev,con,ck)					\
95	{ .dev_id = dev, .con_id = con, .clk = ck }
96
97static struct clk_lookup clocks[] = {
98	INIT_CK("apb:uart1", NULL, &clk_uart),
99	INIT_CK("apb:uart2", NULL, &clk_uart),
100	INIT_CK("apb:uart3", NULL, &clk_uart),
101	INIT_CK(NULL, "pll1", &clk_pll1),
102	INIT_CK(NULL, "fclk", &clk_f),
103	INIT_CK(NULL, "hclk", &clk_h),
104	INIT_CK(NULL, "pclk", &clk_p),
105	INIT_CK(NULL, "pll2", &clk_pll2),
106	INIT_CK(NULL, "usb_host", &clk_usb_host),
107	INIT_CK(NULL, "m2p0", &clk_m2p0),
108	INIT_CK(NULL, "m2p1", &clk_m2p1),
109	INIT_CK(NULL, "m2p2", &clk_m2p2),
110	INIT_CK(NULL, "m2p3", &clk_m2p3),
111	INIT_CK(NULL, "m2p4", &clk_m2p4),
112	INIT_CK(NULL, "m2p5", &clk_m2p5),
113	INIT_CK(NULL, "m2p6", &clk_m2p6),
114	INIT_CK(NULL, "m2p7", &clk_m2p7),
115	INIT_CK(NULL, "m2p8", &clk_m2p8),
116	INIT_CK(NULL, "m2p9", &clk_m2p9),
117	INIT_CK(NULL, "m2m0", &clk_m2m0),
118	INIT_CK(NULL, "m2m1", &clk_m2m1),
119};
120
121
122int clk_enable(struct clk *clk)
123{
124	if (!clk->users++ && clk->enable_reg) {
125		u32 value;
126
127		value = __raw_readl(clk->enable_reg);
128		__raw_writel(value | clk->enable_mask, clk->enable_reg);
129	}
130
131	return 0;
132}
133EXPORT_SYMBOL(clk_enable);
134
135void clk_disable(struct clk *clk)
136{
137	if (!--clk->users && clk->enable_reg) {
138		u32 value;
139
140		value = __raw_readl(clk->enable_reg);
141		__raw_writel(value & ~clk->enable_mask, clk->enable_reg);
142	}
143}
144EXPORT_SYMBOL(clk_disable);
145
146unsigned long clk_get_rate(struct clk *clk)
147{
148	return clk->rate;
149}
150EXPORT_SYMBOL(clk_get_rate);
151
152
153static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
154static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
155static char pclk_divisors[] = { 1, 2, 4, 8 };
156
157/*
158 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
159 */
160static unsigned long calc_pll_rate(u32 config_word)
161{
162	unsigned long long rate;
163	int i;
164
165	rate = 14745600;
166	rate *= ((config_word >> 11) & 0x1f) + 1;		/* X1FBD */
167	rate *= ((config_word >> 5) & 0x3f) + 1;		/* X2FBD */
168	do_div(rate, (config_word & 0x1f) + 1);			/* X2IPD */
169	for (i = 0; i < ((config_word >> 16) & 3); i++)		/* PS */
170		rate >>= 1;
171
172	return (unsigned long)rate;
173}
174
175static void __init ep93xx_dma_clock_init(void)
176{
177	clk_m2p0.rate = clk_h.rate;
178	clk_m2p1.rate = clk_h.rate;
179	clk_m2p2.rate = clk_h.rate;
180	clk_m2p3.rate = clk_h.rate;
181	clk_m2p4.rate = clk_h.rate;
182	clk_m2p5.rate = clk_h.rate;
183	clk_m2p6.rate = clk_h.rate;
184	clk_m2p7.rate = clk_h.rate;
185	clk_m2p8.rate = clk_h.rate;
186	clk_m2p9.rate = clk_h.rate;
187	clk_m2m0.rate = clk_h.rate;
188	clk_m2m1.rate = clk_h.rate;
189}
190
191static int __init ep93xx_clock_init(void)
192{
193	u32 value;
194	int i;
195
196	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
197	if (!(value & 0x00800000)) {			/* PLL1 bypassed?  */
198		clk_pll1.rate = 14745600;
199	} else {
200		clk_pll1.rate = calc_pll_rate(value);
201	}
202	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
203	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
204	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
205	ep93xx_dma_clock_init();
206
207	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
208	if (!(value & 0x00080000)) {			/* PLL2 bypassed?  */
209		clk_pll2.rate = 14745600;
210	} else if (value & 0x00040000) {		/* PLL2 enabled?  */
211		clk_pll2.rate = calc_pll_rate(value);
212	} else {
213		clk_pll2.rate = 0;
214	}
215	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
216
217	printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
218		clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
219	printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
220		clk_f.rate / 1000000, clk_h.rate / 1000000,
221		clk_p.rate / 1000000);
222
223	for (i = 0; i < ARRAY_SIZE(clocks); i++)
224		clkdev_add(&clocks[i]);
225	return 0;
226}
227arch_initcall(ep93xx_clock_init);
228