clock.c revision 3126c7bc4106c572ef47e2c220df5a00e7973379
1/* 2 * arch/arm/mach-ep93xx/clock.c 3 * Clock control for Cirrus EP93xx chips. 4 * 5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or (at 10 * your option) any later version. 11 */ 12 13#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt 14 15#include <linux/kernel.h> 16#include <linux/clk.h> 17#include <linux/err.h> 18#include <linux/module.h> 19#include <linux/string.h> 20#include <linux/io.h> 21#include <linux/spinlock.h> 22 23#include <mach/hardware.h> 24 25#include <asm/clkdev.h> 26#include <asm/div64.h> 27 28 29struct clk { 30 struct clk *parent; 31 unsigned long rate; 32 int users; 33 int sw_locked; 34 void __iomem *enable_reg; 35 u32 enable_mask; 36 37 unsigned long (*get_rate)(struct clk *clk); 38 int (*set_rate)(struct clk *clk, unsigned long rate); 39}; 40 41 42static unsigned long get_uart_rate(struct clk *clk); 43 44static int set_keytchclk_rate(struct clk *clk, unsigned long rate); 45static int set_div_rate(struct clk *clk, unsigned long rate); 46 47 48static struct clk clk_xtali = { 49 .rate = EP93XX_EXT_CLK_RATE, 50}; 51static struct clk clk_uart1 = { 52 .parent = &clk_xtali, 53 .sw_locked = 1, 54 .enable_reg = EP93XX_SYSCON_DEVCFG, 55 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN, 56 .get_rate = get_uart_rate, 57}; 58static struct clk clk_uart2 = { 59 .parent = &clk_xtali, 60 .sw_locked = 1, 61 .enable_reg = EP93XX_SYSCON_DEVCFG, 62 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN, 63 .get_rate = get_uart_rate, 64}; 65static struct clk clk_uart3 = { 66 .parent = &clk_xtali, 67 .sw_locked = 1, 68 .enable_reg = EP93XX_SYSCON_DEVCFG, 69 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN, 70 .get_rate = get_uart_rate, 71}; 72static struct clk clk_pll1 = { 73 .parent = &clk_xtali, 74}; 75static struct clk clk_f = { 76 .parent = &clk_pll1, 77}; 78static struct clk clk_h = { 79 .parent = &clk_pll1, 80}; 81static struct clk clk_p = { 82 .parent = &clk_pll1, 83}; 84static struct clk clk_pll2 = { 85 .parent = &clk_xtali, 86}; 87static struct clk clk_usb_host = { 88 .parent = &clk_pll2, 89 .enable_reg = EP93XX_SYSCON_PWRCNT, 90 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, 91}; 92static struct clk clk_keypad = { 93 .parent = &clk_xtali, 94 .sw_locked = 1, 95 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV, 96 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN, 97 .set_rate = set_keytchclk_rate, 98}; 99static struct clk clk_spi = { 100 .parent = &clk_xtali, 101 .rate = EP93XX_EXT_CLK_RATE, 102}; 103static struct clk clk_pwm = { 104 .parent = &clk_xtali, 105 .rate = EP93XX_EXT_CLK_RATE, 106}; 107 108static struct clk clk_video = { 109 .sw_locked = 1, 110 .enable_reg = EP93XX_SYSCON_VIDCLKDIV, 111 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE, 112 .set_rate = set_div_rate, 113}; 114 115/* DMA Clocks */ 116static struct clk clk_m2p0 = { 117 .parent = &clk_h, 118 .enable_reg = EP93XX_SYSCON_PWRCNT, 119 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0, 120}; 121static struct clk clk_m2p1 = { 122 .parent = &clk_h, 123 .enable_reg = EP93XX_SYSCON_PWRCNT, 124 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1, 125}; 126static struct clk clk_m2p2 = { 127 .parent = &clk_h, 128 .enable_reg = EP93XX_SYSCON_PWRCNT, 129 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2, 130}; 131static struct clk clk_m2p3 = { 132 .parent = &clk_h, 133 .enable_reg = EP93XX_SYSCON_PWRCNT, 134 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3, 135}; 136static struct clk clk_m2p4 = { 137 .parent = &clk_h, 138 .enable_reg = EP93XX_SYSCON_PWRCNT, 139 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4, 140}; 141static struct clk clk_m2p5 = { 142 .parent = &clk_h, 143 .enable_reg = EP93XX_SYSCON_PWRCNT, 144 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5, 145}; 146static struct clk clk_m2p6 = { 147 .parent = &clk_h, 148 .enable_reg = EP93XX_SYSCON_PWRCNT, 149 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6, 150}; 151static struct clk clk_m2p7 = { 152 .parent = &clk_h, 153 .enable_reg = EP93XX_SYSCON_PWRCNT, 154 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7, 155}; 156static struct clk clk_m2p8 = { 157 .parent = &clk_h, 158 .enable_reg = EP93XX_SYSCON_PWRCNT, 159 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8, 160}; 161static struct clk clk_m2p9 = { 162 .parent = &clk_h, 163 .enable_reg = EP93XX_SYSCON_PWRCNT, 164 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9, 165}; 166static struct clk clk_m2m0 = { 167 .parent = &clk_h, 168 .enable_reg = EP93XX_SYSCON_PWRCNT, 169 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0, 170}; 171static struct clk clk_m2m1 = { 172 .parent = &clk_h, 173 .enable_reg = EP93XX_SYSCON_PWRCNT, 174 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1, 175}; 176 177#define INIT_CK(dev,con,ck) \ 178 { .dev_id = dev, .con_id = con, .clk = ck } 179 180static struct clk_lookup clocks[] = { 181 INIT_CK(NULL, "xtali", &clk_xtali), 182 INIT_CK("apb:uart1", NULL, &clk_uart1), 183 INIT_CK("apb:uart2", NULL, &clk_uart2), 184 INIT_CK("apb:uart3", NULL, &clk_uart3), 185 INIT_CK(NULL, "pll1", &clk_pll1), 186 INIT_CK(NULL, "fclk", &clk_f), 187 INIT_CK(NULL, "hclk", &clk_h), 188 INIT_CK(NULL, "apb_pclk", &clk_p), 189 INIT_CK(NULL, "pll2", &clk_pll2), 190 INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), 191 INIT_CK("ep93xx-keypad", NULL, &clk_keypad), 192 INIT_CK("ep93xx-fb", NULL, &clk_video), 193 INIT_CK("ep93xx-spi.0", NULL, &clk_spi), 194 INIT_CK(NULL, "pwm_clk", &clk_pwm), 195 INIT_CK(NULL, "m2p0", &clk_m2p0), 196 INIT_CK(NULL, "m2p1", &clk_m2p1), 197 INIT_CK(NULL, "m2p2", &clk_m2p2), 198 INIT_CK(NULL, "m2p3", &clk_m2p3), 199 INIT_CK(NULL, "m2p4", &clk_m2p4), 200 INIT_CK(NULL, "m2p5", &clk_m2p5), 201 INIT_CK(NULL, "m2p6", &clk_m2p6), 202 INIT_CK(NULL, "m2p7", &clk_m2p7), 203 INIT_CK(NULL, "m2p8", &clk_m2p8), 204 INIT_CK(NULL, "m2p9", &clk_m2p9), 205 INIT_CK(NULL, "m2m0", &clk_m2m0), 206 INIT_CK(NULL, "m2m1", &clk_m2m1), 207}; 208 209static DEFINE_SPINLOCK(clk_lock); 210 211static void __clk_enable(struct clk *clk) 212{ 213 if (!clk->users++) { 214 if (clk->parent) 215 __clk_enable(clk->parent); 216 217 if (clk->enable_reg) { 218 u32 v; 219 220 v = __raw_readl(clk->enable_reg); 221 v |= clk->enable_mask; 222 if (clk->sw_locked) 223 ep93xx_syscon_swlocked_write(v, clk->enable_reg); 224 else 225 __raw_writel(v, clk->enable_reg); 226 } 227 } 228} 229 230int clk_enable(struct clk *clk) 231{ 232 unsigned long flags; 233 234 if (!clk) 235 return -EINVAL; 236 237 spin_lock_irqsave(&clk_lock, flags); 238 __clk_enable(clk); 239 spin_unlock_irqrestore(&clk_lock, flags); 240 241 return 0; 242} 243EXPORT_SYMBOL(clk_enable); 244 245static void __clk_disable(struct clk *clk) 246{ 247 if (!--clk->users) { 248 if (clk->enable_reg) { 249 u32 v; 250 251 v = __raw_readl(clk->enable_reg); 252 v &= ~clk->enable_mask; 253 if (clk->sw_locked) 254 ep93xx_syscon_swlocked_write(v, clk->enable_reg); 255 else 256 __raw_writel(v, clk->enable_reg); 257 } 258 259 if (clk->parent) 260 __clk_disable(clk->parent); 261 } 262} 263 264void clk_disable(struct clk *clk) 265{ 266 unsigned long flags; 267 268 if (!clk) 269 return; 270 271 spin_lock_irqsave(&clk_lock, flags); 272 __clk_disable(clk); 273 spin_unlock_irqrestore(&clk_lock, flags); 274} 275EXPORT_SYMBOL(clk_disable); 276 277static unsigned long get_uart_rate(struct clk *clk) 278{ 279 unsigned long rate = clk_get_rate(clk->parent); 280 u32 value; 281 282 value = __raw_readl(EP93XX_SYSCON_PWRCNT); 283 if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) 284 return rate; 285 else 286 return rate / 2; 287} 288 289unsigned long clk_get_rate(struct clk *clk) 290{ 291 if (clk->get_rate) 292 return clk->get_rate(clk); 293 294 return clk->rate; 295} 296EXPORT_SYMBOL(clk_get_rate); 297 298static int set_keytchclk_rate(struct clk *clk, unsigned long rate) 299{ 300 u32 val; 301 u32 div_bit; 302 303 val = __raw_readl(clk->enable_reg); 304 305 /* 306 * The Key Matrix and ADC clocks are configured using the same 307 * System Controller register. The clock used will be either 308 * 1/4 or 1/16 the external clock rate depending on the 309 * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 310 * bit being set or cleared. 311 */ 312 div_bit = clk->enable_mask >> 15; 313 314 if (rate == EP93XX_KEYTCHCLK_DIV4) 315 val |= div_bit; 316 else if (rate == EP93XX_KEYTCHCLK_DIV16) 317 val &= ~div_bit; 318 else 319 return -EINVAL; 320 321 ep93xx_syscon_swlocked_write(val, clk->enable_reg); 322 clk->rate = rate; 323 return 0; 324} 325 326static int calc_clk_div(struct clk *clk, unsigned long rate, 327 int *psel, int *esel, int *pdiv, int *div) 328{ 329 struct clk *mclk; 330 unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1; 331 int i, found = 0, __div = 0, __pdiv = 0; 332 333 /* Don't exceed the maximum rate */ 334 max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4), 335 clk_xtali.rate / 4); 336 rate = min(rate, max_rate); 337 338 /* 339 * Try the two pll's and the external clock 340 * Because the valid predividers are 2, 2.5 and 3, we multiply 341 * all the clocks by 2 to avoid floating point math. 342 * 343 * This is based on the algorithm in the ep93xx raster guide: 344 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf 345 * 346 */ 347 for (i = 0; i < 3; i++) { 348 if (i == 0) 349 mclk = &clk_xtali; 350 else if (i == 1) 351 mclk = &clk_pll1; 352 else 353 mclk = &clk_pll2; 354 mclk_rate = mclk->rate * 2; 355 356 /* Try each predivider value */ 357 for (__pdiv = 4; __pdiv <= 6; __pdiv++) { 358 __div = mclk_rate / (rate * __pdiv); 359 if (__div < 2 || __div > 127) 360 continue; 361 362 actual_rate = mclk_rate / (__pdiv * __div); 363 364 if (!found || abs(actual_rate - rate) < rate_err) { 365 *pdiv = __pdiv - 3; 366 *div = __div; 367 *psel = (i == 2); 368 *esel = (i != 0); 369 clk->parent = mclk; 370 clk->rate = actual_rate; 371 rate_err = abs(actual_rate - rate); 372 found = 1; 373 } 374 } 375 } 376 377 if (!found) 378 return -EINVAL; 379 380 return 0; 381} 382 383static int set_div_rate(struct clk *clk, unsigned long rate) 384{ 385 int err, psel = 0, esel = 0, pdiv = 0, div = 0; 386 u32 val; 387 388 err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div); 389 if (err) 390 return err; 391 392 /* Clear the esel, psel, pdiv and div bits */ 393 val = __raw_readl(clk->enable_reg); 394 val &= ~0x7fff; 395 396 /* Set the new esel, psel, pdiv and div bits for the new clock rate */ 397 val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) | 398 (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) | 399 (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; 400 ep93xx_syscon_swlocked_write(val, clk->enable_reg); 401 return 0; 402} 403 404int clk_set_rate(struct clk *clk, unsigned long rate) 405{ 406 if (clk->set_rate) 407 return clk->set_rate(clk, rate); 408 409 return -EINVAL; 410} 411EXPORT_SYMBOL(clk_set_rate); 412 413 414static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; 415static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; 416static char pclk_divisors[] = { 1, 2, 4, 8 }; 417 418/* 419 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS 420 */ 421static unsigned long calc_pll_rate(u32 config_word) 422{ 423 unsigned long long rate; 424 int i; 425 426 rate = clk_xtali.rate; 427 rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ 428 rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ 429 do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ 430 for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */ 431 rate >>= 1; 432 433 return (unsigned long)rate; 434} 435 436static void __init ep93xx_dma_clock_init(void) 437{ 438 clk_m2p0.rate = clk_h.rate; 439 clk_m2p1.rate = clk_h.rate; 440 clk_m2p2.rate = clk_h.rate; 441 clk_m2p3.rate = clk_h.rate; 442 clk_m2p4.rate = clk_h.rate; 443 clk_m2p5.rate = clk_h.rate; 444 clk_m2p6.rate = clk_h.rate; 445 clk_m2p7.rate = clk_h.rate; 446 clk_m2p8.rate = clk_h.rate; 447 clk_m2p9.rate = clk_h.rate; 448 clk_m2m0.rate = clk_h.rate; 449 clk_m2m1.rate = clk_h.rate; 450} 451 452static int __init ep93xx_clock_init(void) 453{ 454 u32 value; 455 456 /* Determine the bootloader configured pll1 rate */ 457 value = __raw_readl(EP93XX_SYSCON_CLKSET1); 458 if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) 459 clk_pll1.rate = clk_xtali.rate; 460 else 461 clk_pll1.rate = calc_pll_rate(value); 462 463 /* Initialize the pll1 derived clocks */ 464 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; 465 clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; 466 clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; 467 ep93xx_dma_clock_init(); 468 469 /* Determine the bootloader configured pll2 rate */ 470 value = __raw_readl(EP93XX_SYSCON_CLKSET2); 471 if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) 472 clk_pll2.rate = clk_xtali.rate; 473 else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) 474 clk_pll2.rate = calc_pll_rate(value); 475 else 476 clk_pll2.rate = 0; 477 478 /* Initialize the pll2 derived clocks */ 479 clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); 480 481 /* 482 * EP93xx SSP clock rate was doubled in version E2. For more information 483 * see: 484 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf 485 */ 486 if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) 487 clk_spi.rate /= 2; 488 489 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", 490 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); 491 pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", 492 clk_f.rate / 1000000, clk_h.rate / 1000000, 493 clk_p.rate / 1000000); 494 495 clkdev_add_table(clocks, ARRAY_SIZE(clocks)); 496 return 0; 497} 498arch_initcall(ep93xx_clock_init); 499