core.c revision 999c53fb2200070bdb8923c1894f9e14a5ec2de3 
1/*
2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
7 *
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 */
16
17#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/interrupt.h>
23#include <linux/dma-mapping.h>
24#include <linux/timex.h>
25#include <linux/irq.h>
26#include <linux/io.h>
27#include <linux/gpio.h>
28#include <linux/leds.h>
29#include <linux/termios.h>
30#include <linux/amba/bus.h>
31#include <linux/amba/serial.h>
32#include <linux/mtd/physmap.h>
33#include <linux/i2c.h>
34#include <linux/i2c-gpio.h>
35#include <linux/spi/spi.h>
36#include <linux/export.h>
37
38#include <mach/hardware.h>
39#include <mach/fb.h>
40#include <mach/ep93xx_keypad.h>
41#include <mach/ep93xx_spi.h>
42#include <mach/gpio-ep93xx.h>
43
44#include <asm/mach/map.h>
45#include <asm/mach/time.h>
46
47#include <asm/hardware/vic.h>
48
49#include "soc.h"
50
51/*************************************************************************
52 * Static I/O mappings that are needed for all EP93xx platforms
53 *************************************************************************/
54static struct map_desc ep93xx_io_desc[] __initdata = {
55	{
56		.virtual	= EP93XX_AHB_VIRT_BASE,
57		.pfn		= __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
58		.length		= EP93XX_AHB_SIZE,
59		.type		= MT_DEVICE,
60	}, {
61		.virtual	= EP93XX_APB_VIRT_BASE,
62		.pfn		= __phys_to_pfn(EP93XX_APB_PHYS_BASE),
63		.length		= EP93XX_APB_SIZE,
64		.type		= MT_DEVICE,
65	},
66};
67
68void __init ep93xx_map_io(void)
69{
70	iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
71}
72
73
74/*************************************************************************
75 * Timer handling for EP93xx
76 *************************************************************************
77 * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
78 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
79 * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
80 * is free-running, and can't generate interrupts.
81 *
82 * The 508 kHz timers are ideal for use for the timer interrupt, as the
83 * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
84 * bit timers (timer 1) since we don't need more than 16 bits of reload
85 * value as long as HZ >= 8.
86 *
87 * The higher clock rate of timer 4 makes it a better choice than the
88 * other timers for use in gettimeoffset(), while the fact that it can't
89 * generate interrupts means we don't have to worry about not being able
90 * to use this timer for something else.  We also use timer 4 for keeping
91 * track of lost jiffies.
92 */
93#define EP93XX_TIMER_REG(x)		(EP93XX_TIMER_BASE + (x))
94#define EP93XX_TIMER1_LOAD		EP93XX_TIMER_REG(0x00)
95#define EP93XX_TIMER1_VALUE		EP93XX_TIMER_REG(0x04)
96#define EP93XX_TIMER1_CONTROL		EP93XX_TIMER_REG(0x08)
97#define EP93XX_TIMER123_CONTROL_ENABLE	(1 << 7)
98#define EP93XX_TIMER123_CONTROL_MODE	(1 << 6)
99#define EP93XX_TIMER123_CONTROL_CLKSEL	(1 << 3)
100#define EP93XX_TIMER1_CLEAR		EP93XX_TIMER_REG(0x0c)
101#define EP93XX_TIMER2_LOAD		EP93XX_TIMER_REG(0x20)
102#define EP93XX_TIMER2_VALUE		EP93XX_TIMER_REG(0x24)
103#define EP93XX_TIMER2_CONTROL		EP93XX_TIMER_REG(0x28)
104#define EP93XX_TIMER2_CLEAR		EP93XX_TIMER_REG(0x2c)
105#define EP93XX_TIMER4_VALUE_LOW		EP93XX_TIMER_REG(0x60)
106#define EP93XX_TIMER4_VALUE_HIGH	EP93XX_TIMER_REG(0x64)
107#define EP93XX_TIMER4_VALUE_HIGH_ENABLE	(1 << 8)
108#define EP93XX_TIMER3_LOAD		EP93XX_TIMER_REG(0x80)
109#define EP93XX_TIMER3_VALUE		EP93XX_TIMER_REG(0x84)
110#define EP93XX_TIMER3_CONTROL		EP93XX_TIMER_REG(0x88)
111#define EP93XX_TIMER3_CLEAR		EP93XX_TIMER_REG(0x8c)
112
113#define EP93XX_TIMER123_CLOCK		508469
114#define EP93XX_TIMER4_CLOCK		983040
115
116#define TIMER1_RELOAD			((EP93XX_TIMER123_CLOCK / HZ) - 1)
117#define TIMER4_TICKS_PER_JIFFY		DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
118
119static unsigned int last_jiffy_time;
120
121static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
122{
123	/* Writing any value clears the timer interrupt */
124	__raw_writel(1, EP93XX_TIMER1_CLEAR);
125
126	/* Recover lost jiffies */
127	while ((signed long)
128		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
129						>= TIMER4_TICKS_PER_JIFFY) {
130		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
131		timer_tick();
132	}
133
134	return IRQ_HANDLED;
135}
136
137static struct irqaction ep93xx_timer_irq = {
138	.name		= "ep93xx timer",
139	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
140	.handler	= ep93xx_timer_interrupt,
141};
142
143static void __init ep93xx_timer_init(void)
144{
145	u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
146		    EP93XX_TIMER123_CONTROL_CLKSEL;
147
148	/* Enable periodic HZ timer.  */
149	__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
150	__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
151	__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
152			EP93XX_TIMER1_CONTROL);
153
154	/* Enable lost jiffy timer.  */
155	__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
156			EP93XX_TIMER4_VALUE_HIGH);
157
158	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
159}
160
161static unsigned long ep93xx_gettimeoffset(void)
162{
163	int offset;
164
165	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
166
167	/* Calculate (1000000 / 983040) * offset.  */
168	return offset + (53 * offset / 3072);
169}
170
171struct sys_timer ep93xx_timer = {
172	.init		= ep93xx_timer_init,
173	.offset		= ep93xx_gettimeoffset,
174};
175
176
177/*************************************************************************
178 * EP93xx IRQ handling
179 *************************************************************************/
180void __init ep93xx_init_irq(void)
181{
182	vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
183	vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
184}
185
186
187/*************************************************************************
188 * EP93xx System Controller Software Locked register handling
189 *************************************************************************/
190
191/*
192 * syscon_swlock prevents anything else from writing to the syscon
193 * block while a software locked register is being written.
194 */
195static DEFINE_SPINLOCK(syscon_swlock);
196
197void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
198{
199	unsigned long flags;
200
201	spin_lock_irqsave(&syscon_swlock, flags);
202
203	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
204	__raw_writel(val, reg);
205
206	spin_unlock_irqrestore(&syscon_swlock, flags);
207}
208
209void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
210{
211	unsigned long flags;
212	unsigned int val;
213
214	spin_lock_irqsave(&syscon_swlock, flags);
215
216	val = __raw_readl(EP93XX_SYSCON_DEVCFG);
217	val &= ~clear_bits;
218	val |= set_bits;
219	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
220	__raw_writel(val, EP93XX_SYSCON_DEVCFG);
221
222	spin_unlock_irqrestore(&syscon_swlock, flags);
223}
224
225/**
226 * ep93xx_chip_revision() - returns the EP93xx chip revision
227 *
228 * See <mach/platform.h> for more information.
229 */
230unsigned int ep93xx_chip_revision(void)
231{
232	unsigned int v;
233
234	v = __raw_readl(EP93XX_SYSCON_SYSCFG);
235	v &= EP93XX_SYSCON_SYSCFG_REV_MASK;
236	v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
237	return v;
238}
239
240/*************************************************************************
241 * EP93xx GPIO
242 *************************************************************************/
243static struct resource ep93xx_gpio_resource[] = {
244	{
245		.start		= EP93XX_GPIO_PHYS_BASE,
246		.end		= EP93XX_GPIO_PHYS_BASE + 0xcc - 1,
247		.flags		= IORESOURCE_MEM,
248	},
249};
250
251static struct platform_device ep93xx_gpio_device = {
252	.name		= "gpio-ep93xx",
253	.id		= -1,
254	.num_resources	= ARRAY_SIZE(ep93xx_gpio_resource),
255	.resource	= ep93xx_gpio_resource,
256};
257
258/*************************************************************************
259 * EP93xx peripheral handling
260 *************************************************************************/
261#define EP93XX_UART_MCR_OFFSET		(0x0100)
262
263static void ep93xx_uart_set_mctrl(struct amba_device *dev,
264				  void __iomem *base, unsigned int mctrl)
265{
266	unsigned int mcr;
267
268	mcr = 0;
269	if (mctrl & TIOCM_RTS)
270		mcr |= 2;
271	if (mctrl & TIOCM_DTR)
272		mcr |= 1;
273
274	__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
275}
276
277static struct amba_pl010_data ep93xx_uart_data = {
278	.set_mctrl	= ep93xx_uart_set_mctrl,
279};
280
281static struct amba_device uart1_device = {
282	.dev		= {
283		.init_name	= "apb:uart1",
284		.platform_data	= &ep93xx_uart_data,
285	},
286	.res		= {
287		.start	= EP93XX_UART1_PHYS_BASE,
288		.end	= EP93XX_UART1_PHYS_BASE + 0x0fff,
289		.flags	= IORESOURCE_MEM,
290	},
291	.irq		= { IRQ_EP93XX_UART1, NO_IRQ },
292	.periphid	= 0x00041010,
293};
294
295static struct amba_device uart2_device = {
296	.dev		= {
297		.init_name	= "apb:uart2",
298		.platform_data	= &ep93xx_uart_data,
299	},
300	.res		= {
301		.start	= EP93XX_UART2_PHYS_BASE,
302		.end	= EP93XX_UART2_PHYS_BASE + 0x0fff,
303		.flags	= IORESOURCE_MEM,
304	},
305	.irq		= { IRQ_EP93XX_UART2, NO_IRQ },
306	.periphid	= 0x00041010,
307};
308
309static struct amba_device uart3_device = {
310	.dev		= {
311		.init_name	= "apb:uart3",
312		.platform_data	= &ep93xx_uart_data,
313	},
314	.res		= {
315		.start	= EP93XX_UART3_PHYS_BASE,
316		.end	= EP93XX_UART3_PHYS_BASE + 0x0fff,
317		.flags	= IORESOURCE_MEM,
318	},
319	.irq		= { IRQ_EP93XX_UART3, NO_IRQ },
320	.periphid	= 0x00041010,
321};
322
323
324static struct resource ep93xx_rtc_resource[] = {
325	{
326		.start		= EP93XX_RTC_PHYS_BASE,
327		.end		= EP93XX_RTC_PHYS_BASE + 0x10c - 1,
328		.flags		= IORESOURCE_MEM,
329	},
330};
331
332static struct platform_device ep93xx_rtc_device = {
333	.name		= "ep93xx-rtc",
334	.id		= -1,
335	.num_resources	= ARRAY_SIZE(ep93xx_rtc_resource),
336	.resource	= ep93xx_rtc_resource,
337};
338
339
340static struct resource ep93xx_ohci_resources[] = {
341	[0] = {
342		.start	= EP93XX_USB_PHYS_BASE,
343		.end	= EP93XX_USB_PHYS_BASE + 0x0fff,
344		.flags	= IORESOURCE_MEM,
345	},
346	[1] = {
347		.start	= IRQ_EP93XX_USB,
348		.end	= IRQ_EP93XX_USB,
349		.flags	= IORESOURCE_IRQ,
350	},
351};
352
353
354static struct platform_device ep93xx_ohci_device = {
355	.name		= "ep93xx-ohci",
356	.id		= -1,
357	.dev		= {
358		.dma_mask		= &ep93xx_ohci_device.dev.coherent_dma_mask,
359		.coherent_dma_mask	= DMA_BIT_MASK(32),
360	},
361	.num_resources	= ARRAY_SIZE(ep93xx_ohci_resources),
362	.resource	= ep93xx_ohci_resources,
363};
364
365
366/*************************************************************************
367 * EP93xx physmap'ed flash
368 *************************************************************************/
369static struct physmap_flash_data ep93xx_flash_data;
370
371static struct resource ep93xx_flash_resource = {
372	.flags		= IORESOURCE_MEM,
373};
374
375static struct platform_device ep93xx_flash = {
376	.name		= "physmap-flash",
377	.id		= 0,
378	.dev		= {
379		.platform_data	= &ep93xx_flash_data,
380	},
381	.num_resources	= 1,
382	.resource	= &ep93xx_flash_resource,
383};
384
385/**
386 * ep93xx_register_flash() - Register the external flash device.
387 * @width:	bank width in octets
388 * @start:	resource start address
389 * @size:	resource size
390 */
391void __init ep93xx_register_flash(unsigned int width,
392				  resource_size_t start, resource_size_t size)
393{
394	ep93xx_flash_data.width		= width;
395
396	ep93xx_flash_resource.start	= start;
397	ep93xx_flash_resource.end	= start + size - 1;
398
399	platform_device_register(&ep93xx_flash);
400}
401
402
403/*************************************************************************
404 * EP93xx ethernet peripheral handling
405 *************************************************************************/
406static struct ep93xx_eth_data ep93xx_eth_data;
407
408static struct resource ep93xx_eth_resource[] = {
409	{
410		.start	= EP93XX_ETHERNET_PHYS_BASE,
411		.end	= EP93XX_ETHERNET_PHYS_BASE + 0xffff,
412		.flags	= IORESOURCE_MEM,
413	}, {
414		.start	= IRQ_EP93XX_ETHERNET,
415		.end	= IRQ_EP93XX_ETHERNET,
416		.flags	= IORESOURCE_IRQ,
417	}
418};
419
420static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
421
422static struct platform_device ep93xx_eth_device = {
423	.name		= "ep93xx-eth",
424	.id		= -1,
425	.dev		= {
426		.platform_data		= &ep93xx_eth_data,
427		.coherent_dma_mask	= DMA_BIT_MASK(32),
428		.dma_mask		= &ep93xx_eth_dma_mask,
429	},
430	.num_resources	= ARRAY_SIZE(ep93xx_eth_resource),
431	.resource	= ep93xx_eth_resource,
432};
433
434/**
435 * ep93xx_register_eth - Register the built-in ethernet platform device.
436 * @data:	platform specific ethernet configuration (__initdata)
437 * @copy_addr:	flag indicating that the MAC address should be copied
438 *		from the IndAd registers (as programmed by the bootloader)
439 */
440void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
441{
442	if (copy_addr)
443		memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
444
445	ep93xx_eth_data = *data;
446	platform_device_register(&ep93xx_eth_device);
447}
448
449
450/*************************************************************************
451 * EP93xx i2c peripheral handling
452 *************************************************************************/
453static struct i2c_gpio_platform_data ep93xx_i2c_data;
454
455static struct platform_device ep93xx_i2c_device = {
456	.name		= "i2c-gpio",
457	.id		= 0,
458	.dev		= {
459		.platform_data	= &ep93xx_i2c_data,
460	},
461};
462
463/**
464 * ep93xx_register_i2c - Register the i2c platform device.
465 * @data:	platform specific i2c-gpio configuration (__initdata)
466 * @devices:	platform specific i2c bus device information (__initdata)
467 * @num:	the number of devices on the i2c bus
468 */
469void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
470				struct i2c_board_info *devices, int num)
471{
472	/*
473	 * Set the EEPROM interface pin drive type control.
474	 * Defines the driver type for the EECLK and EEDAT pins as either
475	 * open drain, which will require an external pull-up, or a normal
476	 * CMOS driver.
477	 */
478	if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
479		pr_warning("sda != EEDAT, open drain has no effect\n");
480	if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
481		pr_warning("scl != EECLK, open drain has no effect\n");
482
483	__raw_writel((data->sda_is_open_drain << 1) |
484		     (data->scl_is_open_drain << 0),
485		     EP93XX_GPIO_EEDRIVE);
486
487	ep93xx_i2c_data = *data;
488	i2c_register_board_info(0, devices, num);
489	platform_device_register(&ep93xx_i2c_device);
490}
491
492/*************************************************************************
493 * EP93xx SPI peripheral handling
494 *************************************************************************/
495static struct ep93xx_spi_info ep93xx_spi_master_data;
496
497static struct resource ep93xx_spi_resources[] = {
498	{
499		.start	= EP93XX_SPI_PHYS_BASE,
500		.end	= EP93XX_SPI_PHYS_BASE + 0x18 - 1,
501		.flags	= IORESOURCE_MEM,
502	},
503	{
504		.start	= IRQ_EP93XX_SSP,
505		.end	= IRQ_EP93XX_SSP,
506		.flags	= IORESOURCE_IRQ,
507	},
508};
509
510static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
511
512static struct platform_device ep93xx_spi_device = {
513	.name		= "ep93xx-spi",
514	.id		= 0,
515	.dev		= {
516		.platform_data		= &ep93xx_spi_master_data,
517		.coherent_dma_mask	= DMA_BIT_MASK(32),
518		.dma_mask		= &ep93xx_spi_dma_mask,
519	},
520	.num_resources	= ARRAY_SIZE(ep93xx_spi_resources),
521	.resource	= ep93xx_spi_resources,
522};
523
524/**
525 * ep93xx_register_spi() - registers spi platform device
526 * @info: ep93xx board specific spi master info (__initdata)
527 * @devices: SPI devices to register (__initdata)
528 * @num: number of SPI devices to register
529 *
530 * This function registers platform device for the EP93xx SPI controller and
531 * also makes sure that SPI pins are muxed so that I2S is not using those pins.
532 */
533void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
534				struct spi_board_info *devices, int num)
535{
536	/*
537	 * When SPI is used, we need to make sure that I2S is muxed off from
538	 * SPI pins.
539	 */
540	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP);
541
542	ep93xx_spi_master_data = *info;
543	spi_register_board_info(devices, num);
544	platform_device_register(&ep93xx_spi_device);
545}
546
547/*************************************************************************
548 * EP93xx LEDs
549 *************************************************************************/
550static struct gpio_led ep93xx_led_pins[] = {
551	{
552		.name	= "platform:grled",
553		.gpio	= EP93XX_GPIO_LINE_GRLED,
554	}, {
555		.name	= "platform:rdled",
556		.gpio	= EP93XX_GPIO_LINE_RDLED,
557	},
558};
559
560static struct gpio_led_platform_data ep93xx_led_data = {
561	.num_leds	= ARRAY_SIZE(ep93xx_led_pins),
562	.leds		= ep93xx_led_pins,
563};
564
565static struct platform_device ep93xx_leds = {
566	.name		= "leds-gpio",
567	.id		= -1,
568	.dev		= {
569		.platform_data	= &ep93xx_led_data,
570	},
571};
572
573
574/*************************************************************************
575 * EP93xx pwm peripheral handling
576 *************************************************************************/
577static struct resource ep93xx_pwm0_resource[] = {
578	{
579		.start	= EP93XX_PWM_PHYS_BASE,
580		.end	= EP93XX_PWM_PHYS_BASE + 0x10 - 1,
581		.flags	= IORESOURCE_MEM,
582	},
583};
584
585static struct platform_device ep93xx_pwm0_device = {
586	.name		= "ep93xx-pwm",
587	.id		= 0,
588	.num_resources	= ARRAY_SIZE(ep93xx_pwm0_resource),
589	.resource	= ep93xx_pwm0_resource,
590};
591
592static struct resource ep93xx_pwm1_resource[] = {
593	{
594		.start	= EP93XX_PWM_PHYS_BASE + 0x20,
595		.end	= EP93XX_PWM_PHYS_BASE + 0x30 - 1,
596		.flags	= IORESOURCE_MEM,
597	},
598};
599
600static struct platform_device ep93xx_pwm1_device = {
601	.name		= "ep93xx-pwm",
602	.id		= 1,
603	.num_resources	= ARRAY_SIZE(ep93xx_pwm1_resource),
604	.resource	= ep93xx_pwm1_resource,
605};
606
607void __init ep93xx_register_pwm(int pwm0, int pwm1)
608{
609	if (pwm0)
610		platform_device_register(&ep93xx_pwm0_device);
611
612	/* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
613	if (pwm1)
614		platform_device_register(&ep93xx_pwm1_device);
615}
616
617int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
618{
619	int err;
620
621	if (pdev->id == 0) {
622		err = 0;
623	} else if (pdev->id == 1) {
624		err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
625				   dev_name(&pdev->dev));
626		if (err)
627			return err;
628		err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
629		if (err)
630			goto fail;
631
632		/* PWM 1 output on EGPIO[14] */
633		ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
634	} else {
635		err = -ENODEV;
636	}
637
638	return err;
639
640fail:
641	gpio_free(EP93XX_GPIO_LINE_EGPIO14);
642	return err;
643}
644EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
645
646void ep93xx_pwm_release_gpio(struct platform_device *pdev)
647{
648	if (pdev->id == 1) {
649		gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
650		gpio_free(EP93XX_GPIO_LINE_EGPIO14);
651
652		/* EGPIO[14] used for GPIO */
653		ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
654	}
655}
656EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
657
658
659/*************************************************************************
660 * EP93xx video peripheral handling
661 *************************************************************************/
662static struct ep93xxfb_mach_info ep93xxfb_data;
663
664static struct resource ep93xx_fb_resource[] = {
665	{
666		.start		= EP93XX_RASTER_PHYS_BASE,
667		.end		= EP93XX_RASTER_PHYS_BASE + 0x800 - 1,
668		.flags		= IORESOURCE_MEM,
669	},
670};
671
672static struct platform_device ep93xx_fb_device = {
673	.name			= "ep93xx-fb",
674	.id			= -1,
675	.dev			= {
676		.platform_data		= &ep93xxfb_data,
677		.coherent_dma_mask	= DMA_BIT_MASK(32),
678		.dma_mask		= &ep93xx_fb_device.dev.coherent_dma_mask,
679	},
680	.num_resources		= ARRAY_SIZE(ep93xx_fb_resource),
681	.resource		= ep93xx_fb_resource,
682};
683
684/* The backlight use a single register in the framebuffer's register space */
685#define EP93XX_RASTER_REG_BRIGHTNESS 0x20
686
687static struct resource ep93xx_bl_resources[] = {
688	DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
689		       EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
690};
691
692static struct platform_device ep93xx_bl_device = {
693	.name		= "ep93xx-bl",
694	.id		= -1,
695	.num_resources	= ARRAY_SIZE(ep93xx_bl_resources),
696	.resource	= ep93xx_bl_resources,
697};
698
699/**
700 * ep93xx_register_fb - Register the framebuffer platform device.
701 * @data:	platform specific framebuffer configuration (__initdata)
702 */
703void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
704{
705	ep93xxfb_data = *data;
706	platform_device_register(&ep93xx_fb_device);
707	platform_device_register(&ep93xx_bl_device);
708}
709
710
711/*************************************************************************
712 * EP93xx matrix keypad peripheral handling
713 *************************************************************************/
714static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
715
716static struct resource ep93xx_keypad_resource[] = {
717	{
718		.start	= EP93XX_KEY_MATRIX_PHYS_BASE,
719		.end	= EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1,
720		.flags	= IORESOURCE_MEM,
721	}, {
722		.start	= IRQ_EP93XX_KEY,
723		.end	= IRQ_EP93XX_KEY,
724		.flags	= IORESOURCE_IRQ,
725	},
726};
727
728static struct platform_device ep93xx_keypad_device = {
729	.name		= "ep93xx-keypad",
730	.id		= -1,
731	.dev		= {
732		.platform_data	= &ep93xx_keypad_data,
733	},
734	.num_resources	= ARRAY_SIZE(ep93xx_keypad_resource),
735	.resource	= ep93xx_keypad_resource,
736};
737
738/**
739 * ep93xx_register_keypad - Register the keypad platform device.
740 * @data:	platform specific keypad configuration (__initdata)
741 */
742void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
743{
744	ep93xx_keypad_data = *data;
745	platform_device_register(&ep93xx_keypad_device);
746}
747
748int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
749{
750	int err;
751	int i;
752
753	for (i = 0; i < 8; i++) {
754		err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
755		if (err)
756			goto fail_gpio_c;
757		err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
758		if (err)
759			goto fail_gpio_d;
760	}
761
762	/* Enable the keypad controller; GPIO ports C and D used for keypad */
763	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
764				 EP93XX_SYSCON_DEVCFG_GONK);
765
766	return 0;
767
768fail_gpio_d:
769	gpio_free(EP93XX_GPIO_LINE_C(i));
770fail_gpio_c:
771	for ( ; i >= 0; --i) {
772		gpio_free(EP93XX_GPIO_LINE_C(i));
773		gpio_free(EP93XX_GPIO_LINE_D(i));
774	}
775	return err;
776}
777EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
778
779void ep93xx_keypad_release_gpio(struct platform_device *pdev)
780{
781	int i;
782
783	for (i = 0; i < 8; i++) {
784		gpio_free(EP93XX_GPIO_LINE_C(i));
785		gpio_free(EP93XX_GPIO_LINE_D(i));
786	}
787
788	/* Disable the keypad controller; GPIO ports C and D used for GPIO */
789	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
790			       EP93XX_SYSCON_DEVCFG_GONK);
791}
792EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
793
794/*************************************************************************
795 * EP93xx I2S audio peripheral handling
796 *************************************************************************/
797static struct resource ep93xx_i2s_resource[] = {
798	{
799		.start	= EP93XX_I2S_PHYS_BASE,
800		.end	= EP93XX_I2S_PHYS_BASE + 0x100 - 1,
801		.flags	= IORESOURCE_MEM,
802	},
803};
804
805static struct platform_device ep93xx_i2s_device = {
806	.name		= "ep93xx-i2s",
807	.id		= -1,
808	.num_resources	= ARRAY_SIZE(ep93xx_i2s_resource),
809	.resource	= ep93xx_i2s_resource,
810};
811
812static struct platform_device ep93xx_pcm_device = {
813	.name		= "ep93xx-pcm-audio",
814	.id		= -1,
815};
816
817void __init ep93xx_register_i2s(void)
818{
819	platform_device_register(&ep93xx_i2s_device);
820	platform_device_register(&ep93xx_pcm_device);
821}
822
823#define EP93XX_SYSCON_DEVCFG_I2S_MASK	(EP93XX_SYSCON_DEVCFG_I2SONSSP | \
824					 EP93XX_SYSCON_DEVCFG_I2SONAC97)
825
826#define EP93XX_I2SCLKDIV_MASK		(EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
827					 EP93XX_SYSCON_I2SCLKDIV_SPOL)
828
829int ep93xx_i2s_acquire(void)
830{
831	unsigned val;
832
833	ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
834			EP93XX_SYSCON_DEVCFG_I2S_MASK);
835
836	/*
837	 * This is potentially racy with the clock api for i2s_mclk, sclk and
838	 * lrclk. Since the i2s driver is the only user of those clocks we
839	 * rely on it to prevent parallel use of this function and the
840	 * clock api for the i2s clocks.
841	 */
842	val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
843	val &= ~EP93XX_I2SCLKDIV_MASK;
844	val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
845	ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
846
847	return 0;
848}
849EXPORT_SYMBOL(ep93xx_i2s_acquire);
850
851void ep93xx_i2s_release(void)
852{
853	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
854}
855EXPORT_SYMBOL(ep93xx_i2s_release);
856
857/*************************************************************************
858 * EP93xx AC97 audio peripheral handling
859 *************************************************************************/
860static struct resource ep93xx_ac97_resources[] = {
861	{
862		.start	= EP93XX_AAC_PHYS_BASE,
863		.end	= EP93XX_AAC_PHYS_BASE + 0xac - 1,
864		.flags	= IORESOURCE_MEM,
865	},
866	{
867		.start	= IRQ_EP93XX_AACINTR,
868		.end	= IRQ_EP93XX_AACINTR,
869		.flags	= IORESOURCE_IRQ,
870	},
871};
872
873static struct platform_device ep93xx_ac97_device = {
874	.name		= "ep93xx-ac97",
875	.id		= -1,
876	.num_resources	= ARRAY_SIZE(ep93xx_ac97_resources),
877	.resource	= ep93xx_ac97_resources,
878};
879
880void __init ep93xx_register_ac97(void)
881{
882	/*
883	 * Make sure that the AC97 pins are not used by I2S.
884	 */
885	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
886
887	platform_device_register(&ep93xx_ac97_device);
888	platform_device_register(&ep93xx_pcm_device);
889}
890
891/*************************************************************************
892 * EP93xx Watchdog
893 *************************************************************************/
894static struct resource ep93xx_wdt_resources[] = {
895	DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
896};
897
898static struct platform_device ep93xx_wdt_device = {
899	.name		= "ep93xx-wdt",
900	.id		= -1,
901	.num_resources	= ARRAY_SIZE(ep93xx_wdt_resources),
902	.resource	= ep93xx_wdt_resources,
903};
904
905void __init ep93xx_init_devices(void)
906{
907	/* Disallow access to MaverickCrunch initially */
908	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
909
910	/* Default all ports to GPIO */
911	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
912			       EP93XX_SYSCON_DEVCFG_GONK |
913			       EP93XX_SYSCON_DEVCFG_EONIDE |
914			       EP93XX_SYSCON_DEVCFG_GONIDE |
915			       EP93XX_SYSCON_DEVCFG_HONIDE);
916
917	/* Get the GPIO working early, other devices need it */
918	platform_device_register(&ep93xx_gpio_device);
919
920	amba_device_register(&uart1_device, &iomem_resource);
921	amba_device_register(&uart2_device, &iomem_resource);
922	amba_device_register(&uart3_device, &iomem_resource);
923
924	platform_device_register(&ep93xx_rtc_device);
925	platform_device_register(&ep93xx_ohci_device);
926	platform_device_register(&ep93xx_leds);
927	platform_device_register(&ep93xx_wdt_device);
928}
929
930void ep93xx_restart(char mode, const char *cmd)
931{
932	/*
933	 * Set then clear the SWRST bit to initiate a software reset
934	 */
935	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
936	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
937
938	while (1)
939		;
940}
941