core.c revision d52a26a956d3925c6eaf8770e95e4d5f13740696 
1/*
2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
7 *
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/bitops.h>
25#include <linux/serial_8250.h>
26#include <linux/serial_core.h>
27#include <linux/device.h>
28#include <linux/mm.h>
29#include <linux/dma-mapping.h>
30#include <linux/time.h>
31#include <linux/timex.h>
32#include <linux/delay.h>
33#include <linux/termios.h>
34#include <linux/amba/bus.h>
35#include <linux/amba/serial.h>
36#include <linux/io.h>
37#include <linux/i2c.h>
38#include <linux/i2c-gpio.h>
39
40#include <asm/types.h>
41#include <asm/setup.h>
42#include <asm/memory.h>
43#include <mach/hardware.h>
44#include <asm/irq.h>
45#include <asm/system.h>
46#include <asm/tlbflush.h>
47#include <asm/pgtable.h>
48
49#include <asm/mach/map.h>
50#include <asm/mach/time.h>
51#include <asm/mach/irq.h>
52#include <mach/gpio.h>
53
54#include <asm/hardware/vic.h>
55
56
57/*************************************************************************
58 * Static I/O mappings that are needed for all EP93xx platforms
59 *************************************************************************/
60static struct map_desc ep93xx_io_desc[] __initdata = {
61	{
62		.virtual	= EP93XX_AHB_VIRT_BASE,
63		.pfn		= __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
64		.length		= EP93XX_AHB_SIZE,
65		.type		= MT_DEVICE,
66	}, {
67		.virtual	= EP93XX_APB_VIRT_BASE,
68		.pfn		= __phys_to_pfn(EP93XX_APB_PHYS_BASE),
69		.length		= EP93XX_APB_SIZE,
70		.type		= MT_DEVICE,
71	},
72};
73
74void __init ep93xx_map_io(void)
75{
76	iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
77}
78
79
80/*************************************************************************
81 * Timer handling for EP93xx
82 *************************************************************************
83 * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
84 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
85 * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
86 * is free-running, and can't generate interrupts.
87 *
88 * The 508 kHz timers are ideal for use for the timer interrupt, as the
89 * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
90 * bit timers (timer 1) since we don't need more than 16 bits of reload
91 * value as long as HZ >= 8.
92 *
93 * The higher clock rate of timer 4 makes it a better choice than the
94 * other timers for use in gettimeoffset(), while the fact that it can't
95 * generate interrupts means we don't have to worry about not being able
96 * to use this timer for something else.  We also use timer 4 for keeping
97 * track of lost jiffies.
98 */
99static unsigned int last_jiffy_time;
100
101#define TIMER4_TICKS_PER_JIFFY		((CLOCK_TICK_RATE + (HZ/2)) / HZ)
102
103static int ep93xx_timer_interrupt(int irq, void *dev_id)
104{
105	__raw_writel(1, EP93XX_TIMER1_CLEAR);
106	while ((signed long)
107		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
108						>= TIMER4_TICKS_PER_JIFFY) {
109		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
110		timer_tick();
111	}
112
113	return IRQ_HANDLED;
114}
115
116static struct irqaction ep93xx_timer_irq = {
117	.name		= "ep93xx timer",
118	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
119	.handler	= ep93xx_timer_interrupt,
120};
121
122static void __init ep93xx_timer_init(void)
123{
124	/* Enable periodic HZ timer.  */
125	__raw_writel(0x48, EP93XX_TIMER1_CONTROL);
126	__raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
127	__raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
128
129	/* Enable lost jiffy timer.  */
130	__raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
131
132	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
133}
134
135static unsigned long ep93xx_gettimeoffset(void)
136{
137	int offset;
138
139	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
140
141	/* Calculate (1000000 / 983040) * offset.  */
142	return offset + (53 * offset / 3072);
143}
144
145struct sys_timer ep93xx_timer = {
146	.init		= ep93xx_timer_init,
147	.offset		= ep93xx_gettimeoffset,
148};
149
150
151/*************************************************************************
152 * GPIO handling for EP93xx
153 *************************************************************************/
154static unsigned char gpio_int_unmasked[3];
155static unsigned char gpio_int_enabled[3];
156static unsigned char gpio_int_type1[3];
157static unsigned char gpio_int_type2[3];
158
159/* Port ordering is: A B F */
160static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
161static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
162static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
163static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
164
165void ep93xx_gpio_update_int_params(unsigned port)
166{
167	BUG_ON(port > 2);
168
169	__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
170
171	__raw_writeb(gpio_int_type2[port],
172		EP93XX_GPIO_REG(int_type2_register_offset[port]));
173
174	__raw_writeb(gpio_int_type1[port],
175		EP93XX_GPIO_REG(int_type1_register_offset[port]));
176
177	__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
178		EP93XX_GPIO_REG(int_en_register_offset[port]));
179}
180
181void ep93xx_gpio_int_mask(unsigned line)
182{
183	gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
184}
185
186/*************************************************************************
187 * EP93xx IRQ handling
188 *************************************************************************/
189static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
190{
191	unsigned char status;
192	int i;
193
194	status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
195	for (i = 0; i < 8; i++) {
196		if (status & (1 << i)) {
197			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
198			generic_handle_irq(gpio_irq);
199		}
200	}
201
202	status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
203	for (i = 0; i < 8; i++) {
204		if (status & (1 << i)) {
205			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
206			desc = irq_desc + gpio_irq;
207			generic_handle_irq(gpio_irq);
208		}
209	}
210}
211
212static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
213{
214	/*
215	 * map discontiguous hw irq range to continous sw irq range:
216	 *
217	 *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
218	 */
219	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
220	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
221
222	generic_handle_irq(gpio_irq);
223}
224
225static void ep93xx_gpio_irq_ack(unsigned int irq)
226{
227	int line = irq_to_gpio(irq);
228	int port = line >> 3;
229	int port_mask = 1 << (line & 7);
230
231	if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
232		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
233		ep93xx_gpio_update_int_params(port);
234	}
235
236	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
237}
238
239static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
240{
241	int line = irq_to_gpio(irq);
242	int port = line >> 3;
243	int port_mask = 1 << (line & 7);
244
245	if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
246		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
247
248	gpio_int_unmasked[port] &= ~port_mask;
249	ep93xx_gpio_update_int_params(port);
250
251	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
252}
253
254static void ep93xx_gpio_irq_mask(unsigned int irq)
255{
256	int line = irq_to_gpio(irq);
257	int port = line >> 3;
258
259	gpio_int_unmasked[port] &= ~(1 << (line & 7));
260	ep93xx_gpio_update_int_params(port);
261}
262
263static void ep93xx_gpio_irq_unmask(unsigned int irq)
264{
265	int line = irq_to_gpio(irq);
266	int port = line >> 3;
267
268	gpio_int_unmasked[port] |= 1 << (line & 7);
269	ep93xx_gpio_update_int_params(port);
270}
271
272
273/*
274 * gpio_int_type1 controls whether the interrupt is level (0) or
275 * edge (1) triggered, while gpio_int_type2 controls whether it
276 * triggers on low/falling (0) or high/rising (1).
277 */
278static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
279{
280	struct irq_desc *desc = irq_desc + irq;
281	const int gpio = irq_to_gpio(irq);
282	const int port = gpio >> 3;
283	const int port_mask = 1 << (gpio & 7);
284
285	gpio_direction_input(gpio);
286
287	switch (type) {
288	case IRQ_TYPE_EDGE_RISING:
289		gpio_int_type1[port] |= port_mask;
290		gpio_int_type2[port] |= port_mask;
291		desc->handle_irq = handle_edge_irq;
292		break;
293	case IRQ_TYPE_EDGE_FALLING:
294		gpio_int_type1[port] |= port_mask;
295		gpio_int_type2[port] &= ~port_mask;
296		desc->handle_irq = handle_edge_irq;
297		break;
298	case IRQ_TYPE_LEVEL_HIGH:
299		gpio_int_type1[port] &= ~port_mask;
300		gpio_int_type2[port] |= port_mask;
301		desc->handle_irq = handle_level_irq;
302		break;
303	case IRQ_TYPE_LEVEL_LOW:
304		gpio_int_type1[port] &= ~port_mask;
305		gpio_int_type2[port] &= ~port_mask;
306		desc->handle_irq = handle_level_irq;
307		break;
308	case IRQ_TYPE_EDGE_BOTH:
309		gpio_int_type1[port] |= port_mask;
310		/* set initial polarity based on current input level */
311		if (gpio_get_value(gpio))
312			gpio_int_type2[port] &= ~port_mask; /* falling */
313		else
314			gpio_int_type2[port] |= port_mask; /* rising */
315		desc->handle_irq = handle_edge_irq;
316		break;
317	default:
318		pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
319		       type, gpio);
320		return -EINVAL;
321	}
322
323	gpio_int_enabled[port] |= port_mask;
324
325	desc->status &= ~IRQ_TYPE_SENSE_MASK;
326	desc->status |= type & IRQ_TYPE_SENSE_MASK;
327
328	ep93xx_gpio_update_int_params(port);
329
330	return 0;
331}
332
333static struct irq_chip ep93xx_gpio_irq_chip = {
334	.name		= "GPIO",
335	.ack		= ep93xx_gpio_irq_ack,
336	.mask_ack	= ep93xx_gpio_irq_mask_ack,
337	.mask		= ep93xx_gpio_irq_mask,
338	.unmask		= ep93xx_gpio_irq_unmask,
339	.set_type	= ep93xx_gpio_irq_type,
340};
341
342
343void __init ep93xx_init_irq(void)
344{
345	int gpio_irq;
346
347	vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
348	vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
349
350	for (gpio_irq = gpio_to_irq(0);
351	     gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
352		set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
353		set_irq_handler(gpio_irq, handle_level_irq);
354		set_irq_flags(gpio_irq, IRQF_VALID);
355	}
356
357	set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
358	set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
359	set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
360	set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
361	set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
362	set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
363	set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
364	set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
365	set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
366}
367
368
369/*************************************************************************
370 * EP93xx peripheral handling
371 *************************************************************************/
372#define EP93XX_UART_MCR_OFFSET		(0x0100)
373
374static void ep93xx_uart_set_mctrl(struct amba_device *dev,
375				  void __iomem *base, unsigned int mctrl)
376{
377	unsigned int mcr;
378
379	mcr = 0;
380	if (!(mctrl & TIOCM_RTS))
381		mcr |= 2;
382	if (!(mctrl & TIOCM_DTR))
383		mcr |= 1;
384
385	__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
386}
387
388static struct amba_pl010_data ep93xx_uart_data = {
389	.set_mctrl	= ep93xx_uart_set_mctrl,
390};
391
392static struct amba_device uart1_device = {
393	.dev		= {
394		.bus_id		= "apb:uart1",
395		.platform_data	= &ep93xx_uart_data,
396	},
397	.res		= {
398		.start	= EP93XX_UART1_PHYS_BASE,
399		.end	= EP93XX_UART1_PHYS_BASE + 0x0fff,
400		.flags	= IORESOURCE_MEM,
401	},
402	.irq		= { IRQ_EP93XX_UART1, NO_IRQ },
403	.periphid	= 0x00041010,
404};
405
406static struct amba_device uart2_device = {
407	.dev		= {
408		.bus_id		= "apb:uart2",
409		.platform_data	= &ep93xx_uart_data,
410	},
411	.res		= {
412		.start	= EP93XX_UART2_PHYS_BASE,
413		.end	= EP93XX_UART2_PHYS_BASE + 0x0fff,
414		.flags	= IORESOURCE_MEM,
415	},
416	.irq		= { IRQ_EP93XX_UART2, NO_IRQ },
417	.periphid	= 0x00041010,
418};
419
420static struct amba_device uart3_device = {
421	.dev		= {
422		.bus_id		= "apb:uart3",
423		.platform_data	= &ep93xx_uart_data,
424	},
425	.res		= {
426		.start	= EP93XX_UART3_PHYS_BASE,
427		.end	= EP93XX_UART3_PHYS_BASE + 0x0fff,
428		.flags	= IORESOURCE_MEM,
429	},
430	.irq		= { IRQ_EP93XX_UART3, NO_IRQ },
431	.periphid	= 0x00041010,
432};
433
434
435static struct platform_device ep93xx_rtc_device = {
436       .name           = "ep93xx-rtc",
437       .id             = -1,
438       .num_resources  = 0,
439};
440
441
442static struct resource ep93xx_ohci_resources[] = {
443	[0] = {
444		.start	= EP93XX_USB_PHYS_BASE,
445		.end	= EP93XX_USB_PHYS_BASE + 0x0fff,
446		.flags	= IORESOURCE_MEM,
447	},
448	[1] = {
449		.start	= IRQ_EP93XX_USB,
450		.end	= IRQ_EP93XX_USB,
451		.flags	= IORESOURCE_IRQ,
452	},
453};
454
455
456static struct platform_device ep93xx_ohci_device = {
457	.name		= "ep93xx-ohci",
458	.id		= -1,
459	.dev		= {
460		.dma_mask		= &ep93xx_ohci_device.dev.coherent_dma_mask,
461		.coherent_dma_mask	= DMA_BIT_MASK(32),
462	},
463	.num_resources	= ARRAY_SIZE(ep93xx_ohci_resources),
464	.resource	= ep93xx_ohci_resources,
465};
466
467static struct ep93xx_eth_data ep93xx_eth_data;
468
469static struct resource ep93xx_eth_resource[] = {
470	{
471		.start	= EP93XX_ETHERNET_PHYS_BASE,
472		.end	= EP93XX_ETHERNET_PHYS_BASE + 0xffff,
473		.flags	= IORESOURCE_MEM,
474	}, {
475		.start	= IRQ_EP93XX_ETHERNET,
476		.end	= IRQ_EP93XX_ETHERNET,
477		.flags	= IORESOURCE_IRQ,
478	}
479};
480
481static struct platform_device ep93xx_eth_device = {
482	.name		= "ep93xx-eth",
483	.id		= -1,
484	.dev		= {
485		.platform_data	= &ep93xx_eth_data,
486	},
487	.num_resources	= ARRAY_SIZE(ep93xx_eth_resource),
488	.resource	= ep93xx_eth_resource,
489};
490
491void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
492{
493	if (copy_addr) {
494		memcpy(data->dev_addr,
495			(void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
496	}
497
498	ep93xx_eth_data = *data;
499	platform_device_register(&ep93xx_eth_device);
500}
501
502static struct i2c_gpio_platform_data ep93xx_i2c_data = {
503	.sda_pin		= EP93XX_GPIO_LINE_EEDAT,
504	.sda_is_open_drain	= 0,
505	.scl_pin		= EP93XX_GPIO_LINE_EECLK,
506	.scl_is_open_drain	= 0,
507	.udelay			= 2,
508};
509
510static struct platform_device ep93xx_i2c_device = {
511	.name			= "i2c-gpio",
512	.id			= 0,
513	.dev.platform_data	= &ep93xx_i2c_data,
514};
515
516void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
517{
518	i2c_register_board_info(0, devices, num);
519	platform_device_register(&ep93xx_i2c_device);
520}
521
522extern void ep93xx_gpio_init(void);
523
524void __init ep93xx_init_devices(void)
525{
526	unsigned int v;
527
528	/*
529	 * Disallow access to MaverickCrunch initially.
530	 */
531	v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
532	v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
533	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
534	__raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
535
536	ep93xx_gpio_init();
537
538	amba_device_register(&uart1_device, &iomem_resource);
539	amba_device_register(&uart2_device, &iomem_resource);
540	amba_device_register(&uart3_device, &iomem_resource);
541
542	platform_device_register(&ep93xx_rtc_device);
543	platform_device_register(&ep93xx_ohci_device);
544}
545