1/*
2 *  Copyright (C) 2000 Deep Blue Solutions Ltd
3 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/serial_8250.h>
21#include <linux/gpio.h>
22#include <linux/i2c.h>
23#include <linux/irq.h>
24#include <linux/irqdomain.h>
25
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/time.h>
29#include <asm/memory.h>
30#include <asm/mach/map.h>
31
32#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
33#include <linux/mfd/wm8350/audio.h>
34#include <linux/mfd/wm8350/core.h>
35#include <linux/mfd/wm8350/pmic.h>
36#endif
37
38#include "common.h"
39#include "devices-imx31.h"
40#include "hardware.h"
41#include "iomux-mx3.h"
42
43/* Base address of PBC controller */
44#define PBC_BASE_ADDRESS	MX31_CS4_BASE_ADDR_VIRT
45
46/* PBC Board interrupt status register */
47#define PBC_INTSTATUS           0x000016
48
49/* PBC Board interrupt current status register */
50#define PBC_INTCURR_STATUS      0x000018
51
52/* PBC Interrupt mask register set address */
53#define PBC_INTMASK_SET         0x00001A
54
55/* PBC Interrupt mask register clear address */
56#define PBC_INTMASK_CLEAR       0x00001C
57
58/* External UART A */
59#define PBC_SC16C652_UARTA      0x010000
60
61/* External UART B */
62#define PBC_SC16C652_UARTB      0x010010
63
64#define PBC_INTSTATUS_REG	(PBC_INTSTATUS + PBC_BASE_ADDRESS)
65#define PBC_INTMASK_SET_REG	(PBC_INTMASK_SET + PBC_BASE_ADDRESS)
66#define PBC_INTMASK_CLEAR_REG	(PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
67
68#define EXPIO_INT_XUART_INTA	10
69#define EXPIO_INT_XUART_INTB	11
70
71#define MXC_MAX_EXP_IO_LINES	16
72
73/* CS8900 */
74#define EXPIO_INT_ENET_INT	8
75#define CS4_CS8900_MMIO_START	0x20000
76
77static struct irq_domain *domain;
78
79/*
80 * The serial port definition structure.
81 */
82static struct plat_serial8250_port serial_platform_data[] = {
83	{
84		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
85		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
86		.uartclk  = 14745600,
87		.regshift = 0,
88		.iotype   = UPIO_MEM,
89		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
90	}, {
91		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
92		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
93		.uartclk  = 14745600,
94		.regshift = 0,
95		.iotype   = UPIO_MEM,
96		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
97	},
98	{},
99};
100
101static struct platform_device serial_device = {
102	.name	= "serial8250",
103	.id	= 0,
104	.dev	= {
105		.platform_data = serial_platform_data,
106	},
107};
108
109static struct resource mx31ads_cs8900_resources[] __initdata = {
110	DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
111	DEFINE_RES_IRQ(-1),
112};
113
114static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
115	.name = "cs89x0",
116	.id = 0,
117	.res = mx31ads_cs8900_resources,
118	.num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
119};
120
121static int __init mxc_init_extuart(void)
122{
123	serial_platform_data[0].irq = irq_find_mapping(domain,
124						       EXPIO_INT_XUART_INTA);
125	serial_platform_data[1].irq = irq_find_mapping(domain,
126						       EXPIO_INT_XUART_INTB);
127	return platform_device_register(&serial_device);
128}
129
130static void __init mxc_init_ext_ethernet(void)
131{
132	mx31ads_cs8900_resources[1].start =
133			irq_find_mapping(domain, EXPIO_INT_ENET_INT);
134	mx31ads_cs8900_resources[1].end =
135			irq_find_mapping(domain, EXPIO_INT_ENET_INT);
136	platform_device_register_full(
137		(struct platform_device_info *)&mx31ads_cs8900_devinfo);
138}
139
140static const struct imxuart_platform_data uart_pdata __initconst = {
141	.flags = IMXUART_HAVE_RTSCTS,
142};
143
144static unsigned int uart_pins[] = {
145	MX31_PIN_CTS1__CTS1,
146	MX31_PIN_RTS1__RTS1,
147	MX31_PIN_TXD1__TXD1,
148	MX31_PIN_RXD1__RXD1
149};
150
151static inline void mxc_init_imx_uart(void)
152{
153	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
154	imx31_add_imx_uart0(&uart_pdata);
155}
156
157static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
158{
159	u32 imr_val;
160	u32 int_valid;
161	u32 expio_irq;
162
163	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
164	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
165
166	expio_irq = 0;
167	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
168		if ((int_valid & 1) == 0)
169			continue;
170
171		generic_handle_irq(irq_find_mapping(domain, expio_irq));
172	}
173}
174
175/*
176 * Disable an expio pin's interrupt by setting the bit in the imr.
177 * @param d	an expio virtual irq description
178 */
179static void expio_mask_irq(struct irq_data *d)
180{
181	u32 expio = d->hwirq;
182	/* mask the interrupt */
183	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
184	__raw_readw(PBC_INTMASK_CLEAR_REG);
185}
186
187/*
188 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
189 * @param d	an expio virtual irq description
190 */
191static void expio_ack_irq(struct irq_data *d)
192{
193	u32 expio = d->hwirq;
194	/* clear the interrupt status */
195	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
196}
197
198/*
199 * Enable a expio pin's interrupt by clearing the bit in the imr.
200 * @param d	an expio virtual irq description
201 */
202static void expio_unmask_irq(struct irq_data *d)
203{
204	u32 expio = d->hwirq;
205	/* unmask the interrupt */
206	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
207}
208
209static struct irq_chip expio_irq_chip = {
210	.name = "EXPIO(CPLD)",
211	.irq_ack = expio_ack_irq,
212	.irq_mask = expio_mask_irq,
213	.irq_unmask = expio_unmask_irq,
214};
215
216static void __init mx31ads_init_expio(void)
217{
218	int irq_base;
219	int i, irq;
220
221	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
222
223	/*
224	 * Configure INT line as GPIO input
225	 */
226	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
227
228	/* disable the interrupt and clear the status */
229	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
230	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
231
232	irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
233	WARN_ON(irq_base < 0);
234
235	domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
236				       &irq_domain_simple_ops, NULL);
237	WARN_ON(!domain);
238
239	for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
240		irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
241		set_irq_flags(i, IRQF_VALID);
242	}
243	irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
244	irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
245	irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
246}
247
248#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
249/* This section defines setup for the Wolfson Microelectronics
250 * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
251 * regulator definitions may be shared with them, but for now they can
252 * only be used with this board so would generate warnings about
253 * unused statics and some of the configuration is specific to this
254 * module.
255 */
256
257/* CPU */
258static struct regulator_consumer_supply sw1a_consumers[] = {
259	{
260		.supply = "cpu_vcc",
261	}
262};
263
264static struct regulator_init_data sw1a_data = {
265	.constraints = {
266		.name = "SW1A",
267		.min_uV = 1275000,
268		.max_uV = 1600000,
269		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
270				  REGULATOR_CHANGE_MODE,
271		.valid_modes_mask = REGULATOR_MODE_NORMAL |
272				    REGULATOR_MODE_FAST,
273		.state_mem = {
274			 .uV = 1400000,
275			 .mode = REGULATOR_MODE_NORMAL,
276			 .enabled = 1,
277		 },
278		.initial_state = PM_SUSPEND_MEM,
279		.always_on = 1,
280		.boot_on = 1,
281	},
282	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
283	.consumer_supplies = sw1a_consumers,
284};
285
286/* System IO - High */
287static struct regulator_init_data viohi_data = {
288	.constraints = {
289		.name = "VIOHO",
290		.min_uV = 2800000,
291		.max_uV = 2800000,
292		.state_mem = {
293			 .uV = 2800000,
294			 .mode = REGULATOR_MODE_NORMAL,
295			 .enabled = 1,
296		 },
297		.initial_state = PM_SUSPEND_MEM,
298		.always_on = 1,
299		.boot_on = 1,
300	},
301};
302
303/* System IO - Low */
304static struct regulator_init_data violo_data = {
305	.constraints = {
306		.name = "VIOLO",
307		.min_uV = 1800000,
308		.max_uV = 1800000,
309		.state_mem = {
310			 .uV = 1800000,
311			 .mode = REGULATOR_MODE_NORMAL,
312			 .enabled = 1,
313		 },
314		.initial_state = PM_SUSPEND_MEM,
315		.always_on = 1,
316		.boot_on = 1,
317	},
318};
319
320/* DDR RAM */
321static struct regulator_init_data sw2a_data = {
322	.constraints = {
323		.name = "SW2A",
324		.min_uV = 1800000,
325		.max_uV = 1800000,
326		.valid_modes_mask = REGULATOR_MODE_NORMAL,
327		.state_mem = {
328			 .uV = 1800000,
329			 .mode = REGULATOR_MODE_NORMAL,
330			 .enabled = 1,
331		 },
332		.state_disk = {
333			 .mode = REGULATOR_MODE_NORMAL,
334			 .enabled = 0,
335		 },
336		.always_on = 1,
337		.boot_on = 1,
338		.initial_state = PM_SUSPEND_MEM,
339	},
340};
341
342static struct regulator_init_data ldo1_data = {
343	.constraints = {
344		.name = "VCAM/VMMC1/VMMC2",
345		.min_uV = 2800000,
346		.max_uV = 2800000,
347		.valid_modes_mask = REGULATOR_MODE_NORMAL,
348		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
349		.apply_uV = 1,
350	},
351};
352
353static struct regulator_consumer_supply ldo2_consumers[] = {
354	{ .supply = "AVDD", .dev_name = "1-001a" },
355	{ .supply = "HPVDD", .dev_name = "1-001a" },
356};
357
358/* CODEC and SIM */
359static struct regulator_init_data ldo2_data = {
360	.constraints = {
361		.name = "VESIM/VSIM/AVDD",
362		.min_uV = 3300000,
363		.max_uV = 3300000,
364		.valid_modes_mask = REGULATOR_MODE_NORMAL,
365		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
366		.apply_uV = 1,
367	},
368	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
369	.consumer_supplies = ldo2_consumers,
370};
371
372/* General */
373static struct regulator_init_data vdig_data = {
374	.constraints = {
375		.name = "VDIG",
376		.min_uV = 1500000,
377		.max_uV = 1500000,
378		.valid_modes_mask = REGULATOR_MODE_NORMAL,
379		.apply_uV = 1,
380		.always_on = 1,
381		.boot_on = 1,
382	},
383};
384
385/* Tranceivers */
386static struct regulator_init_data ldo4_data = {
387	.constraints = {
388		.name = "VRF1/CVDD_2.775",
389		.min_uV = 2500000,
390		.max_uV = 2500000,
391		.valid_modes_mask = REGULATOR_MODE_NORMAL,
392		.apply_uV = 1,
393		.always_on = 1,
394		.boot_on = 1,
395	},
396};
397
398static struct wm8350_led_platform_data wm8350_led_data = {
399	.name            = "wm8350:white",
400	.default_trigger = "heartbeat",
401	.max_uA          = 27899,
402};
403
404static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
405	.vmid_discharge_msecs = 1000,
406	.drain_msecs = 30,
407	.cap_discharge_msecs = 700,
408	.vmid_charge_msecs = 700,
409	.vmid_s_curve = WM8350_S_CURVE_SLOW,
410	.dis_out4 = WM8350_DISCHARGE_SLOW,
411	.dis_out3 = WM8350_DISCHARGE_SLOW,
412	.dis_out2 = WM8350_DISCHARGE_SLOW,
413	.dis_out1 = WM8350_DISCHARGE_SLOW,
414	.vroi_out4 = WM8350_TIE_OFF_500R,
415	.vroi_out3 = WM8350_TIE_OFF_500R,
416	.vroi_out2 = WM8350_TIE_OFF_500R,
417	.vroi_out1 = WM8350_TIE_OFF_500R,
418	.vroi_enable = 0,
419	.codec_current_on = WM8350_CODEC_ISEL_1_0,
420	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
421	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
422};
423
424static int mx31_wm8350_init(struct wm8350 *wm8350)
425{
426	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
427			   WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
428			   WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
429			   WM8350_GPIO_DEBOUNCE_ON);
430
431	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
432			   WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
433			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
434			   WM8350_GPIO_DEBOUNCE_ON);
435
436	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
437			   WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
438			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
439			   WM8350_GPIO_DEBOUNCE_OFF);
440
441	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
442			   WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
443			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
444			   WM8350_GPIO_DEBOUNCE_OFF);
445
446	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
447			   WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
448			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
449			   WM8350_GPIO_DEBOUNCE_OFF);
450
451	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
452			   WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
453			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
454			   WM8350_GPIO_DEBOUNCE_OFF);
455
456	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
457			   WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
458			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
459			   WM8350_GPIO_DEBOUNCE_OFF);
460
461	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
462	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
463	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
464	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
465	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
466	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
467	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
468	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
469
470	/* LEDs */
471	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
472			     WM8350_DC5_ERRACT_SHUTDOWN_CONV);
473	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
474			       WM8350_ISINK_FLASH_DISABLE,
475			       WM8350_ISINK_FLASH_TRIG_BIT,
476			       WM8350_ISINK_FLASH_DUR_32MS,
477			       WM8350_ISINK_FLASH_ON_INSTANT,
478			       WM8350_ISINK_FLASH_OFF_INSTANT,
479			       WM8350_ISINK_FLASH_MODE_EN);
480	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
481			       WM8350_ISINK_MODE_BOOST,
482			       WM8350_ISINK_ILIM_NORMAL,
483			       WM8350_DC5_RMP_20V,
484			       WM8350_DC5_FBSRC_ISINKA);
485	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
486			    &wm8350_led_data);
487
488	wm8350->codec.platform_data = &imx32ads_wm8350_setup;
489
490	regulator_has_full_constraints();
491
492	return 0;
493}
494
495static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
496	.init = mx31_wm8350_init,
497};
498#endif
499
500static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
501#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
502	{
503		I2C_BOARD_INFO("wm8350", 0x1a),
504		.platform_data = &mx31_wm8350_pdata,
505		/* irq number is run-time assigned */
506	},
507#endif
508};
509
510static void __init mxc_init_i2c(void)
511{
512#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
513	mx31ads_i2c1_devices[0].irq =
514			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
515#endif
516	i2c_register_board_info(1, mx31ads_i2c1_devices,
517				ARRAY_SIZE(mx31ads_i2c1_devices));
518
519	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
520	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
521
522	imx31_add_imx_i2c1(NULL);
523}
524
525static unsigned int ssi_pins[] = {
526	MX31_PIN_SFS5__SFS5,
527	MX31_PIN_SCK5__SCK5,
528	MX31_PIN_SRXD5__SRXD5,
529	MX31_PIN_STXD5__STXD5,
530};
531
532static void __init mxc_init_audio(void)
533{
534	imx31_add_imx_ssi(0, NULL);
535	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
536}
537
538/*
539 * Static mappings, starting from the CS4 start address up to the start address
540 * of the CS8900.
541 */
542static struct map_desc mx31ads_io_desc[] __initdata = {
543	{
544		.virtual	= (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
545		.pfn		= __phys_to_pfn(MX31_CS4_BASE_ADDR),
546		.length		= CS4_CS8900_MMIO_START,
547		.type		= MT_DEVICE
548	},
549};
550
551static void __init mx31ads_map_io(void)
552{
553	mx31_map_io();
554	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
555}
556
557static void __init mx31ads_init_irq(void)
558{
559	mx31_init_irq();
560	mx31ads_init_expio();
561}
562
563static void __init mx31ads_init(void)
564{
565	imx31_soc_init();
566
567	mxc_init_extuart();
568	mxc_init_imx_uart();
569	mxc_init_i2c();
570	mxc_init_audio();
571	mxc_init_ext_ethernet();
572}
573
574static void __init mx31ads_timer_init(void)
575{
576	mx31_clocks_init(26000000);
577}
578
579MACHINE_START(MX31ADS, "Freescale MX31ADS")
580	/* Maintainer: Freescale Semiconductor, Inc. */
581	.atag_offset = 0x100,
582	.map_io = mx31ads_map_io,
583	.init_early = imx31_init_early,
584	.init_irq = mx31ads_init_irq,
585	.init_time	= mx31ads_timer_init,
586	.init_machine = mx31ads_init,
587	.restart	= mxc_restart,
588MACHINE_END
589