integrator_cp.c revision df36680f1a71eef97685c30eb9eaf55a6813b6cd 
1/*
2 *  linux/arch/arm/mach-integrator/integrator_cp.c
3 *
4 *  Copyright (C) 2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10#include <linux/types.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/list.h>
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/string.h>
17#include <linux/device.h>
18#include <linux/amba/bus.h>
19#include <linux/amba/kmi.h>
20#include <linux/amba/clcd.h>
21#include <linux/amba/mmci.h>
22#include <linux/io.h>
23#include <linux/irqchip/versatile-fpga.h>
24#include <linux/gfp.h>
25#include <linux/mtd/physmap.h>
26#include <linux/platform_data/clk-integrator.h>
27#include <linux/of_irq.h>
28#include <linux/of_address.h>
29#include <linux/of_platform.h>
30#include <linux/sys_soc.h>
31
32#include <mach/hardware.h>
33#include <mach/platform.h>
34#include <asm/setup.h>
35#include <asm/mach-types.h>
36#include <asm/hardware/arm_timer.h>
37#include <asm/hardware/icst.h>
38
39#include <mach/lm.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/map.h>
44#include <asm/mach/time.h>
45
46#include <asm/hardware/timer-sp.h>
47
48#include <plat/clcd.h>
49#include <plat/sched_clock.h>
50
51#include "cm.h"
52#include "common.h"
53
54/* Base address to the CP controller */
55static void __iomem *intcp_con_base;
56
57#define INTCP_PA_FLASH_BASE		0x24000000
58
59#define INTCP_PA_CLCD_BASE		0xc0000000
60
61#define INTCP_FLASHPROG			0x04
62#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
63#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)
64
65/*
66 * Logical      Physical
67 * f1000000	10000000	Core module registers
68 * f1100000	11000000	System controller registers
69 * f1200000	12000000	EBI registers
70 * f1300000	13000000	Counter/Timer
71 * f1400000	14000000	Interrupt controller
72 * f1600000	16000000	UART 0
73 * f1700000	17000000	UART 1
74 * f1a00000	1a000000	Debug LEDs
75 * fc900000	c9000000	GPIO
76 * fca00000	ca000000	SIC
77 * fcb00000	cb000000	CP system control
78 */
79
80static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
81	{
82		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
83		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
84		.length		= SZ_4K,
85		.type		= MT_DEVICE
86	}, {
87		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
88		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
89		.length		= SZ_4K,
90		.type		= MT_DEVICE
91	}, {
92		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
93		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
94		.length		= SZ_4K,
95		.type		= MT_DEVICE
96	}, {
97		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
98		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
99		.length		= SZ_4K,
100		.type		= MT_DEVICE
101	}, {
102		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
103		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
104		.length		= SZ_4K,
105		.type		= MT_DEVICE
106	}, {
107		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
108		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
109		.length		= SZ_4K,
110		.type		= MT_DEVICE
111	}, {
112		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
113		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
114		.length		= SZ_4K,
115		.type		= MT_DEVICE
116	}, {
117		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
118		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
119		.length		= SZ_4K,
120		.type		= MT_DEVICE
121	}
122};
123
124static void __init intcp_map_io(void)
125{
126	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
127}
128
129/*
130 * Flash handling.
131 */
132static int intcp_flash_init(struct platform_device *dev)
133{
134	u32 val;
135
136	val = readl(intcp_con_base + INTCP_FLASHPROG);
137	val |= CINTEGRATOR_FLASHPROG_FLWREN;
138	writel(val, intcp_con_base + INTCP_FLASHPROG);
139
140	return 0;
141}
142
143static void intcp_flash_exit(struct platform_device *dev)
144{
145	u32 val;
146
147	val = readl(intcp_con_base + INTCP_FLASHPROG);
148	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
149	writel(val, intcp_con_base + INTCP_FLASHPROG);
150}
151
152static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
153{
154	u32 val;
155
156	val = readl(intcp_con_base + INTCP_FLASHPROG);
157	if (on)
158		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
159	else
160		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
161	writel(val, intcp_con_base + INTCP_FLASHPROG);
162}
163
164static struct physmap_flash_data intcp_flash_data = {
165	.width		= 4,
166	.init		= intcp_flash_init,
167	.exit		= intcp_flash_exit,
168	.set_vpp	= intcp_flash_set_vpp,
169};
170
171/*
172 * It seems that the card insertion interrupt remains active after
173 * we've acknowledged it.  We therefore ignore the interrupt, and
174 * rely on reading it from the SIC.  This also means that we must
175 * clear the latched interrupt.
176 */
177static unsigned int mmc_status(struct device *dev)
178{
179	unsigned int status = readl(__io_address(0xca000000 + 4));
180	writel(8, intcp_con_base + 8);
181
182	return status & 8;
183}
184
185static struct mmci_platform_data mmc_data = {
186	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
187	.status		= mmc_status,
188	.gpio_wp	= -1,
189	.gpio_cd	= -1,
190};
191
192/*
193 * CLCD support
194 */
195/*
196 * Ensure VGA is selected.
197 */
198static void cp_clcd_enable(struct clcd_fb *fb)
199{
200	struct fb_var_screeninfo *var = &fb->fb.var;
201	u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
202
203	if (var->bits_per_pixel <= 8 ||
204	    (var->bits_per_pixel == 16 && var->green.length == 5))
205		/* Pseudocolor, RGB555, BGR555 */
206		val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
207	else if (fb->fb.var.bits_per_pixel <= 16)
208		/* truecolor RGB565 */
209		val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
210	else
211		val = 0; /* no idea for this, don't trust the docs */
212
213	cm_control(CM_CTRL_LCDMUXSEL_MASK|
214		   CM_CTRL_LCDEN0|
215		   CM_CTRL_LCDEN1|
216		   CM_CTRL_STATIC1|
217		   CM_CTRL_STATIC2|
218		   CM_CTRL_STATIC|
219		   CM_CTRL_n24BITEN, val);
220}
221
222static int cp_clcd_setup(struct clcd_fb *fb)
223{
224	fb->panel = versatile_clcd_get_panel("VGA");
225	if (!fb->panel)
226		return -EINVAL;
227
228	return versatile_clcd_setup_dma(fb, SZ_1M);
229}
230
231static struct clcd_board clcd_data = {
232	.name		= "Integrator/CP",
233	.caps		= CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
234	.check		= clcdfb_check,
235	.decode		= clcdfb_decode,
236	.enable		= cp_clcd_enable,
237	.setup		= cp_clcd_setup,
238	.mmap		= versatile_clcd_mmap_dma,
239	.remove		= versatile_clcd_remove_dma,
240};
241
242#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
243
244static void __init intcp_init_early(void)
245{
246#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
247	versatile_sched_clock_init(REFCOUNTER, 24000000);
248#endif
249}
250
251static const struct of_device_id fpga_irq_of_match[] __initconst = {
252	{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
253	{ /* Sentinel */ }
254};
255
256static void __init intcp_init_irq_of(void)
257{
258	cm_init();
259	of_irq_init(fpga_irq_of_match);
260	integrator_clk_init(true);
261}
262
263/*
264 * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
265 * and enforce the bus names since these are used for clock lookups.
266 */
267static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
268	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
269		"rtc", NULL),
270	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
271		"uart0", NULL),
272	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
273		"uart1", NULL),
274	OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
275		"kmi0", NULL),
276	OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
277		"kmi1", NULL),
278	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
279		"mmci", &mmc_data),
280	OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
281		"aaci", &mmc_data),
282	OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
283		"clcd", &clcd_data),
284	OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
285		"physmap-flash", &intcp_flash_data),
286	{ /* sentinel */ },
287};
288
289static const struct of_device_id intcp_syscon_match[] = {
290	{ .compatible = "arm,integrator-cp-syscon"},
291	{ },
292};
293
294static void __init intcp_init_of(void)
295{
296	struct device_node *root;
297	struct device_node *cpcon;
298	struct device *parent;
299	struct soc_device *soc_dev;
300	struct soc_device_attribute *soc_dev_attr;
301	u32 intcp_sc_id;
302	int err;
303
304	/* Here we create an SoC device for the root node */
305	root = of_find_node_by_path("/");
306	if (!root)
307		return;
308
309	cpcon = of_find_matching_node(root, intcp_syscon_match);
310	if (!cpcon)
311		return;
312
313	intcp_con_base = of_iomap(cpcon, 0);
314	if (!intcp_con_base)
315		return;
316
317	intcp_sc_id = readl(intcp_con_base);
318
319	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
320	if (!soc_dev_attr)
321		return;
322
323	err = of_property_read_string(root, "compatible",
324				      &soc_dev_attr->soc_id);
325	if (err)
326		return;
327	err = of_property_read_string(root, "model", &soc_dev_attr->machine);
328	if (err)
329		return;
330	soc_dev_attr->family = "Integrator";
331	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
332					   'A' + (intcp_sc_id & 0x0f));
333
334	soc_dev = soc_device_register(soc_dev_attr);
335	if (IS_ERR(soc_dev)) {
336		kfree(soc_dev_attr->revision);
337		kfree(soc_dev_attr);
338		return;
339	}
340
341	parent = soc_device_to_device(soc_dev);
342	integrator_init_sysfs(parent, intcp_sc_id);
343	of_platform_populate(root, of_default_bus_match_table,
344			intcp_auxdata_lookup, parent);
345}
346
347static const char * intcp_dt_board_compat[] = {
348	"arm,integrator-cp",
349	NULL,
350};
351
352DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
353	.reserve	= integrator_reserve,
354	.map_io		= intcp_map_io,
355	.init_early	= intcp_init_early,
356	.init_irq	= intcp_init_irq_of,
357	.handle_irq	= fpga_handle_irq,
358	.init_machine	= intcp_init_of,
359	.restart	= integrator_restart,
360	.dt_compat      = intcp_dt_board_compat,
361MACHINE_END
362