1c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek/* 2a09e64fbc0094e3073dbb09c3b4bfe4ab669244bRussell King * arch/arm/mach-iop33x/include/mach/iop33x.h 3c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * 4c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * Intel IOP33X Chip definitions 5c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * 6c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * Author: Dave Jiang (dave.jiang@intel.com) 7c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * Copyright (C) 2003, 2004 Intel Corp. 8c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * 9c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * This program is free software; you can redistribute it and/or modify 10c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * it under the terms of the GNU General Public License version 2 as 11c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * published by the Free Software Foundation. 12c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek */ 13c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek 14c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek#ifndef __IOP33X_H 15c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek#define __IOP33X_H 16c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek 17c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek/* 18c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * Peripherals that are shared between the iop32x and iop33x but 19c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek * located at different addresses. 20c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek */ 21c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg)) 22c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek 23c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek#include <asm/hardware/iop3xx.h> 24c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek 25c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek/* UARTs */ 26c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700) 27c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700) 28c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740) 29c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740) 30c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek 31e90ddd813df7897af34226ed1cd442f7a182816eDan Williams/* ATU Parameters 32e90ddd813df7897af34226ed1cd442f7a182816eDan Williams * set up a 1:1 bus to physical ram relationship 33e90ddd813df7897af34226ed1cd442f7a182816eDan Williams * w/ pci on top of physical ram in memory map 34e90ddd813df7897af34226ed1cd442f7a182816eDan Williams */ 35e90ddd813df7897af34226ed1cd442f7a182816eDan Williams#define IOP33X_MAX_RAM_SIZE 0x80000000UL 36e90ddd813df7897af34226ed1cd442f7a182816eDan Williams#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE 37e90ddd813df7897af34226ed1cd442f7a182816eDan Williams#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE) 38e90ddd813df7897af34226ed1cd442f7a182816eDan Williams 39c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek 40c852ac80440db9b0a47f48578e9c6303078abbc1Lennert Buytenhek#endif 41