clkt2xxx_dpllcore.c revision d037e100d138fb522ed0ea3e3a915bd8e0e36f63 
1/*
2 * DPLL + CORE_CLK composite clock functions
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 * XXX The DPLL and CORE clocks should be split into two separate clock
19 * types.
20 */
21#undef DEBUG
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/clk.h>
26#include <linux/io.h>
27
28#include "../plat-omap/sram.h"
29
30#include "clock.h"
31#include "clock2xxx.h"
32#include "opp2xxx.h"
33#include "cm2xxx.h"
34#include "cm-regbits-24xx.h"
35#include "sdrc.h"
36
37/* #define DOWN_VARIABLE_DPLL 1 */		/* Experimental */
38
39/*
40 * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
41 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree).  Set
42 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
43 */
44static struct clk_hw_omap *dpll_core_ck;
45
46/**
47 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
48 *
49 * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
50 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
51 * (the latter is unusual).  This currently should be called with
52 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
53 * core_ck.
54 */
55unsigned long omap2xxx_clk_get_core_rate(void)
56{
57	long long core_clk;
58	u32 v;
59
60	WARN_ON(!dpll_core_ck);
61
62	core_clk = omap2_get_dpll_rate(dpll_core_ck);
63
64	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
65	v &= OMAP24XX_CORE_CLK_SRC_MASK;
66
67	if (v == CORE_CLK_SRC_32K)
68		core_clk = 32768;
69	else
70		core_clk *= v;
71
72	return core_clk;
73}
74
75/*
76 * Uses the current prcm set to tell if a rate is valid.
77 * You can go slower, but not faster within a given rate set.
78 */
79static long omap2_dpllcore_round_rate(unsigned long target_rate)
80{
81	u32 high, low, core_clk_src;
82
83	core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
84	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
85
86	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */
87		high = curr_prcm_set->dpll_speed * 2;
88		low = curr_prcm_set->dpll_speed;
89	} else {				/* DPLL clockout x 2 */
90		high = curr_prcm_set->dpll_speed;
91		low = curr_prcm_set->dpll_speed / 2;
92	}
93
94#ifdef DOWN_VARIABLE_DPLL
95	if (target_rate > high)
96		return high;
97	else
98		return target_rate;
99#else
100	if (target_rate > low)
101		return high;
102	else
103		return low;
104#endif
105
106}
107
108unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
109				    unsigned long parent_rate)
110{
111	return omap2xxx_clk_get_core_rate();
112}
113
114int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
115			     unsigned long parent_rate)
116{
117	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
118	u32 cur_rate, low, mult, div, valid_rate, done_rate;
119	u32 bypass = 0;
120	struct prcm_config tmpset;
121	const struct dpll_data *dd;
122
123	cur_rate = omap2xxx_clk_get_core_rate();
124	mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
125	mult &= OMAP24XX_CORE_CLK_SRC_MASK;
126
127	if ((rate == (cur_rate / 2)) && (mult == 2)) {
128		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
129	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
130		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
131	} else if (rate != cur_rate) {
132		valid_rate = omap2_dpllcore_round_rate(rate);
133		if (valid_rate != rate)
134			return -EINVAL;
135
136		if (mult == 1)
137			low = curr_prcm_set->dpll_speed;
138		else
139			low = curr_prcm_set->dpll_speed / 2;
140
141		dd = clk->dpll_data;
142		if (!dd)
143			return -EINVAL;
144
145		tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
146		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
147					   dd->div1_mask);
148		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
149		tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
150		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
151		if (rate > low) {
152			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
153			mult = ((rate / 2) / 1000000);
154			done_rate = CORE_CLK_SRC_DPLL_X2;
155		} else {
156			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
157			mult = (rate / 1000000);
158			done_rate = CORE_CLK_SRC_DPLL;
159		}
160		tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
161		tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
162
163		/* Worst case */
164		tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
165
166		if (rate == curr_prcm_set->xtal_speed)	/* If asking for 1-1 */
167			bypass = 1;
168
169		/* For omap2xxx_sdrc_init_params() */
170		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
171
172		/* Force dll lock mode */
173		omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
174			       bypass);
175
176		/* Errata: ret dll entry state */
177		omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
178		omap2xxx_sdrc_reprogram(done_rate, 0);
179	}
180
181	return 0;
182}
183
184/**
185 * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
186 * @clk: struct clk *dpll_ck
187 *
188 * Store a local copy of @clk in dpll_core_ck so other code can query
189 * the core rate without having to clk_get(), which can sleep.  Must
190 * only be called once.  No return value.  XXX If the clock
191 * registration process is ever changed such that dpll_ck is no longer
192 * statically defined, this code may need to change to increment some
193 * kind of use count on dpll_ck.
194 */
195void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
196{
197	WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
198	dpll_core_ck = to_clk_hw_omap(hw);
199}
200