1657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley/* 2657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * OMAP3-specific clock framework functions 3657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * 4657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * Copyright (C) 2007-2008 Texas Instruments, Inc. 5657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * Copyright (C) 2007-2010 Nokia Corporation 6657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * 7657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * Paul Walmsley 8657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * Jouni Högander 9657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * 10657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * Parts of this code are based on code written by 11657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu 12657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * 13657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * This program is free software; you can redistribute it and/or modify 14657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * it under the terms of the GNU General Public License version 2 as 15657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * published by the Free Software Foundation. 16657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley */ 17657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#undef DEBUG 18657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 19657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#include <linux/kernel.h> 20657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#include <linux/errno.h> 21657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#include <linux/clk.h> 22657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#include <linux/io.h> 23657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 24dbc04161048dd5e5c3c58546688a0cc0854051e9Tony Lindgren#include "soc.h" 25657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#include "clock.h" 26657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#include "clock3xxx.h" 2759fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#include "prm2xxx_3xxx.h" 28657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#include "prm-regbits-34xx.h" 2959fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#include "cm2xxx_3xxx.h" 30657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#include "cm-regbits-34xx.h" 31657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 32657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley/* 33657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks 34657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * that are sourced by DPLL5, and both of these require this clock 35657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * to be at 120 MHz for proper operation. 36657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley */ 37657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley#define DPLL5_FREQ_FOR_USBHOST 120000000 38657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 39657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley/* needed by omap3_core_dpll_m2_set_rate() */ 40657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsleystruct clk *sdrc_ick_p, *arm_fck_p; 41b4777a21381fd1f87be8c606a616b7f97f485d2bRajendra Nayakint omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, 42b4777a21381fd1f87be8c606a616b7f97f485d2bRajendra Nayak unsigned long parent_rate) 43657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley{ 44657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley /* 45657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * According to the 12-5 CDP code from TI, "Limitation 2.5" 46657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * on 3430ES1 prevents us from changing DPLL multipliers or dividers 47657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley * on DPLL4. 48657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley */ 49657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley if (omap_rev() == OMAP3430_REV_ES1_0) { 507852ec0536ca39cefffc6301dc77f8ae55592926Paul Walmsley pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); 51657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley return -EINVAL; 52657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley } 53657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 54b4777a21381fd1f87be8c606a616b7f97f485d2bRajendra Nayak return omap3_noncore_dpll_set_rate(hw, rate, parent_rate); 55657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley} 56657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 57657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsleyvoid __init omap3_clk_lock_dpll5(void) 58657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley{ 59657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley struct clk *dpll5_clk; 60657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley struct clk *dpll5_m2_clk; 61657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 62657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley dpll5_clk = clk_get(NULL, "dpll5_ck"); 63657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); 644d7cb45ee823541632a3d50f57031ce9fd60e13fRajendra Nayak clk_prepare_enable(dpll5_clk); 65657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 66657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley /* Program dpll5_m2_clk divider for no division */ 67657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); 684d7cb45ee823541632a3d50f57031ce9fd60e13fRajendra Nayak clk_prepare_enable(dpll5_m2_clk); 69657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); 70657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 714d7cb45ee823541632a3d50f57031ce9fd60e13fRajendra Nayak clk_disable_unprepare(dpll5_m2_clk); 724d7cb45ee823541632a3d50f57031ce9fd60e13fRajendra Nayak clk_disable_unprepare(dpll5_clk); 73657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley return; 74657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley} 75657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 76657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley/* Common clock code */ 77657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 78657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley/* 794d30e82c26b7212021b9a5ab57760d9b8a3075fePaul Walmsley * Switch the MPU rate if specified on cmdline. We cannot do this 804d30e82c26b7212021b9a5ab57760d9b8a3075fePaul Walmsley * early until cmdline is parsed. XXX This should be removed from the 814d30e82c26b7212021b9a5ab57760d9b8a3075fePaul Walmsley * clock code and handled by the OPP layer code in the near future. 82657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley */ 83657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsleystatic int __init omap3xxx_clk_arch_init(void) 84657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley{ 854d30e82c26b7212021b9a5ab57760d9b8a3075fePaul Walmsley int ret; 86657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 87657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley if (!cpu_is_omap34xx()) 88657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley return 0; 89657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 904d30e82c26b7212021b9a5ab57760d9b8a3075fePaul Walmsley ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck"); 914d30e82c26b7212021b9a5ab57760d9b8a3075fePaul Walmsley if (!ret) 92f1f4b7703f8fd165ece458ae97ebddb2b62b2ce3Paul Walmsley omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck"); 93657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 944d30e82c26b7212021b9a5ab57760d9b8a3075fePaul Walmsley return ret; 95657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley} 964d30e82c26b7212021b9a5ab57760d9b8a3075fePaul Walmsley 97b76c8b19b082c3fc84725de0d3ba5ee1f571c0aeTony Lindgrenomap_arch_initcall(omap3xxx_clk_arch_init); 98657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 99657ebfadc19c5a14f709dee1645082828330d5d4Paul Walmsley 100