1/*
2 * OMAP2xxx CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 * Rajendra Nayak <rnayak@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/delay.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
21#include "prm2xxx.h"
22#include "cm.h"
23#include "cm2xxx.h"
24#include "cm-regbits-24xx.h"
25#include "clockdomain.h"
26
27/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
28#define DPLL_AUTOIDLE_DISABLE				0x0
29#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP		0x3
30
31/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
32#define OMAP2XXX_APLL_AUTOIDLE_DISABLE			0x0
33#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP		0x3
34
35/* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */
36#define EN_APLL_LOCKED					3
37
38static const u8 omap2xxx_cm_idlest_offs[] = {
39	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
40};
41
42/*
43 *
44 */
45
46static void _write_clktrctrl(u8 c, s16 module, u32 mask)
47{
48	u32 v;
49
50	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
51	v &= ~mask;
52	v |= c << __ffs(mask);
53	omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
54}
55
56bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
57{
58	u32 v;
59
60	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
61	v &= mask;
62	v >>= __ffs(mask);
63
64	return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
65}
66
67void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
68{
69	_write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
70}
71
72void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
73{
74	_write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
75}
76
77/*
78 * DPLL autoidle control
79 */
80
81static void _omap2xxx_set_dpll_autoidle(u8 m)
82{
83	u32 v;
84
85	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
86	v &= ~OMAP24XX_AUTO_DPLL_MASK;
87	v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
88	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
89}
90
91void omap2xxx_cm_set_dpll_disable_autoidle(void)
92{
93	_omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
94}
95
96void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
97{
98	_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
99}
100
101/*
102 * APLL control
103 */
104
105static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
106{
107	u32 v;
108
109	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
110	v &= ~mask;
111	v |= m << __ffs(mask);
112	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
113}
114
115void omap2xxx_cm_set_apll54_disable_autoidle(void)
116{
117	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
118				    OMAP24XX_AUTO_54M_MASK);
119}
120
121void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
122{
123	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
124				    OMAP24XX_AUTO_54M_MASK);
125}
126
127void omap2xxx_cm_set_apll96_disable_autoidle(void)
128{
129	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
130				    OMAP24XX_AUTO_96M_MASK);
131}
132
133void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
134{
135	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
136				    OMAP24XX_AUTO_96M_MASK);
137}
138
139/* Enable an APLL if off */
140static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit)
141{
142	u32 v, m;
143
144	m = EN_APLL_LOCKED << enable_bit;
145
146	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
147	if (v & m)
148		return 0;   /* apll already enabled */
149
150	v |= m;
151	omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
152
153	omap2xxx_cm_wait_module_ready(PLL_MOD, 1, status_bit);
154
155	/*
156	 * REVISIT: Should we return an error code if
157	 * omap2xxx_cm_wait_module_ready() fails?
158	 */
159	return 0;
160}
161
162/* Stop APLL */
163static void _omap2xxx_apll_disable(u8 enable_bit)
164{
165	u32 v;
166
167	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
168	v &= ~(EN_APLL_LOCKED << enable_bit);
169	omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
170}
171
172/* Enable an APLL if off */
173int omap2xxx_cm_apll54_enable(void)
174{
175	return _omap2xxx_apll_enable(OMAP24XX_EN_54M_PLL_SHIFT,
176				     OMAP24XX_ST_54M_APLL_SHIFT);
177}
178
179/* Enable an APLL if off */
180int omap2xxx_cm_apll96_enable(void)
181{
182	return _omap2xxx_apll_enable(OMAP24XX_EN_96M_PLL_SHIFT,
183				     OMAP24XX_ST_96M_APLL_SHIFT);
184}
185
186/* Stop APLL */
187void omap2xxx_cm_apll54_disable(void)
188{
189	_omap2xxx_apll_disable(OMAP24XX_EN_54M_PLL_SHIFT);
190}
191
192/* Stop APLL */
193void omap2xxx_cm_apll96_disable(void)
194{
195	_omap2xxx_apll_disable(OMAP24XX_EN_96M_PLL_SHIFT);
196}
197
198/**
199 * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
200 * @idlest_reg: CM_IDLEST* virtual address
201 * @prcm_inst: pointer to an s16 to return the PRCM instance offset
202 * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
203 *
204 * XXX This function is only needed until absolute register addresses are
205 * removed from the OMAP struct clk records.
206 */
207int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
208				 u8 *idlest_reg_id)
209{
210	unsigned long offs;
211	u8 idlest_offs;
212	int i;
213
214	if (idlest_reg < cm_base || idlest_reg > (cm_base + 0x0fff))
215		return -EINVAL;
216
217	idlest_offs = (unsigned long)idlest_reg & 0xff;
218	for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) {
219		if (idlest_offs == omap2xxx_cm_idlest_offs[i]) {
220			*idlest_reg_id = i + 1;
221			break;
222		}
223	}
224
225	if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs))
226		return -EINVAL;
227
228	offs = idlest_reg - cm_base;
229	offs &= 0xff00;
230	*prcm_inst = offs;
231
232	return 0;
233}
234
235/*
236 *
237 */
238
239/**
240 * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
241 * @prcm_mod: PRCM module offset
242 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
243 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
244 *
245 * Wait for the PRCM to indicate that the module identified by
246 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
247 * success or -EBUSY if the module doesn't enable in time.
248 */
249int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
250{
251	int ena = 0, i = 0;
252	u8 cm_idlest_reg;
253	u32 mask;
254
255	if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
256		return -EINVAL;
257
258	cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
259
260	mask = 1 << idlest_shift;
261	ena = mask;
262
263	omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
264			    mask) == ena), MAX_MODULE_READY_TIME, i);
265
266	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
267}
268
269/* Clockdomain low-level functions */
270
271static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
272{
273	omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
274				       clkdm->clktrctrl_mask);
275}
276
277static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
278{
279	omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
280					clkdm->clktrctrl_mask);
281}
282
283static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
284{
285	bool hwsup = false;
286
287	if (!clkdm->clktrctrl_mask)
288		return 0;
289
290	hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
291					      clkdm->clktrctrl_mask);
292	if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
293		omap2xxx_clkdm_wakeup(clkdm);
294
295	return 0;
296}
297
298static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
299{
300	bool hwsup = false;
301
302	if (!clkdm->clktrctrl_mask)
303		return 0;
304
305	hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
306					      clkdm->clktrctrl_mask);
307
308	if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
309		omap2xxx_clkdm_sleep(clkdm);
310
311	return 0;
312}
313
314struct clkdm_ops omap2_clkdm_operations = {
315	.clkdm_add_wkdep	= omap2_clkdm_add_wkdep,
316	.clkdm_del_wkdep	= omap2_clkdm_del_wkdep,
317	.clkdm_read_wkdep	= omap2_clkdm_read_wkdep,
318	.clkdm_clear_all_wkdeps	= omap2_clkdm_clear_all_wkdeps,
319	.clkdm_sleep		= omap2xxx_clkdm_sleep,
320	.clkdm_wakeup		= omap2xxx_clkdm_wakeup,
321	.clkdm_allow_idle	= omap2xxx_clkdm_allow_idle,
322	.clkdm_deny_idle	= omap2xxx_clkdm_deny_idle,
323	.clkdm_clk_enable	= omap2xxx_clkdm_clk_enable,
324	.clkdm_clk_disable	= omap2xxx_clkdm_clk_disable,
325};
326
327int omap2xxx_cm_fclks_active(void)
328{
329	u32 f1, f2;
330
331	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
332	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
333
334	return (f1 | f2) ? 1 : 0;
335}
336
337int omap2xxx_cm_mpu_retention_allowed(void)
338{
339	u32 l;
340
341	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
342	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
343	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
344		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
345		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
346		return 0;
347	/* Check for UART3. */
348	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
349	if (l & OMAP24XX_EN_UART3_MASK)
350		return 0;
351
352	return 1;
353}
354
355u32 omap2xxx_cm_get_core_clk_src(void)
356{
357	u32 v;
358
359	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
360	v &= OMAP24XX_CORE_CLK_SRC_MASK;
361
362	return v;
363}
364
365u32 omap2xxx_cm_get_core_pll_config(void)
366{
367	return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
368}
369
370u32 omap2xxx_cm_get_pll_config(void)
371{
372	return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
373}
374
375u32 omap2xxx_cm_get_pll_status(void)
376{
377	return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
378}
379
380void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
381{
382	u32 tmp;
383
384	omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
385	omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
386	omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
387	tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
388		OMAP24XX_CLKSEL_DSS2_MASK;
389	omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
390	if (mdm)
391		omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
392}
393
394/*
395 *
396 */
397
398static struct cm_ll_data omap2xxx_cm_ll_data = {
399	.split_idlest_reg	= &omap2xxx_cm_split_idlest_reg,
400	.wait_module_ready	= &omap2xxx_cm_wait_module_ready,
401};
402
403int __init omap2xxx_cm_init(void)
404{
405	return cm_register(&omap2xxx_cm_ll_data);
406}
407
408static void __exit omap2xxx_cm_exit(void)
409{
410	cm_unregister(&omap2xxx_cm_ll_data);
411}
412__exitcall(omap2xxx_cm_exit);
413