159fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley/* 259fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * OMAP2/3 Clock Management (CM) register definitions 359fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * 459fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * Copyright (C) 2007-2009 Texas Instruments, Inc. 559fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * Copyright (C) 2007-2010 Nokia Corporation 659fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * Paul Walmsley 759fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * 859fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * This program is free software; you can redistribute it and/or modify 959fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * it under the terms of the GNU General Public License version 2 as 1059fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * published by the Free Software Foundation. 1159fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * 1259fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * The CM hardware modules on the OMAP2/3 are quite similar to each 1359fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * other. The CM modules/instances on OMAP4 are quite different, so 1459fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * they are handled in a separate file. 1559fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley */ 1659fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H 1759fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H 1859fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 19d9a16f9ab9332b7cf1c95086a4efb98a0d13a57aPaul Walmsley#include "cm.h" 2059fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 2159fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley/* 2259fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * Module specific CM register offsets from CM_BASE + domain offset 2359fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * Use cm_{read,write}_mod_reg() with these registers. 2459fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley * These register offsets generally appear in more than one PRCM submodule. 2559fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley */ 2659fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 2759fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley/* Common between OMAP2 and OMAP3 */ 2859fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 2959fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_FCLKEN 0x0000 3059fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_FCLKEN1 CM_FCLKEN 3159fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_CLKEN CM_FCLKEN 3259fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_ICLKEN 0x0010 3359fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_ICLKEN1 CM_ICLKEN 3459fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_ICLKEN2 0x0014 3559fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_ICLKEN3 0x0018 3659fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_IDLEST 0x0020 3759fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_IDLEST1 CM_IDLEST 3859fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_IDLEST2 0x0024 39ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley#define OMAP2430_CM_IDLEST3 0x0028 4059fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_AUTOIDLE 0x0030 4159fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_AUTOIDLE1 CM_AUTOIDLE 4259fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_AUTOIDLE2 0x0034 4359fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_AUTOIDLE3 0x0038 4459fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_CLKSEL 0x0040 4559fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_CLKSEL1 CM_CLKSEL 4659fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define CM_CLKSEL2 0x0044 4759fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define OMAP2_CM_CLKSTCTRL 0x0048 4859fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 49ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley#ifndef __ASSEMBLER__ 5059fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 51ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley#include <linux/io.h> 5259fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 53ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsleystatic inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) 54ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley{ 55edfaf05c2fcb853fcf35f12aeb9c340f5913337fVictor Kamensky return readl_relaxed(cm_base + module + idx); 56ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley} 5759fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 58ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsleystatic inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) 59ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley{ 60edfaf05c2fcb853fcf35f12aeb9c340f5913337fVictor Kamensky writel_relaxed(val, cm_base + module + idx); 61ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley} 6259fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 63ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley/* Read-modify-write a register in a CM module. Caller must lock */ 64ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsleystatic inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, 65ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley s16 idx) 66ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley{ 67ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley u32 v; 6859fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 69ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley v = omap2_cm_read_mod_reg(module, idx); 70ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley v &= ~mask; 71ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley v |= bits; 72ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley omap2_cm_write_mod_reg(v, module, idx); 7359fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 74ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley return v; 75ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley} 7655ae35073b1c76f24c3736cf797c40d9932b19aaPaul Walmsley 774bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley/* Read a CM register, AND it, and shift the result down to bit 0 */ 784bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsleystatic inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) 794bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley{ 804bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley u32 v; 814bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley 824bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley v = omap2_cm_read_mod_reg(domain, idx); 834bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley v &= mask; 844bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley v >>= __ffs(mask); 854bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley 864bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley return v; 874bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley} 884bd5259e53accda0fe295d3b25da348f4d5f4b09Paul Walmsley 89ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsleystatic inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) 90ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley{ 91ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); 92ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley} 9355ae35073b1c76f24c3736cf797c40d9932b19aaPaul Walmsley 94ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsleystatic inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) 95ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley{ 96ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); 97ff4ae5d9319b86f940e410e92659c50f9879ff46Paul Walmsley} 9892618ff8b025419960e2e845983f0f49b0cb57a9Paul Walmsley 99b6ffa05091978c68e94d2802200f2aaa06a598d9Paul Walmsleyextern int omap2xxx_cm_apll54_enable(void); 100b6ffa05091978c68e94d2802200f2aaa06a598d9Paul Walmsleyextern void omap2xxx_cm_apll54_disable(void); 101b6ffa05091978c68e94d2802200f2aaa06a598d9Paul Walmsleyextern int omap2xxx_cm_apll96_enable(void); 102b6ffa05091978c68e94d2802200f2aaa06a598d9Paul Walmsleyextern void omap2xxx_cm_apll96_disable(void); 103b6ffa05091978c68e94d2802200f2aaa06a598d9Paul Walmsley 10459fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#endif 10559fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 10659fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley/* CM register bits shared between 24XX and 3430 */ 10759fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 10859fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley/* CM_CLKSEL_GFX */ 10959fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define OMAP_CLKSEL_GFX_SHIFT 0 11059fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define OMAP_CLKSEL_GFX_MASK (0x7 << 0) 11199e7938def490ea68e201578a83cff6248217891Rajendra Nayak#define OMAP_CLKSEL_GFX_WIDTH 3 11259fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 11359fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley/* CM_ICLKEN_GFX */ 11459fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define OMAP_EN_GFX_SHIFT 0 11559fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define OMAP_EN_GFX_MASK (1 << 0) 11659fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 11759fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley/* CM_IDLEST_GFX */ 11859fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#define OMAP_ST_GFX_MASK (1 << 0) 11959fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley 12059fb659b065f52fcc2deed293cfbfc58f890376cPaul Walmsley#endif 121