1/* 2 * GPMC support functions 3 * 4 * Copyright (C) 2005-2006 Nokia Corporation 5 * 6 * Author: Juha Yrjola 7 * 8 * Copyright (C) 2009 Texas Instruments 9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15#undef DEBUG 16 17#include <linux/irq.h> 18#include <linux/kernel.h> 19#include <linux/init.h> 20#include <linux/err.h> 21#include <linux/clk.h> 22#include <linux/ioport.h> 23#include <linux/spinlock.h> 24#include <linux/io.h> 25#include <linux/module.h> 26#include <linux/interrupt.h> 27#include <linux/platform_device.h> 28#include <linux/of.h> 29#include <linux/of_address.h> 30#include <linux/of_mtd.h> 31#include <linux/of_device.h> 32#include <linux/mtd/nand.h> 33#include <linux/pm_runtime.h> 34 35#include <linux/platform_data/mtd-nand-omap2.h> 36 37#include <asm/mach-types.h> 38 39#include "soc.h" 40#include "common.h" 41#include "omap_device.h" 42#include "gpmc.h" 43#include "gpmc-nand.h" 44#include "gpmc-onenand.h" 45 46#define DEVICE_NAME "omap-gpmc" 47 48/* GPMC register offsets */ 49#define GPMC_REVISION 0x00 50#define GPMC_SYSCONFIG 0x10 51#define GPMC_SYSSTATUS 0x14 52#define GPMC_IRQSTATUS 0x18 53#define GPMC_IRQENABLE 0x1c 54#define GPMC_TIMEOUT_CONTROL 0x40 55#define GPMC_ERR_ADDRESS 0x44 56#define GPMC_ERR_TYPE 0x48 57#define GPMC_CONFIG 0x50 58#define GPMC_STATUS 0x54 59#define GPMC_PREFETCH_CONFIG1 0x1e0 60#define GPMC_PREFETCH_CONFIG2 0x1e4 61#define GPMC_PREFETCH_CONTROL 0x1ec 62#define GPMC_PREFETCH_STATUS 0x1f0 63#define GPMC_ECC_CONFIG 0x1f4 64#define GPMC_ECC_CONTROL 0x1f8 65#define GPMC_ECC_SIZE_CONFIG 0x1fc 66#define GPMC_ECC1_RESULT 0x200 67#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ 68#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ 69#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ 70#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ 71#define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */ 72#define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */ 73#define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */ 74 75/* GPMC ECC control settings */ 76#define GPMC_ECC_CTRL_ECCCLEAR 0x100 77#define GPMC_ECC_CTRL_ECCDISABLE 0x000 78#define GPMC_ECC_CTRL_ECCREG1 0x001 79#define GPMC_ECC_CTRL_ECCREG2 0x002 80#define GPMC_ECC_CTRL_ECCREG3 0x003 81#define GPMC_ECC_CTRL_ECCREG4 0x004 82#define GPMC_ECC_CTRL_ECCREG5 0x005 83#define GPMC_ECC_CTRL_ECCREG6 0x006 84#define GPMC_ECC_CTRL_ECCREG7 0x007 85#define GPMC_ECC_CTRL_ECCREG8 0x008 86#define GPMC_ECC_CTRL_ECCREG9 0x009 87 88#define GPMC_CONFIG2_CSEXTRADELAY BIT(7) 89#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) 90#define GPMC_CONFIG4_OEEXTRADELAY BIT(7) 91#define GPMC_CONFIG4_WEEXTRADELAY BIT(23) 92#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) 93#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) 94 95#define GPMC_CS0_OFFSET 0x60 96#define GPMC_CS_SIZE 0x30 97#define GPMC_BCH_SIZE 0x10 98 99#define GPMC_MEM_END 0x3FFFFFFF 100 101#define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 102#define GPMC_SECTION_SHIFT 28 /* 128 MB */ 103 104#define CS_NUM_SHIFT 24 105#define ENABLE_PREFETCH (0x1 << 7) 106#define DMA_MPU_MODE 2 107 108#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) 109#define GPMC_REVISION_MINOR(l) (l & 0xf) 110 111#define GPMC_HAS_WR_ACCESS 0x1 112#define GPMC_HAS_WR_DATA_MUX_BUS 0x2 113#define GPMC_HAS_MUX_AAD 0x4 114 115#define GPMC_NR_WAITPINS 4 116 117/* XXX: Only NAND irq has been considered,currently these are the only ones used 118 */ 119#define GPMC_NR_IRQ 2 120 121struct gpmc_client_irq { 122 unsigned irq; 123 u32 bitmask; 124}; 125 126/* Structure to save gpmc cs context */ 127struct gpmc_cs_config { 128 u32 config1; 129 u32 config2; 130 u32 config3; 131 u32 config4; 132 u32 config5; 133 u32 config6; 134 u32 config7; 135 int is_valid; 136}; 137 138/* 139 * Structure to save/restore gpmc context 140 * to support core off on OMAP3 141 */ 142struct omap3_gpmc_regs { 143 u32 sysconfig; 144 u32 irqenable; 145 u32 timeout_ctrl; 146 u32 config; 147 u32 prefetch_config1; 148 u32 prefetch_config2; 149 u32 prefetch_control; 150 struct gpmc_cs_config cs_context[GPMC_CS_NUM]; 151}; 152 153static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; 154static struct irq_chip gpmc_irq_chip; 155static int gpmc_irq_start; 156 157static struct resource gpmc_mem_root; 158static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 159static DEFINE_SPINLOCK(gpmc_mem_lock); 160/* Define chip-selects as reserved by default until probe completes */ 161static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); 162static unsigned int gpmc_cs_num = GPMC_CS_NUM; 163static unsigned int gpmc_nr_waitpins; 164static struct device *gpmc_dev; 165static int gpmc_irq; 166static resource_size_t phys_base, mem_size; 167static unsigned gpmc_capability; 168static void __iomem *gpmc_base; 169 170static struct clk *gpmc_l3_clk; 171 172static irqreturn_t gpmc_handle_irq(int irq, void *dev); 173 174static void gpmc_write_reg(int idx, u32 val) 175{ 176 writel_relaxed(val, gpmc_base + idx); 177} 178 179static u32 gpmc_read_reg(int idx) 180{ 181 return readl_relaxed(gpmc_base + idx); 182} 183 184void gpmc_cs_write_reg(int cs, int idx, u32 val) 185{ 186 void __iomem *reg_addr; 187 188 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 189 writel_relaxed(val, reg_addr); 190} 191 192static u32 gpmc_cs_read_reg(int cs, int idx) 193{ 194 void __iomem *reg_addr; 195 196 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 197 return readl_relaxed(reg_addr); 198} 199 200/* TODO: Add support for gpmc_fck to clock framework and use it */ 201static unsigned long gpmc_get_fclk_period(void) 202{ 203 unsigned long rate = clk_get_rate(gpmc_l3_clk); 204 205 if (rate == 0) { 206 printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); 207 return 0; 208 } 209 210 rate /= 1000; 211 rate = 1000000000 / rate; /* In picoseconds */ 212 213 return rate; 214} 215 216static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 217{ 218 unsigned long tick_ps; 219 220 /* Calculate in picosecs to yield more exact results */ 221 tick_ps = gpmc_get_fclk_period(); 222 223 return (time_ns * 1000 + tick_ps - 1) / tick_ps; 224} 225 226static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) 227{ 228 unsigned long tick_ps; 229 230 /* Calculate in picosecs to yield more exact results */ 231 tick_ps = gpmc_get_fclk_period(); 232 233 return (time_ps + tick_ps - 1) / tick_ps; 234} 235 236unsigned int gpmc_ticks_to_ns(unsigned int ticks) 237{ 238 return ticks * gpmc_get_fclk_period() / 1000; 239} 240 241static unsigned int gpmc_ticks_to_ps(unsigned int ticks) 242{ 243 return ticks * gpmc_get_fclk_period(); 244} 245 246static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) 247{ 248 unsigned long ticks = gpmc_ps_to_ticks(time_ps); 249 250 return ticks * gpmc_get_fclk_period(); 251} 252 253static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) 254{ 255 u32 l; 256 257 l = gpmc_cs_read_reg(cs, reg); 258 if (value) 259 l |= mask; 260 else 261 l &= ~mask; 262 gpmc_cs_write_reg(cs, reg, l); 263} 264 265static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) 266{ 267 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, 268 GPMC_CONFIG1_TIME_PARA_GRAN, 269 p->time_para_granularity); 270 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, 271 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); 272 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, 273 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); 274 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 275 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); 276 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 277 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay); 278 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 279 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, 280 p->cycle2cyclesamecsen); 281 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 282 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, 283 p->cycle2cyclediffcsen); 284} 285 286#ifdef DEBUG 287static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, 288 int time, const char *name) 289#else 290static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, 291 int time) 292#endif 293{ 294 u32 l; 295 int ticks, mask, nr_bits; 296 297 if (time == 0) 298 ticks = 0; 299 else 300 ticks = gpmc_ns_to_ticks(time); 301 nr_bits = end_bit - st_bit + 1; 302 if (ticks >= 1 << nr_bits) { 303#ifdef DEBUG 304 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", 305 cs, name, time, ticks, 1 << nr_bits); 306#endif 307 return -1; 308 } 309 310 mask = (1 << nr_bits) - 1; 311 l = gpmc_cs_read_reg(cs, reg); 312#ifdef DEBUG 313 printk(KERN_INFO 314 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", 315 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, 316 (l >> st_bit) & mask, time); 317#endif 318 l &= ~(mask << st_bit); 319 l |= ticks << st_bit; 320 gpmc_cs_write_reg(cs, reg, l); 321 322 return 0; 323} 324 325#ifdef DEBUG 326#define GPMC_SET_ONE(reg, st, end, field) \ 327 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ 328 t->field, #field) < 0) \ 329 return -1 330#else 331#define GPMC_SET_ONE(reg, st, end, field) \ 332 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ 333 return -1 334#endif 335 336int gpmc_calc_divider(unsigned int sync_clk) 337{ 338 int div; 339 u32 l; 340 341 l = sync_clk + (gpmc_get_fclk_period() - 1); 342 div = l / gpmc_get_fclk_period(); 343 if (div > 4) 344 return -1; 345 if (div <= 0) 346 div = 1; 347 348 return div; 349} 350 351int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) 352{ 353 int div; 354 u32 l; 355 356 div = gpmc_calc_divider(t->sync_clk); 357 if (div < 0) 358 return div; 359 360 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); 361 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); 362 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); 363 364 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); 365 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); 366 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); 367 368 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); 369 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); 370 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); 371 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); 372 373 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); 374 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); 375 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); 376 377 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); 378 379 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround); 380 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay); 381 382 GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring); 383 GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation); 384 385 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 386 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); 387 if (gpmc_capability & GPMC_HAS_WR_ACCESS) 388 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); 389 390 /* caller is expected to have initialized CONFIG1 to cover 391 * at least sync vs async 392 */ 393 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 394 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { 395#ifdef DEBUG 396 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", 397 cs, (div * gpmc_get_fclk_period()) / 1000, div); 398#endif 399 l &= ~0x03; 400 l |= (div - 1); 401 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); 402 } 403 404 gpmc_cs_bool_timings(cs, &t->bool_timings); 405 406 return 0; 407} 408 409static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) 410{ 411 u32 l; 412 u32 mask; 413 414 /* 415 * Ensure that base address is aligned on a 416 * boundary equal to or greater than size. 417 */ 418 if (base & (size - 1)) 419 return -EINVAL; 420 421 mask = (1 << GPMC_SECTION_SHIFT) - size; 422 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 423 l &= ~0x3f; 424 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; 425 l &= ~(0x0f << 8); 426 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; 427 l |= GPMC_CONFIG7_CSVALID; 428 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 429 430 return 0; 431} 432 433static void gpmc_cs_disable_mem(int cs) 434{ 435 u32 l; 436 437 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 438 l &= ~GPMC_CONFIG7_CSVALID; 439 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 440} 441 442static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) 443{ 444 u32 l; 445 u32 mask; 446 447 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 448 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; 449 mask = (l >> 8) & 0x0f; 450 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); 451} 452 453static int gpmc_cs_mem_enabled(int cs) 454{ 455 u32 l; 456 457 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 458 return l & GPMC_CONFIG7_CSVALID; 459} 460 461static void gpmc_cs_set_reserved(int cs, int reserved) 462{ 463 gpmc_cs_map &= ~(1 << cs); 464 gpmc_cs_map |= (reserved ? 1 : 0) << cs; 465} 466 467static bool gpmc_cs_reserved(int cs) 468{ 469 return gpmc_cs_map & (1 << cs); 470} 471 472static unsigned long gpmc_mem_align(unsigned long size) 473{ 474 int order; 475 476 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); 477 order = GPMC_CHUNK_SHIFT - 1; 478 do { 479 size >>= 1; 480 order++; 481 } while (size); 482 size = 1 << order; 483 return size; 484} 485 486static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) 487{ 488 struct resource *res = &gpmc_cs_mem[cs]; 489 int r; 490 491 size = gpmc_mem_align(size); 492 spin_lock(&gpmc_mem_lock); 493 res->start = base; 494 res->end = base + size - 1; 495 r = request_resource(&gpmc_mem_root, res); 496 spin_unlock(&gpmc_mem_lock); 497 498 return r; 499} 500 501static int gpmc_cs_delete_mem(int cs) 502{ 503 struct resource *res = &gpmc_cs_mem[cs]; 504 int r; 505 506 spin_lock(&gpmc_mem_lock); 507 r = release_resource(res); 508 res->start = 0; 509 res->end = 0; 510 spin_unlock(&gpmc_mem_lock); 511 512 return r; 513} 514 515/** 516 * gpmc_cs_remap - remaps a chip-select physical base address 517 * @cs: chip-select to remap 518 * @base: physical base address to re-map chip-select to 519 * 520 * Re-maps a chip-select to a new physical base address specified by 521 * "base". Returns 0 on success and appropriate negative error code 522 * on failure. 523 */ 524static int gpmc_cs_remap(int cs, u32 base) 525{ 526 int ret; 527 u32 old_base, size; 528 529 if (cs > gpmc_cs_num) { 530 pr_err("%s: requested chip-select is disabled\n", __func__); 531 return -ENODEV; 532 } 533 534 /* 535 * Make sure we ignore any device offsets from the GPMC partition 536 * allocated for the chip select and that the new base confirms 537 * to the GPMC 16MB minimum granularity. 538 */ 539 base &= ~(SZ_16M - 1); 540 541 gpmc_cs_get_memconf(cs, &old_base, &size); 542 if (base == old_base) 543 return 0; 544 gpmc_cs_disable_mem(cs); 545 ret = gpmc_cs_delete_mem(cs); 546 if (ret < 0) 547 return ret; 548 ret = gpmc_cs_insert_mem(cs, base, size); 549 if (ret < 0) 550 return ret; 551 ret = gpmc_cs_enable_mem(cs, base, size); 552 if (ret < 0) 553 return ret; 554 555 return 0; 556} 557 558int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) 559{ 560 struct resource *res = &gpmc_cs_mem[cs]; 561 int r = -1; 562 563 if (cs > gpmc_cs_num) { 564 pr_err("%s: requested chip-select is disabled\n", __func__); 565 return -ENODEV; 566 } 567 size = gpmc_mem_align(size); 568 if (size > (1 << GPMC_SECTION_SHIFT)) 569 return -ENOMEM; 570 571 spin_lock(&gpmc_mem_lock); 572 if (gpmc_cs_reserved(cs)) { 573 r = -EBUSY; 574 goto out; 575 } 576 if (gpmc_cs_mem_enabled(cs)) 577 r = adjust_resource(res, res->start & ~(size - 1), size); 578 if (r < 0) 579 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, 580 size, NULL, NULL); 581 if (r < 0) 582 goto out; 583 584 r = gpmc_cs_enable_mem(cs, res->start, resource_size(res)); 585 if (r < 0) { 586 release_resource(res); 587 goto out; 588 } 589 590 *base = res->start; 591 gpmc_cs_set_reserved(cs, 1); 592out: 593 spin_unlock(&gpmc_mem_lock); 594 return r; 595} 596EXPORT_SYMBOL(gpmc_cs_request); 597 598void gpmc_cs_free(int cs) 599{ 600 struct resource *res = &gpmc_cs_mem[cs]; 601 602 spin_lock(&gpmc_mem_lock); 603 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { 604 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); 605 BUG(); 606 spin_unlock(&gpmc_mem_lock); 607 return; 608 } 609 gpmc_cs_disable_mem(cs); 610 if (res->flags) 611 release_resource(res); 612 gpmc_cs_set_reserved(cs, 0); 613 spin_unlock(&gpmc_mem_lock); 614} 615EXPORT_SYMBOL(gpmc_cs_free); 616 617/** 618 * gpmc_configure - write request to configure gpmc 619 * @cmd: command type 620 * @wval: value to write 621 * @return status of the operation 622 */ 623int gpmc_configure(int cmd, int wval) 624{ 625 u32 regval; 626 627 switch (cmd) { 628 case GPMC_ENABLE_IRQ: 629 gpmc_write_reg(GPMC_IRQENABLE, wval); 630 break; 631 632 case GPMC_SET_IRQ_STATUS: 633 gpmc_write_reg(GPMC_IRQSTATUS, wval); 634 break; 635 636 case GPMC_CONFIG_WP: 637 regval = gpmc_read_reg(GPMC_CONFIG); 638 if (wval) 639 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ 640 else 641 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ 642 gpmc_write_reg(GPMC_CONFIG, regval); 643 break; 644 645 default: 646 pr_err("%s: command not supported\n", __func__); 647 return -EINVAL; 648 } 649 650 return 0; 651} 652EXPORT_SYMBOL(gpmc_configure); 653 654void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) 655{ 656 int i; 657 658 reg->gpmc_status = gpmc_base + GPMC_STATUS; 659 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + 660 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; 661 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + 662 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; 663 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + 664 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; 665 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; 666 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; 667 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; 668 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; 669 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; 670 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; 671 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; 672 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; 673 674 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { 675 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + 676 GPMC_BCH_SIZE * i; 677 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + 678 GPMC_BCH_SIZE * i; 679 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + 680 GPMC_BCH_SIZE * i; 681 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + 682 GPMC_BCH_SIZE * i; 683 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + 684 i * GPMC_BCH_SIZE; 685 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + 686 i * GPMC_BCH_SIZE; 687 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + 688 i * GPMC_BCH_SIZE; 689 } 690} 691 692int gpmc_get_client_irq(unsigned irq_config) 693{ 694 int i; 695 696 if (hweight32(irq_config) > 1) 697 return 0; 698 699 for (i = 0; i < GPMC_NR_IRQ; i++) 700 if (gpmc_client_irq[i].bitmask & irq_config) 701 return gpmc_client_irq[i].irq; 702 703 return 0; 704} 705 706static int gpmc_irq_endis(unsigned irq, bool endis) 707{ 708 int i; 709 u32 regval; 710 711 for (i = 0; i < GPMC_NR_IRQ; i++) 712 if (irq == gpmc_client_irq[i].irq) { 713 regval = gpmc_read_reg(GPMC_IRQENABLE); 714 if (endis) 715 regval |= gpmc_client_irq[i].bitmask; 716 else 717 regval &= ~gpmc_client_irq[i].bitmask; 718 gpmc_write_reg(GPMC_IRQENABLE, regval); 719 break; 720 } 721 722 return 0; 723} 724 725static void gpmc_irq_disable(struct irq_data *p) 726{ 727 gpmc_irq_endis(p->irq, false); 728} 729 730static void gpmc_irq_enable(struct irq_data *p) 731{ 732 gpmc_irq_endis(p->irq, true); 733} 734 735static void gpmc_irq_noop(struct irq_data *data) { } 736 737static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } 738 739static int gpmc_setup_irq(void) 740{ 741 int i; 742 u32 regval; 743 744 if (!gpmc_irq) 745 return -EINVAL; 746 747 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); 748 if (gpmc_irq_start < 0) { 749 pr_err("irq_alloc_descs failed\n"); 750 return gpmc_irq_start; 751 } 752 753 gpmc_irq_chip.name = "gpmc"; 754 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; 755 gpmc_irq_chip.irq_enable = gpmc_irq_enable; 756 gpmc_irq_chip.irq_disable = gpmc_irq_disable; 757 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; 758 gpmc_irq_chip.irq_ack = gpmc_irq_noop; 759 gpmc_irq_chip.irq_mask = gpmc_irq_noop; 760 gpmc_irq_chip.irq_unmask = gpmc_irq_noop; 761 762 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; 763 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; 764 765 for (i = 0; i < GPMC_NR_IRQ; i++) { 766 gpmc_client_irq[i].irq = gpmc_irq_start + i; 767 irq_set_chip_and_handler(gpmc_client_irq[i].irq, 768 &gpmc_irq_chip, handle_simple_irq); 769 set_irq_flags(gpmc_client_irq[i].irq, 770 IRQF_VALID | IRQF_NOAUTOEN); 771 } 772 773 /* Disable interrupts */ 774 gpmc_write_reg(GPMC_IRQENABLE, 0); 775 776 /* clear interrupts */ 777 regval = gpmc_read_reg(GPMC_IRQSTATUS); 778 gpmc_write_reg(GPMC_IRQSTATUS, regval); 779 780 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); 781} 782 783static int gpmc_free_irq(void) 784{ 785 int i; 786 787 if (gpmc_irq) 788 free_irq(gpmc_irq, NULL); 789 790 for (i = 0; i < GPMC_NR_IRQ; i++) { 791 irq_set_handler(gpmc_client_irq[i].irq, NULL); 792 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip); 793 irq_modify_status(gpmc_client_irq[i].irq, 0, 0); 794 } 795 796 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ); 797 798 return 0; 799} 800 801static void gpmc_mem_exit(void) 802{ 803 int cs; 804 805 for (cs = 0; cs < gpmc_cs_num; cs++) { 806 if (!gpmc_cs_mem_enabled(cs)) 807 continue; 808 gpmc_cs_delete_mem(cs); 809 } 810 811} 812 813static void gpmc_mem_init(void) 814{ 815 int cs; 816 817 /* 818 * The first 1MB of GPMC address space is typically mapped to 819 * the internal ROM. Never allocate the first page, to 820 * facilitate bug detection; even if we didn't boot from ROM. 821 */ 822 gpmc_mem_root.start = SZ_1M; 823 gpmc_mem_root.end = GPMC_MEM_END; 824 825 /* Reserve all regions that has been set up by bootloader */ 826 for (cs = 0; cs < gpmc_cs_num; cs++) { 827 u32 base, size; 828 829 if (!gpmc_cs_mem_enabled(cs)) 830 continue; 831 gpmc_cs_get_memconf(cs, &base, &size); 832 if (gpmc_cs_insert_mem(cs, base, size)) { 833 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", 834 __func__, cs, base, base + size); 835 gpmc_cs_disable_mem(cs); 836 } 837 } 838} 839 840static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) 841{ 842 u32 temp; 843 int div; 844 845 div = gpmc_calc_divider(sync_clk); 846 temp = gpmc_ps_to_ticks(time_ps); 847 temp = (temp + div - 1) / div; 848 return gpmc_ticks_to_ps(temp * div); 849} 850 851/* XXX: can the cycles be avoided ? */ 852static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, 853 struct gpmc_device_timings *dev_t, 854 bool mux) 855{ 856 u32 temp; 857 858 /* adv_rd_off */ 859 temp = dev_t->t_avdp_r; 860 /* XXX: mux check required ? */ 861 if (mux) { 862 /* XXX: t_avdp not to be required for sync, only added for tusb 863 * this indirectly necessitates requirement of t_avdp_r and 864 * t_avdp_w instead of having a single t_avdp 865 */ 866 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); 867 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 868 } 869 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 870 871 /* oe_on */ 872 temp = dev_t->t_oeasu; /* XXX: remove this ? */ 873 if (mux) { 874 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); 875 temp = max_t(u32, temp, gpmc_t->adv_rd_off + 876 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); 877 } 878 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 879 880 /* access */ 881 /* XXX: any scope for improvement ?, by combining oe_on 882 * and clk_activation, need to check whether 883 * access = clk_activation + round to sync clk ? 884 */ 885 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); 886 temp += gpmc_t->clk_activation; 887 if (dev_t->cyc_oe) 888 temp = max_t(u32, temp, gpmc_t->oe_on + 889 gpmc_ticks_to_ps(dev_t->cyc_oe)); 890 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 891 892 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 893 gpmc_t->cs_rd_off = gpmc_t->oe_off; 894 895 /* rd_cycle */ 896 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); 897 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + 898 gpmc_t->access; 899 /* XXX: barter t_ce_rdyz with t_cez_r ? */ 900 if (dev_t->t_ce_rdyz) 901 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); 902 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 903 904 return 0; 905} 906 907static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, 908 struct gpmc_device_timings *dev_t, 909 bool mux) 910{ 911 u32 temp; 912 913 /* adv_wr_off */ 914 temp = dev_t->t_avdp_w; 915 if (mux) { 916 temp = max_t(u32, temp, 917 gpmc_t->clk_activation + dev_t->t_avdh); 918 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 919 } 920 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 921 922 /* wr_data_mux_bus */ 923 temp = max_t(u32, dev_t->t_weasu, 924 gpmc_t->clk_activation + dev_t->t_rdyo); 925 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, 926 * and in that case remember to handle we_on properly 927 */ 928 if (mux) { 929 temp = max_t(u32, temp, 930 gpmc_t->adv_wr_off + dev_t->t_aavdh); 931 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 932 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 933 } 934 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 935 936 /* we_on */ 937 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 938 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 939 else 940 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 941 942 /* wr_access */ 943 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ 944 gpmc_t->wr_access = gpmc_t->access; 945 946 /* we_off */ 947 temp = gpmc_t->we_on + dev_t->t_wpl; 948 temp = max_t(u32, temp, 949 gpmc_t->wr_access + gpmc_ticks_to_ps(1)); 950 temp = max_t(u32, temp, 951 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); 952 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 953 954 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 955 dev_t->t_wph); 956 957 /* wr_cycle */ 958 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); 959 temp += gpmc_t->wr_access; 960 /* XXX: barter t_ce_rdyz with t_cez_w ? */ 961 if (dev_t->t_ce_rdyz) 962 temp = max_t(u32, temp, 963 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); 964 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 965 966 return 0; 967} 968 969static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, 970 struct gpmc_device_timings *dev_t, 971 bool mux) 972{ 973 u32 temp; 974 975 /* adv_rd_off */ 976 temp = dev_t->t_avdp_r; 977 if (mux) 978 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 979 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 980 981 /* oe_on */ 982 temp = dev_t->t_oeasu; 983 if (mux) 984 temp = max_t(u32, temp, 985 gpmc_t->adv_rd_off + dev_t->t_aavdh); 986 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 987 988 /* access */ 989 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ 990 gpmc_t->oe_on + dev_t->t_oe); 991 temp = max_t(u32, temp, 992 gpmc_t->cs_on + dev_t->t_ce); 993 temp = max_t(u32, temp, 994 gpmc_t->adv_on + dev_t->t_aa); 995 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 996 997 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 998 gpmc_t->cs_rd_off = gpmc_t->oe_off; 999 1000 /* rd_cycle */ 1001 temp = max_t(u32, dev_t->t_rd_cycle, 1002 gpmc_t->cs_rd_off + dev_t->t_cez_r); 1003 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); 1004 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 1005 1006 return 0; 1007} 1008 1009static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, 1010 struct gpmc_device_timings *dev_t, 1011 bool mux) 1012{ 1013 u32 temp; 1014 1015 /* adv_wr_off */ 1016 temp = dev_t->t_avdp_w; 1017 if (mux) 1018 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1019 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 1020 1021 /* wr_data_mux_bus */ 1022 temp = dev_t->t_weasu; 1023 if (mux) { 1024 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); 1025 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 1026 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 1027 } 1028 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 1029 1030 /* we_on */ 1031 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 1032 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 1033 else 1034 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 1035 1036 /* we_off */ 1037 temp = gpmc_t->we_on + dev_t->t_wpl; 1038 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 1039 1040 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 1041 dev_t->t_wph); 1042 1043 /* wr_cycle */ 1044 temp = max_t(u32, dev_t->t_wr_cycle, 1045 gpmc_t->cs_wr_off + dev_t->t_cez_w); 1046 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 1047 1048 return 0; 1049} 1050 1051static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, 1052 struct gpmc_device_timings *dev_t) 1053{ 1054 u32 temp; 1055 1056 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * 1057 gpmc_get_fclk_period(); 1058 1059 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( 1060 dev_t->t_bacc, 1061 gpmc_t->sync_clk); 1062 1063 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); 1064 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); 1065 1066 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) 1067 return 0; 1068 1069 if (dev_t->ce_xdelay) 1070 gpmc_t->bool_timings.cs_extra_delay = true; 1071 if (dev_t->avd_xdelay) 1072 gpmc_t->bool_timings.adv_extra_delay = true; 1073 if (dev_t->oe_xdelay) 1074 gpmc_t->bool_timings.oe_extra_delay = true; 1075 if (dev_t->we_xdelay) 1076 gpmc_t->bool_timings.we_extra_delay = true; 1077 1078 return 0; 1079} 1080 1081static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, 1082 struct gpmc_device_timings *dev_t, 1083 bool sync) 1084{ 1085 u32 temp; 1086 1087 /* cs_on */ 1088 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); 1089 1090 /* adv_on */ 1091 temp = dev_t->t_avdasu; 1092 if (dev_t->t_ce_avd) 1093 temp = max_t(u32, temp, 1094 gpmc_t->cs_on + dev_t->t_ce_avd); 1095 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); 1096 1097 if (sync) 1098 gpmc_calc_sync_common_timings(gpmc_t, dev_t); 1099 1100 return 0; 1101} 1102 1103/* TODO: remove this function once all peripherals are confirmed to 1104 * work with generic timing. Simultaneously gpmc_cs_set_timings() 1105 * has to be modified to handle timings in ps instead of ns 1106*/ 1107static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) 1108{ 1109 t->cs_on /= 1000; 1110 t->cs_rd_off /= 1000; 1111 t->cs_wr_off /= 1000; 1112 t->adv_on /= 1000; 1113 t->adv_rd_off /= 1000; 1114 t->adv_wr_off /= 1000; 1115 t->we_on /= 1000; 1116 t->we_off /= 1000; 1117 t->oe_on /= 1000; 1118 t->oe_off /= 1000; 1119 t->page_burst_access /= 1000; 1120 t->access /= 1000; 1121 t->rd_cycle /= 1000; 1122 t->wr_cycle /= 1000; 1123 t->bus_turnaround /= 1000; 1124 t->cycle2cycle_delay /= 1000; 1125 t->wait_monitoring /= 1000; 1126 t->clk_activation /= 1000; 1127 t->wr_access /= 1000; 1128 t->wr_data_mux_bus /= 1000; 1129} 1130 1131int gpmc_calc_timings(struct gpmc_timings *gpmc_t, 1132 struct gpmc_settings *gpmc_s, 1133 struct gpmc_device_timings *dev_t) 1134{ 1135 bool mux = false, sync = false; 1136 1137 if (gpmc_s) { 1138 mux = gpmc_s->mux_add_data ? true : false; 1139 sync = (gpmc_s->sync_read || gpmc_s->sync_write); 1140 } 1141 1142 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1143 1144 gpmc_calc_common_timings(gpmc_t, dev_t, sync); 1145 1146 if (gpmc_s && gpmc_s->sync_read) 1147 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); 1148 else 1149 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); 1150 1151 if (gpmc_s && gpmc_s->sync_write) 1152 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); 1153 else 1154 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); 1155 1156 /* TODO: remove, see function definition */ 1157 gpmc_convert_ps_to_ns(gpmc_t); 1158 1159 return 0; 1160} 1161 1162/** 1163 * gpmc_cs_program_settings - programs non-timing related settings 1164 * @cs: GPMC chip-select to program 1165 * @p: pointer to GPMC settings structure 1166 * 1167 * Programs non-timing related settings for a GPMC chip-select, such as 1168 * bus-width, burst configuration, etc. Function should be called once 1169 * for each chip-select that is being used and must be called before 1170 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 1171 * register will be initialised to zero by this function. Returns 0 on 1172 * success and appropriate negative error code on failure. 1173 */ 1174int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) 1175{ 1176 u32 config1; 1177 1178 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { 1179 pr_err("%s: invalid width %d!", __func__, p->device_width); 1180 return -EINVAL; 1181 } 1182 1183 /* Address-data multiplexing not supported for NAND devices */ 1184 if (p->device_nand && p->mux_add_data) { 1185 pr_err("%s: invalid configuration!\n", __func__); 1186 return -EINVAL; 1187 } 1188 1189 if ((p->mux_add_data > GPMC_MUX_AD) || 1190 ((p->mux_add_data == GPMC_MUX_AAD) && 1191 !(gpmc_capability & GPMC_HAS_MUX_AAD))) { 1192 pr_err("%s: invalid multiplex configuration!\n", __func__); 1193 return -EINVAL; 1194 } 1195 1196 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ 1197 if (p->burst_read || p->burst_write) { 1198 switch (p->burst_len) { 1199 case GPMC_BURST_4: 1200 case GPMC_BURST_8: 1201 case GPMC_BURST_16: 1202 break; 1203 default: 1204 pr_err("%s: invalid page/burst-length (%d)\n", 1205 __func__, p->burst_len); 1206 return -EINVAL; 1207 } 1208 } 1209 1210 if (p->wait_pin > gpmc_nr_waitpins) { 1211 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); 1212 return -EINVAL; 1213 } 1214 1215 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); 1216 1217 if (p->sync_read) 1218 config1 |= GPMC_CONFIG1_READTYPE_SYNC; 1219 if (p->sync_write) 1220 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; 1221 if (p->wait_on_read) 1222 config1 |= GPMC_CONFIG1_WAIT_READ_MON; 1223 if (p->wait_on_write) 1224 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; 1225 if (p->wait_on_read || p->wait_on_write) 1226 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); 1227 if (p->device_nand) 1228 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); 1229 if (p->mux_add_data) 1230 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); 1231 if (p->burst_read) 1232 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; 1233 if (p->burst_write) 1234 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; 1235 if (p->burst_read || p->burst_write) { 1236 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); 1237 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; 1238 } 1239 1240 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); 1241 1242 return 0; 1243} 1244 1245#ifdef CONFIG_OF 1246static const struct of_device_id gpmc_dt_ids[] = { 1247 { .compatible = "ti,omap2420-gpmc" }, 1248 { .compatible = "ti,omap2430-gpmc" }, 1249 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ 1250 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ 1251 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ 1252 { } 1253}; 1254MODULE_DEVICE_TABLE(of, gpmc_dt_ids); 1255 1256/** 1257 * gpmc_read_settings_dt - read gpmc settings from device-tree 1258 * @np: pointer to device-tree node for a gpmc child device 1259 * @p: pointer to gpmc settings structure 1260 * 1261 * Reads the GPMC settings for a GPMC child device from device-tree and 1262 * stores them in the GPMC settings structure passed. The GPMC settings 1263 * structure is initialised to zero by this function and so any 1264 * previously stored settings will be cleared. 1265 */ 1266void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) 1267{ 1268 memset(p, 0, sizeof(struct gpmc_settings)); 1269 1270 p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); 1271 p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); 1272 of_property_read_u32(np, "gpmc,device-width", &p->device_width); 1273 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); 1274 1275 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { 1276 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); 1277 p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); 1278 p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); 1279 if (!p->burst_read && !p->burst_write) 1280 pr_warn("%s: page/burst-length set but not used!\n", 1281 __func__); 1282 } 1283 1284 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { 1285 p->wait_on_read = of_property_read_bool(np, 1286 "gpmc,wait-on-read"); 1287 p->wait_on_write = of_property_read_bool(np, 1288 "gpmc,wait-on-write"); 1289 if (!p->wait_on_read && !p->wait_on_write) 1290 pr_debug("%s: rd/wr wait monitoring not enabled!\n", 1291 __func__); 1292 } 1293} 1294 1295static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, 1296 struct gpmc_timings *gpmc_t) 1297{ 1298 struct gpmc_bool_timings *p; 1299 1300 if (!np || !gpmc_t) 1301 return; 1302 1303 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1304 1305 /* minimum clock period for syncronous mode */ 1306 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); 1307 1308 /* chip select timtings */ 1309 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); 1310 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); 1311 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); 1312 1313 /* ADV signal timings */ 1314 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); 1315 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); 1316 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); 1317 1318 /* WE signal timings */ 1319 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); 1320 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); 1321 1322 /* OE signal timings */ 1323 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); 1324 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); 1325 1326 /* access and cycle timings */ 1327 of_property_read_u32(np, "gpmc,page-burst-access-ns", 1328 &gpmc_t->page_burst_access); 1329 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); 1330 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); 1331 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); 1332 of_property_read_u32(np, "gpmc,bus-turnaround-ns", 1333 &gpmc_t->bus_turnaround); 1334 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", 1335 &gpmc_t->cycle2cycle_delay); 1336 of_property_read_u32(np, "gpmc,wait-monitoring-ns", 1337 &gpmc_t->wait_monitoring); 1338 of_property_read_u32(np, "gpmc,clk-activation-ns", 1339 &gpmc_t->clk_activation); 1340 1341 /* only applicable to OMAP3+ */ 1342 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); 1343 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", 1344 &gpmc_t->wr_data_mux_bus); 1345 1346 /* bool timing parameters */ 1347 p = &gpmc_t->bool_timings; 1348 1349 p->cycle2cyclediffcsen = 1350 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); 1351 p->cycle2cyclesamecsen = 1352 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); 1353 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); 1354 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); 1355 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); 1356 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); 1357 p->time_para_granularity = 1358 of_property_read_bool(np, "gpmc,time-para-granularity"); 1359} 1360 1361#if IS_ENABLED(CONFIG_MTD_NAND) 1362 1363static const char * const nand_xfer_types[] = { 1364 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", 1365 [NAND_OMAP_POLLED] = "polled", 1366 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma", 1367 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq", 1368}; 1369 1370static int gpmc_probe_nand_child(struct platform_device *pdev, 1371 struct device_node *child) 1372{ 1373 u32 val; 1374 const char *s; 1375 struct gpmc_timings gpmc_t; 1376 struct omap_nand_platform_data *gpmc_nand_data; 1377 1378 if (of_property_read_u32(child, "reg", &val) < 0) { 1379 dev_err(&pdev->dev, "%s has no 'reg' property\n", 1380 child->full_name); 1381 return -ENODEV; 1382 } 1383 1384 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data), 1385 GFP_KERNEL); 1386 if (!gpmc_nand_data) 1387 return -ENOMEM; 1388 1389 gpmc_nand_data->cs = val; 1390 gpmc_nand_data->of_node = child; 1391 1392 /* Detect availability of ELM module */ 1393 gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0); 1394 if (gpmc_nand_data->elm_of_node == NULL) 1395 gpmc_nand_data->elm_of_node = 1396 of_parse_phandle(child, "elm_id", 0); 1397 if (gpmc_nand_data->elm_of_node == NULL) 1398 pr_warn("%s: ti,elm-id property not found\n", __func__); 1399 1400 /* select ecc-scheme for NAND */ 1401 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) { 1402 pr_err("%s: ti,nand-ecc-opt not found\n", __func__); 1403 return -ENODEV; 1404 } 1405 1406 if (!strcmp(s, "sw")) 1407 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW; 1408 else if (!strcmp(s, "ham1") || 1409 !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) 1410 gpmc_nand_data->ecc_opt = 1411 OMAP_ECC_HAM1_CODE_HW; 1412 else if (!strcmp(s, "bch4")) 1413 if (gpmc_nand_data->elm_of_node) 1414 gpmc_nand_data->ecc_opt = 1415 OMAP_ECC_BCH4_CODE_HW; 1416 else 1417 gpmc_nand_data->ecc_opt = 1418 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW; 1419 else if (!strcmp(s, "bch8")) 1420 if (gpmc_nand_data->elm_of_node) 1421 gpmc_nand_data->ecc_opt = 1422 OMAP_ECC_BCH8_CODE_HW; 1423 else 1424 gpmc_nand_data->ecc_opt = 1425 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; 1426 else if (!strcmp(s, "bch16")) 1427 if (gpmc_nand_data->elm_of_node) 1428 gpmc_nand_data->ecc_opt = 1429 OMAP_ECC_BCH16_CODE_HW; 1430 else 1431 pr_err("%s: BCH16 requires ELM support\n", __func__); 1432 else 1433 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__); 1434 1435 /* select data transfer mode for NAND controller */ 1436 if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) 1437 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++) 1438 if (!strcasecmp(s, nand_xfer_types[val])) { 1439 gpmc_nand_data->xfer_type = val; 1440 break; 1441 } 1442 1443 gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child); 1444 1445 val = of_get_nand_bus_width(child); 1446 if (val == 16) 1447 gpmc_nand_data->devsize = NAND_BUSWIDTH_16; 1448 1449 gpmc_read_timings_dt(child, &gpmc_t); 1450 gpmc_nand_init(gpmc_nand_data, &gpmc_t); 1451 1452 return 0; 1453} 1454#else 1455static int gpmc_probe_nand_child(struct platform_device *pdev, 1456 struct device_node *child) 1457{ 1458 return 0; 1459} 1460#endif 1461 1462#if IS_ENABLED(CONFIG_MTD_ONENAND) 1463static int gpmc_probe_onenand_child(struct platform_device *pdev, 1464 struct device_node *child) 1465{ 1466 u32 val; 1467 struct omap_onenand_platform_data *gpmc_onenand_data; 1468 1469 if (of_property_read_u32(child, "reg", &val) < 0) { 1470 dev_err(&pdev->dev, "%s has no 'reg' property\n", 1471 child->full_name); 1472 return -ENODEV; 1473 } 1474 1475 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data), 1476 GFP_KERNEL); 1477 if (!gpmc_onenand_data) 1478 return -ENOMEM; 1479 1480 gpmc_onenand_data->cs = val; 1481 gpmc_onenand_data->of_node = child; 1482 gpmc_onenand_data->dma_channel = -1; 1483 1484 if (!of_property_read_u32(child, "dma-channel", &val)) 1485 gpmc_onenand_data->dma_channel = val; 1486 1487 gpmc_onenand_init(gpmc_onenand_data); 1488 1489 return 0; 1490} 1491#else 1492static int gpmc_probe_onenand_child(struct platform_device *pdev, 1493 struct device_node *child) 1494{ 1495 return 0; 1496} 1497#endif 1498 1499/** 1500 * gpmc_probe_generic_child - configures the gpmc for a child device 1501 * @pdev: pointer to gpmc platform device 1502 * @child: pointer to device-tree node for child device 1503 * 1504 * Allocates and configures a GPMC chip-select for a child device. 1505 * Returns 0 on success and appropriate negative error code on failure. 1506 */ 1507static int gpmc_probe_generic_child(struct platform_device *pdev, 1508 struct device_node *child) 1509{ 1510 struct gpmc_settings gpmc_s; 1511 struct gpmc_timings gpmc_t; 1512 struct resource res; 1513 unsigned long base; 1514 int ret, cs; 1515 1516 if (of_property_read_u32(child, "reg", &cs) < 0) { 1517 dev_err(&pdev->dev, "%s has no 'reg' property\n", 1518 child->full_name); 1519 return -ENODEV; 1520 } 1521 1522 if (of_address_to_resource(child, 0, &res) < 0) { 1523 dev_err(&pdev->dev, "%s has malformed 'reg' property\n", 1524 child->full_name); 1525 return -ENODEV; 1526 } 1527 1528 ret = gpmc_cs_request(cs, resource_size(&res), &base); 1529 if (ret < 0) { 1530 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); 1531 return ret; 1532 } 1533 1534 /* 1535 * For some GPMC devices we still need to rely on the bootloader 1536 * timings because the devices can be connected via FPGA. So far 1537 * the list is smc91x on the omap2 SDP boards, and 8250 on zooms. 1538 * REVISIT: Add timing support from slls644g.pdf and from the 1539 * lan91c96 manual. 1540 */ 1541 if (of_device_is_compatible(child, "ns16550a") || 1542 of_device_is_compatible(child, "smsc,lan91c94") || 1543 of_device_is_compatible(child, "smsc,lan91c111")) { 1544 dev_warn(&pdev->dev, 1545 "%s using bootloader timings on CS%d\n", 1546 child->name, cs); 1547 goto no_timings; 1548 } 1549 1550 /* 1551 * FIXME: gpmc_cs_request() will map the CS to an arbitary 1552 * location in the gpmc address space. When booting with 1553 * device-tree we want the NOR flash to be mapped to the 1554 * location specified in the device-tree blob. So remap the 1555 * CS to this location. Once DT migration is complete should 1556 * just make gpmc_cs_request() map a specific address. 1557 */ 1558 ret = gpmc_cs_remap(cs, res.start); 1559 if (ret < 0) { 1560 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", 1561 cs, &res.start); 1562 goto err; 1563 } 1564 1565 gpmc_read_settings_dt(child, &gpmc_s); 1566 1567 ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width); 1568 if (ret < 0) 1569 goto err; 1570 1571 ret = gpmc_cs_program_settings(cs, &gpmc_s); 1572 if (ret < 0) 1573 goto err; 1574 1575 gpmc_read_timings_dt(child, &gpmc_t); 1576 gpmc_cs_set_timings(cs, &gpmc_t); 1577 1578no_timings: 1579 if (of_platform_device_create(child, NULL, &pdev->dev)) 1580 return 0; 1581 1582 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name); 1583 ret = -ENODEV; 1584 1585err: 1586 gpmc_cs_free(cs); 1587 1588 return ret; 1589} 1590 1591static int gpmc_probe_dt(struct platform_device *pdev) 1592{ 1593 int ret; 1594 struct device_node *child; 1595 const struct of_device_id *of_id = 1596 of_match_device(gpmc_dt_ids, &pdev->dev); 1597 1598 if (!of_id) 1599 return 0; 1600 1601 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", 1602 &gpmc_cs_num); 1603 if (ret < 0) { 1604 pr_err("%s: number of chip-selects not defined\n", __func__); 1605 return ret; 1606 } else if (gpmc_cs_num < 1) { 1607 pr_err("%s: all chip-selects are disabled\n", __func__); 1608 return -EINVAL; 1609 } else if (gpmc_cs_num > GPMC_CS_NUM) { 1610 pr_err("%s: number of supported chip-selects cannot be > %d\n", 1611 __func__, GPMC_CS_NUM); 1612 return -EINVAL; 1613 } 1614 1615 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", 1616 &gpmc_nr_waitpins); 1617 if (ret < 0) { 1618 pr_err("%s: number of wait pins not found!\n", __func__); 1619 return ret; 1620 } 1621 1622 for_each_available_child_of_node(pdev->dev.of_node, child) { 1623 1624 if (!child->name) 1625 continue; 1626 1627 if (of_node_cmp(child->name, "nand") == 0) 1628 ret = gpmc_probe_nand_child(pdev, child); 1629 else if (of_node_cmp(child->name, "onenand") == 0) 1630 ret = gpmc_probe_onenand_child(pdev, child); 1631 else if (of_node_cmp(child->name, "ethernet") == 0 || 1632 of_node_cmp(child->name, "nor") == 0 || 1633 of_node_cmp(child->name, "uart") == 0) 1634 ret = gpmc_probe_generic_child(pdev, child); 1635 1636 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n", 1637 __func__, child->full_name)) 1638 of_node_put(child); 1639 } 1640 1641 return 0; 1642} 1643#else 1644static int gpmc_probe_dt(struct platform_device *pdev) 1645{ 1646 return 0; 1647} 1648#endif 1649 1650static int gpmc_probe(struct platform_device *pdev) 1651{ 1652 int rc; 1653 u32 l; 1654 struct resource *res; 1655 1656 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1657 if (res == NULL) 1658 return -ENOENT; 1659 1660 phys_base = res->start; 1661 mem_size = resource_size(res); 1662 1663 gpmc_base = devm_ioremap_resource(&pdev->dev, res); 1664 if (IS_ERR(gpmc_base)) 1665 return PTR_ERR(gpmc_base); 1666 1667 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1668 if (res == NULL) 1669 dev_warn(&pdev->dev, "Failed to get resource: irq\n"); 1670 else 1671 gpmc_irq = res->start; 1672 1673 gpmc_l3_clk = clk_get(&pdev->dev, "fck"); 1674 if (IS_ERR(gpmc_l3_clk)) { 1675 dev_err(&pdev->dev, "error: clk_get\n"); 1676 gpmc_irq = 0; 1677 return PTR_ERR(gpmc_l3_clk); 1678 } 1679 1680 pm_runtime_enable(&pdev->dev); 1681 pm_runtime_get_sync(&pdev->dev); 1682 1683 gpmc_dev = &pdev->dev; 1684 1685 l = gpmc_read_reg(GPMC_REVISION); 1686 1687 /* 1688 * FIXME: Once device-tree migration is complete the below flags 1689 * should be populated based upon the device-tree compatible 1690 * string. For now just use the IP revision. OMAP3+ devices have 1691 * the wr_access and wr_data_mux_bus register fields. OMAP4+ 1692 * devices support the addr-addr-data multiplex protocol. 1693 * 1694 * GPMC IP revisions: 1695 * - OMAP24xx = 2.0 1696 * - OMAP3xxx = 5.0 1697 * - OMAP44xx/54xx/AM335x = 6.0 1698 */ 1699 if (GPMC_REVISION_MAJOR(l) > 0x4) 1700 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; 1701 if (GPMC_REVISION_MAJOR(l) > 0x5) 1702 gpmc_capability |= GPMC_HAS_MUX_AAD; 1703 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), 1704 GPMC_REVISION_MINOR(l)); 1705 1706 gpmc_mem_init(); 1707 1708 if (gpmc_setup_irq() < 0) 1709 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); 1710 1711 /* Now the GPMC is initialised, unreserve the chip-selects */ 1712 gpmc_cs_map = 0; 1713 1714 if (!pdev->dev.of_node) { 1715 gpmc_cs_num = GPMC_CS_NUM; 1716 gpmc_nr_waitpins = GPMC_NR_WAITPINS; 1717 } 1718 1719 rc = gpmc_probe_dt(pdev); 1720 if (rc < 0) { 1721 pm_runtime_put_sync(&pdev->dev); 1722 clk_put(gpmc_l3_clk); 1723 dev_err(gpmc_dev, "failed to probe DT parameters\n"); 1724 return rc; 1725 } 1726 1727 return 0; 1728} 1729 1730static int gpmc_remove(struct platform_device *pdev) 1731{ 1732 gpmc_free_irq(); 1733 gpmc_mem_exit(); 1734 pm_runtime_put_sync(&pdev->dev); 1735 pm_runtime_disable(&pdev->dev); 1736 gpmc_dev = NULL; 1737 return 0; 1738} 1739 1740#ifdef CONFIG_PM_SLEEP 1741static int gpmc_suspend(struct device *dev) 1742{ 1743 omap3_gpmc_save_context(); 1744 pm_runtime_put_sync(dev); 1745 return 0; 1746} 1747 1748static int gpmc_resume(struct device *dev) 1749{ 1750 pm_runtime_get_sync(dev); 1751 omap3_gpmc_restore_context(); 1752 return 0; 1753} 1754#endif 1755 1756static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); 1757 1758static struct platform_driver gpmc_driver = { 1759 .probe = gpmc_probe, 1760 .remove = gpmc_remove, 1761 .driver = { 1762 .name = DEVICE_NAME, 1763 .owner = THIS_MODULE, 1764 .of_match_table = of_match_ptr(gpmc_dt_ids), 1765 .pm = &gpmc_pm_ops, 1766 }, 1767}; 1768 1769static __init int gpmc_init(void) 1770{ 1771 return platform_driver_register(&gpmc_driver); 1772} 1773 1774static __exit void gpmc_exit(void) 1775{ 1776 platform_driver_unregister(&gpmc_driver); 1777 1778} 1779 1780omap_postcore_initcall(gpmc_init); 1781module_exit(gpmc_exit); 1782 1783static int __init omap_gpmc_init(void) 1784{ 1785 struct omap_hwmod *oh; 1786 struct platform_device *pdev; 1787 char *oh_name = "gpmc"; 1788 1789 /* 1790 * if the board boots up with a populated DT, do not 1791 * manually add the device from this initcall 1792 */ 1793 if (of_have_populated_dt()) 1794 return -ENODEV; 1795 1796 oh = omap_hwmod_lookup(oh_name); 1797 if (!oh) { 1798 pr_err("Could not look up %s\n", oh_name); 1799 return -ENODEV; 1800 } 1801 1802 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0); 1803 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 1804 1805 return PTR_RET(pdev); 1806} 1807omap_postcore_initcall(omap_gpmc_init); 1808 1809static irqreturn_t gpmc_handle_irq(int irq, void *dev) 1810{ 1811 int i; 1812 u32 regval; 1813 1814 regval = gpmc_read_reg(GPMC_IRQSTATUS); 1815 1816 if (!regval) 1817 return IRQ_NONE; 1818 1819 for (i = 0; i < GPMC_NR_IRQ; i++) 1820 if (regval & gpmc_client_irq[i].bitmask) 1821 generic_handle_irq(gpmc_client_irq[i].irq); 1822 1823 gpmc_write_reg(GPMC_IRQSTATUS, regval); 1824 1825 return IRQ_HANDLED; 1826} 1827 1828static struct omap3_gpmc_regs gpmc_context; 1829 1830void omap3_gpmc_save_context(void) 1831{ 1832 int i; 1833 1834 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); 1835 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); 1836 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); 1837 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); 1838 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); 1839 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); 1840 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); 1841 for (i = 0; i < gpmc_cs_num; i++) { 1842 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); 1843 if (gpmc_context.cs_context[i].is_valid) { 1844 gpmc_context.cs_context[i].config1 = 1845 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); 1846 gpmc_context.cs_context[i].config2 = 1847 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); 1848 gpmc_context.cs_context[i].config3 = 1849 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); 1850 gpmc_context.cs_context[i].config4 = 1851 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); 1852 gpmc_context.cs_context[i].config5 = 1853 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); 1854 gpmc_context.cs_context[i].config6 = 1855 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); 1856 gpmc_context.cs_context[i].config7 = 1857 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); 1858 } 1859 } 1860} 1861 1862void omap3_gpmc_restore_context(void) 1863{ 1864 int i; 1865 1866 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); 1867 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); 1868 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); 1869 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); 1870 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); 1871 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); 1872 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); 1873 for (i = 0; i < gpmc_cs_num; i++) { 1874 if (gpmc_context.cs_context[i].is_valid) { 1875 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, 1876 gpmc_context.cs_context[i].config1); 1877 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, 1878 gpmc_context.cs_context[i].config2); 1879 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, 1880 gpmc_context.cs_context[i].config3); 1881 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, 1882 gpmc_context.cs_context[i].config4); 1883 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, 1884 gpmc_context.cs_context[i].config5); 1885 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, 1886 gpmc_context.cs_context[i].config6); 1887 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 1888 gpmc_context.cs_context[i].config7); 1889 } 1890 } 1891} 1892