common.c revision 0a4b8c654615be5dd12d67e951446095bef8b565 
1/*
2 * arch/arm/mach-orion5x/common.c
3 *
4 * Core functions for Marvell Orion 5x SoCs
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2.  This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/serial_8250.h>
18#include <linux/mv643xx_i2c.h>
19#include <linux/ata_platform.h>
20#include <linux/delay.h>
21#include <linux/clk-provider.h>
22#include <net/dsa.h>
23#include <asm/page.h>
24#include <asm/setup.h>
25#include <asm/system_misc.h>
26#include <asm/timex.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/time.h>
30#include <mach/bridge-regs.h>
31#include <mach/hardware.h>
32#include <mach/orion5x.h>
33#include <plat/orion_nand.h>
34#include <plat/ehci-orion.h>
35#include <plat/time.h>
36#include <plat/common.h>
37#include <plat/addr-map.h>
38#include "common.h"
39
40/*****************************************************************************
41 * I/O Address Mapping
42 ****************************************************************************/
43static struct map_desc orion5x_io_desc[] __initdata = {
44	{
45		.virtual	= ORION5X_REGS_VIRT_BASE,
46		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
47		.length		= ORION5X_REGS_SIZE,
48		.type		= MT_DEVICE,
49	}, {
50		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
51		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
52		.length		= ORION5X_PCIE_WA_SIZE,
53		.type		= MT_DEVICE,
54	},
55};
56
57void __init orion5x_map_io(void)
58{
59	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
60}
61
62
63/*****************************************************************************
64 * CLK tree
65 ****************************************************************************/
66static struct clk *tclk;
67
68static void __init clk_init(void)
69{
70	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
71				       orion5x_tclk);
72
73	orion_clkdev_init(tclk);
74}
75
76/*****************************************************************************
77 * EHCI0
78 ****************************************************************************/
79void __init orion5x_ehci0_init(void)
80{
81	orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
82			EHCI_PHY_ORION);
83}
84
85
86/*****************************************************************************
87 * EHCI1
88 ****************************************************************************/
89void __init orion5x_ehci1_init(void)
90{
91	orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
92}
93
94
95/*****************************************************************************
96 * GE00
97 ****************************************************************************/
98void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
99{
100	orion_ge00_init(eth_data,
101			ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
102			IRQ_ORION5X_ETH_ERR);
103}
104
105
106/*****************************************************************************
107 * Ethernet switch
108 ****************************************************************************/
109void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
110{
111	orion_ge00_switch_init(d, irq);
112}
113
114
115/*****************************************************************************
116 * I2C
117 ****************************************************************************/
118void __init orion5x_i2c_init(void)
119{
120	orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
121
122}
123
124
125/*****************************************************************************
126 * SATA
127 ****************************************************************************/
128void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
129{
130	orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
131}
132
133
134/*****************************************************************************
135 * SPI
136 ****************************************************************************/
137void __init orion5x_spi_init()
138{
139	orion_spi_init(SPI_PHYS_BASE);
140}
141
142
143/*****************************************************************************
144 * UART0
145 ****************************************************************************/
146void __init orion5x_uart0_init(void)
147{
148	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
149			 IRQ_ORION5X_UART0, tclk);
150}
151
152/*****************************************************************************
153 * UART1
154 ****************************************************************************/
155void __init orion5x_uart1_init(void)
156{
157	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
158			 IRQ_ORION5X_UART1, tclk);
159}
160
161/*****************************************************************************
162 * XOR engine
163 ****************************************************************************/
164void __init orion5x_xor_init(void)
165{
166	orion_xor0_init(ORION5X_XOR_PHYS_BASE,
167			ORION5X_XOR_PHYS_BASE + 0x200,
168			IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
169}
170
171/*****************************************************************************
172 * Cryptographic Engines and Security Accelerator (CESA)
173 ****************************************************************************/
174static void __init orion5x_crypto_init(void)
175{
176	orion5x_setup_sram_win();
177	orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
178			  SZ_8K, IRQ_ORION5X_CESA);
179}
180
181/*****************************************************************************
182 * Watchdog
183 ****************************************************************************/
184void __init orion5x_wdt_init(void)
185{
186	orion_wdt_init();
187}
188
189
190/*****************************************************************************
191 * Time handling
192 ****************************************************************************/
193void __init orion5x_init_early(void)
194{
195	orion_time_set_base(TIMER_VIRT_BASE);
196}
197
198int orion5x_tclk;
199
200int __init orion5x_find_tclk(void)
201{
202	u32 dev, rev;
203
204	orion5x_pcie_id(&dev, &rev);
205	if (dev == MV88F6183_DEV_ID &&
206	    (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
207		return 133333333;
208
209	return 166666667;
210}
211
212static void __init orion5x_timer_init(void)
213{
214	orion5x_tclk = orion5x_find_tclk();
215
216	orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
217			IRQ_ORION5X_BRIDGE, orion5x_tclk);
218}
219
220struct sys_timer orion5x_timer = {
221	.init = orion5x_timer_init,
222};
223
224
225/*****************************************************************************
226 * General
227 ****************************************************************************/
228/*
229 * Identify device ID and rev from PCIe configuration header space '0'.
230 */
231static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
232{
233	orion5x_pcie_id(dev, rev);
234
235	if (*dev == MV88F5281_DEV_ID) {
236		if (*rev == MV88F5281_REV_D2) {
237			*dev_name = "MV88F5281-D2";
238		} else if (*rev == MV88F5281_REV_D1) {
239			*dev_name = "MV88F5281-D1";
240		} else if (*rev == MV88F5281_REV_D0) {
241			*dev_name = "MV88F5281-D0";
242		} else {
243			*dev_name = "MV88F5281-Rev-Unsupported";
244		}
245	} else if (*dev == MV88F5182_DEV_ID) {
246		if (*rev == MV88F5182_REV_A2) {
247			*dev_name = "MV88F5182-A2";
248		} else {
249			*dev_name = "MV88F5182-Rev-Unsupported";
250		}
251	} else if (*dev == MV88F5181_DEV_ID) {
252		if (*rev == MV88F5181_REV_B1) {
253			*dev_name = "MV88F5181-Rev-B1";
254		} else if (*rev == MV88F5181L_REV_A1) {
255			*dev_name = "MV88F5181L-Rev-A1";
256		} else {
257			*dev_name = "MV88F5181(L)-Rev-Unsupported";
258		}
259	} else if (*dev == MV88F6183_DEV_ID) {
260		if (*rev == MV88F6183_REV_B0) {
261			*dev_name = "MV88F6183-Rev-B0";
262		} else {
263			*dev_name = "MV88F6183-Rev-Unsupported";
264		}
265	} else {
266		*dev_name = "Device-Unknown";
267	}
268}
269
270void __init orion5x_init(void)
271{
272	char *dev_name;
273	u32 dev, rev;
274
275	orion5x_id(&dev, &rev, &dev_name);
276	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
277
278	/*
279	 * Setup Orion address map
280	 */
281	orion5x_setup_cpu_mbus_bridge();
282
283	/* Setup root of clk tree */
284	clk_init();
285
286	/*
287	 * Don't issue "Wait for Interrupt" instruction if we are
288	 * running on D0 5281 silicon.
289	 */
290	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
291		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
292		disable_hlt();
293	}
294
295	/*
296	 * The 5082/5181l/5182/6082/6082l/6183 have crypto
297	 * while 5180n/5181/5281 don't have crypto.
298	 */
299	if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
300	    dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
301		orion5x_crypto_init();
302
303	/*
304	 * Register watchdog driver
305	 */
306	orion5x_wdt_init();
307}
308
309void orion5x_restart(char mode, const char *cmd)
310{
311	/*
312	 * Enable and issue soft reset
313	 */
314	orion5x_setbits(RSTOUTn_MASK, (1 << 2));
315	orion5x_setbits(CPU_SOFT_RESET, 1);
316	mdelay(200);
317	orion5x_clrbits(CPU_SOFT_RESET, 1);
318}
319
320/*
321 * Many orion-based systems have buggy bootloader implementations.
322 * This is a common fixup for bogus memory tags.
323 */
324void __init tag_fixup_mem32(struct tag *t, char **from,
325			    struct meminfo *meminfo)
326{
327	for (; t->hdr.size; t = tag_next(t))
328		if (t->hdr.tag == ATAG_MEM &&
329		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
330		     t->u.mem.start & ~PAGE_MASK)) {
331			printk(KERN_WARNING
332			       "Clearing invalid memory bank %dKB@0x%08x\n",
333			       t->u.mem.size / 1024, t->u.mem.start);
334			t->hdr.tag = 0;
335		}
336}
337