common.c revision db33f4de9952af112b0d4f2436ce931ae632aba0 
1/*
2 * arch/arm/mach-orion5x/common.c
3 *
4 * Core functions for Marvell Orion 5x SoCs
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2.  This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/serial_8250.h>
18#include <linux/mv643xx_i2c.h>
19#include <linux/ata_platform.h>
20#include <net/dsa.h>
21#include <asm/page.h>
22#include <asm/setup.h>
23#include <asm/timex.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/time.h>
27#include <mach/bridge-regs.h>
28#include <mach/hardware.h>
29#include <mach/orion5x.h>
30#include <plat/orion_nand.h>
31#include <plat/time.h>
32#include <plat/common.h>
33#include <plat/addr-map.h>
34#include "common.h"
35
36/*****************************************************************************
37 * I/O Address Mapping
38 ****************************************************************************/
39static struct map_desc orion5x_io_desc[] __initdata = {
40	{
41		.virtual	= ORION5X_REGS_VIRT_BASE,
42		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
43		.length		= ORION5X_REGS_SIZE,
44		.type		= MT_DEVICE,
45	}, {
46		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
47		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
48		.length		= ORION5X_PCIE_IO_SIZE,
49		.type		= MT_DEVICE,
50	}, {
51		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
52		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
53		.length		= ORION5X_PCI_IO_SIZE,
54		.type		= MT_DEVICE,
55	}, {
56		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
57		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
58		.length		= ORION5X_PCIE_WA_SIZE,
59		.type		= MT_DEVICE,
60	},
61};
62
63void __init orion5x_map_io(void)
64{
65	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
66}
67
68
69/*****************************************************************************
70 * EHCI0
71 ****************************************************************************/
72void __init orion5x_ehci0_init(void)
73{
74	orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
75}
76
77
78/*****************************************************************************
79 * EHCI1
80 ****************************************************************************/
81void __init orion5x_ehci1_init(void)
82{
83	orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
84}
85
86
87/*****************************************************************************
88 * GE00
89 ****************************************************************************/
90void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
91{
92	orion_ge00_init(eth_data,
93			ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
94			IRQ_ORION5X_ETH_ERR, orion5x_tclk);
95}
96
97
98/*****************************************************************************
99 * Ethernet switch
100 ****************************************************************************/
101void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
102{
103	orion_ge00_switch_init(d, irq);
104}
105
106
107/*****************************************************************************
108 * I2C
109 ****************************************************************************/
110void __init orion5x_i2c_init(void)
111{
112	orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
113
114}
115
116
117/*****************************************************************************
118 * SATA
119 ****************************************************************************/
120void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
121{
122	orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
123}
124
125
126/*****************************************************************************
127 * SPI
128 ****************************************************************************/
129void __init orion5x_spi_init()
130{
131	orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
132}
133
134
135/*****************************************************************************
136 * UART0
137 ****************************************************************************/
138void __init orion5x_uart0_init(void)
139{
140	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
141			 IRQ_ORION5X_UART0, orion5x_tclk);
142}
143
144/*****************************************************************************
145 * UART1
146 ****************************************************************************/
147void __init orion5x_uart1_init(void)
148{
149	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
150			 IRQ_ORION5X_UART1, orion5x_tclk);
151}
152
153/*****************************************************************************
154 * XOR engine
155 ****************************************************************************/
156void __init orion5x_xor_init(void)
157{
158	orion_xor0_init(ORION5X_XOR_PHYS_BASE,
159			ORION5X_XOR_PHYS_BASE + 0x200,
160			IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
161}
162
163/*****************************************************************************
164 * Cryptographic Engines and Security Accelerator (CESA)
165 ****************************************************************************/
166static void __init orion5x_crypto_init(void)
167{
168	orion5x_setup_sram_win();
169	orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
170			  SZ_8K, IRQ_ORION5X_CESA);
171}
172
173/*****************************************************************************
174 * Watchdog
175 ****************************************************************************/
176void __init orion5x_wdt_init(void)
177{
178	orion_wdt_init(orion5x_tclk);
179}
180
181
182/*****************************************************************************
183 * Time handling
184 ****************************************************************************/
185void __init orion5x_init_early(void)
186{
187	orion_time_set_base(TIMER_VIRT_BASE);
188}
189
190int orion5x_tclk;
191
192int __init orion5x_find_tclk(void)
193{
194	u32 dev, rev;
195
196	orion5x_pcie_id(&dev, &rev);
197	if (dev == MV88F6183_DEV_ID &&
198	    (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
199		return 133333333;
200
201	return 166666667;
202}
203
204static void orion5x_timer_init(void)
205{
206	orion5x_tclk = orion5x_find_tclk();
207
208	orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
209			IRQ_ORION5X_BRIDGE, orion5x_tclk);
210}
211
212struct sys_timer orion5x_timer = {
213	.init = orion5x_timer_init,
214};
215
216
217/*****************************************************************************
218 * General
219 ****************************************************************************/
220/*
221 * Identify device ID and rev from PCIe configuration header space '0'.
222 */
223static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
224{
225	orion5x_pcie_id(dev, rev);
226
227	if (*dev == MV88F5281_DEV_ID) {
228		if (*rev == MV88F5281_REV_D2) {
229			*dev_name = "MV88F5281-D2";
230		} else if (*rev == MV88F5281_REV_D1) {
231			*dev_name = "MV88F5281-D1";
232		} else if (*rev == MV88F5281_REV_D0) {
233			*dev_name = "MV88F5281-D0";
234		} else {
235			*dev_name = "MV88F5281-Rev-Unsupported";
236		}
237	} else if (*dev == MV88F5182_DEV_ID) {
238		if (*rev == MV88F5182_REV_A2) {
239			*dev_name = "MV88F5182-A2";
240		} else {
241			*dev_name = "MV88F5182-Rev-Unsupported";
242		}
243	} else if (*dev == MV88F5181_DEV_ID) {
244		if (*rev == MV88F5181_REV_B1) {
245			*dev_name = "MV88F5181-Rev-B1";
246		} else if (*rev == MV88F5181L_REV_A1) {
247			*dev_name = "MV88F5181L-Rev-A1";
248		} else {
249			*dev_name = "MV88F5181(L)-Rev-Unsupported";
250		}
251	} else if (*dev == MV88F6183_DEV_ID) {
252		if (*rev == MV88F6183_REV_B0) {
253			*dev_name = "MV88F6183-Rev-B0";
254		} else {
255			*dev_name = "MV88F6183-Rev-Unsupported";
256		}
257	} else {
258		*dev_name = "Device-Unknown";
259	}
260}
261
262void __init orion5x_init(void)
263{
264	char *dev_name;
265	u32 dev, rev;
266
267	orion5x_id(&dev, &rev, &dev_name);
268	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
269
270	/*
271	 * Setup Orion address map
272	 */
273	orion5x_setup_cpu_mbus_bridge();
274
275	/*
276	 * Don't issue "Wait for Interrupt" instruction if we are
277	 * running on D0 5281 silicon.
278	 */
279	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
280		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
281		disable_hlt();
282	}
283
284	/*
285	 * The 5082/5181l/5182/6082/6082l/6183 have crypto
286	 * while 5180n/5181/5281 don't have crypto.
287	 */
288	if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
289	    dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
290		orion5x_crypto_init();
291
292	/*
293	 * Register watchdog driver
294	 */
295	orion5x_wdt_init();
296}
297
298/*
299 * Many orion-based systems have buggy bootloader implementations.
300 * This is a common fixup for bogus memory tags.
301 */
302void __init tag_fixup_mem32(struct tag *t, char **from,
303			    struct meminfo *meminfo)
304{
305	for (; t->hdr.size; t = tag_next(t))
306		if (t->hdr.tag == ATAG_MEM &&
307		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
308		     t->u.mem.start & ~PAGE_MASK)) {
309			printk(KERN_WARNING
310			       "Clearing invalid memory bank %dKB@0x%08x\n",
311			       t->u.mem.size / 1024, t->u.mem.start);
312			t->hdr.tag = 0;
313		}
314}
315