11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2a09e64fbc0094e3073dbb09c3b4bfe4ab669244bRussell King * arch/arm/mach-pxa/include/mach/irqs.h 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Author: Nicolas Pitre 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Created: Jun 15, 2001 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright: MontaVista Software Inc. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1235f53aafb60ebc3a26e5508e0e87bfc88c703654Russell King#ifndef __ASM_MACH_IRQS_H 1335f53aafb60ebc3a26e5508e0e87bfc88c703654Russell King#define __ASM_MACH_IRQS_H 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1557a7a62eb65b35f51814382b0841ff99be242880Marc Zyngier#ifdef CONFIG_PXA_HAVE_ISA_IRQS 1657a7a62eb65b35f51814382b0841ff99be242880Marc Zyngier#define PXA_ISA_IRQ(x) (x) 1757a7a62eb65b35f51814382b0841ff99be242880Marc Zyngier#define PXA_ISA_IRQ_NUM (16) 1857a7a62eb65b35f51814382b0841ff99be242880Marc Zyngier#else 1957a7a62eb65b35f51814382b0841ff99be242880Marc Zyngier#define PXA_ISA_IRQ_NUM (0) 2057a7a62eb65b35f51814382b0841ff99be242880Marc Zyngier#endif 2157a7a62eb65b35f51814382b0841ff99be242880Marc Zyngier 2257a7a62eb65b35f51814382b0841ff99be242880Marc Zyngier#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x)) 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ 26bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */ 27bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */ 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ 29bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */ 30bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */ 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */ 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_USB PXA_IRQ(11) /* USB Service */ 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ 39bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */ 40bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */ 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */ 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */ 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ 49bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */ 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */ 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */ 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */ 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */ 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */ 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */ 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */ 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ 65a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ 669db95cb6c430b3d9b8abbd5870e0d1e69b884ba0Haojian Zhuang#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ 67a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ 68bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ 69a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ 70bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */ 71bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */ 72a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ 73bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */ 74a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ 75a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ 76a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ 77a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */ 78a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ 79a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ 80a8929198563c48544cc0cee0565be7d6629a2a4eeric miao#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ 81a8929198563c48544cc0cee0565be7d6629a2a4eeric miao 829db95cb6c430b3d9b8abbd5870e0d1e69b884ba0Haojian Zhuang#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ 839db95cb6c430b3d9b8abbd5870e0d1e69b884ba0Haojian Zhuang#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ 84bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */ 85bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */ 86bb71bdd31b48efa2b9834f1a47eb5f657e3c217cHaojian Zhuang#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */ 879db95cb6c430b3d9b8abbd5870e0d1e69b884ba0Haojian Zhuang#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ 889db95cb6c430b3d9b8abbd5870e0d1e69b884ba0Haojian Zhuang 899db95cb6c430b3d9b8abbd5870e0d1e69b884ba0Haojian Zhuang#define PXA_GPIO_IRQ_BASE PXA_IRQ(96) 901a8d5fab16ed9401d99d0c463b5e57bdd744c8d3Haojian Zhuang#define PXA_NR_BUILTIN_GPIO (192) 9187c49e20579c933d531a376596875b8fd5dcb04fHaojian Zhuang#define PXA_GPIO_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 94a01bd58449088b63da45ab5f2c7921893eb7d143Philipp Zabel * The following interrupts are for board specific purposes. Since 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the kernel can only run on one machine at a time, we can re-use 966ac6b817f3f4c23c5febd960d8deb343e13af5f3Haojian Zhuang * these. 976ac6b817f3f4c23c5febd960d8deb343e13af5f3Haojian Zhuang * By default, no board IRQ is reserved. It should be finished in 986ac6b817f3f4c23c5febd960d8deb343e13af5f3Haojian Zhuang * custom board since sparse IRQ is already enabled. 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1001a8d5fab16ed9401d99d0c463b5e57bdd744c8d3Haojian Zhuang#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO) 101a01bd58449088b63da45ab5f2c7921893eb7d143Philipp Zabel 1024e611091f859906c28921cf8d3c75a848fd249bdRob Herring#define PXA_NR_IRQS (IRQ_BOARD_START) 10335f53aafb60ebc3a26e5508e0e87bfc88c703654Russell King 1045d284e353eb11ab2e8b1c5671ba06489b0bd1e0cEric Miao#ifndef __ASSEMBLY__ 1055d284e353eb11ab2e8b1c5671ba06489b0bd1e0cEric Miaostruct irq_data; 106a551e4f787220459c6e78668a15cbe01f1ac7637Eric Miaostruct pt_regs; 1075d284e353eb11ab2e8b1c5671ba06489b0bd1e0cEric Miao 1085d284e353eb11ab2e8b1c5671ba06489b0bd1e0cEric Miaovoid pxa_mask_irq(struct irq_data *); 1095d284e353eb11ab2e8b1c5671ba06489b0bd1e0cEric Miaovoid pxa_unmask_irq(struct irq_data *); 110a551e4f787220459c6e78668a15cbe01f1ac7637Eric Miaovoid icip_handle_irq(struct pt_regs *); 111a551e4f787220459c6e78668a15cbe01f1ac7637Eric Miaovoid ichp_handle_irq(struct pt_regs *); 112ca0e687c8ea5a7ae4b1c7a735f797f95ed953f9aEric Miao 113ca0e687c8ea5a7ae4b1c7a735f797f95ed953f9aEric Miaovoid pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int)); 1145d284e353eb11ab2e8b1c5671ba06489b0bd1e0cEric Miao#endif 1155d284e353eb11ab2e8b1c5671ba06489b0bd1e0cEric Miao 11635f53aafb60ebc3a26e5508e0e87bfc88c703654Russell King#endif /* __ASM_MACH_IRQS_H */ 117