1a09e64fbc0094e3073dbb09c3b4bfe4ab669244bRussell King/* arch/arm/mach-s3c2410/include/mach/dma.h 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3ccae941ee2de58b9391f4e166b1bad33fcbfc119Ben Dooks * Copyright (C) 2003-2006 Simtec Electronics 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ben Dooks <ben@simtec.co.uk> 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 644dc94045f6ddbc07db3e0eb3448c2efc13ac2cfBen Dooks * Samsung S3C24XX DMA support 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds*/ 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef __ASM_ARCH_DMA_H 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define __ASM_ARCH_DMA_H __FILE__ 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 164a858cfc9af87cc60b3113c3b7b377a4305eac6aKay Sievers#include <linux/device.h> 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks/* We use `virtual` dma channels to hide the fact we have only a limited 2125985edcedea6396277003854657b5f3cb31a628Lucas De Marchi * number of DMA channels, and not of all of them (dependent on the device) 22505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks * can be attached to any DMA source. We therefore let the DMA core handle 23505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks * the allocation of hardware channels to clients. 24505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks*/ 25505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks 26505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooksenum dma_ch { 27e1267371eacf2cbcf580e41f9e64a986cdaf5c1dHeiko Stuebner DMACH_XD0 = 0, 28505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_XD1, 29505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_SDI, 30505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_SPI0, 31505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_SPI1, 32505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_UART0, 33505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_UART1, 34505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_UART2, 35505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_TIMER, 36505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_I2S_IN, 37505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_I2S_OUT, 38505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_PCM_IN, 39505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_PCM_OUT, 40505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_MIC_IN, 41505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_USB_EP1, 42505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_USB_EP2, 43505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_USB_EP3, 44505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_USB_EP4, 4534348012d6b43eca5e241fe97381420d5758866cBen Dooks DMACH_UART0_SRC2, /* s3c2412 second uart sources */ 4634348012d6b43eca5e241fe97381420d5758866cBen Dooks DMACH_UART1_SRC2, 4734348012d6b43eca5e241fe97381420d5758866cBen Dooks DMACH_UART2_SRC2, 4815e4db7b8054ac171de946b9511655446dd29b8fBen Dooks DMACH_UART3, /* s3c2443 has extra uart */ 4915e4db7b8054ac171de946b9511655446dd29b8fBen Dooks DMACH_UART3_SRC2, 50ad6c1d43964dcba57bfe20b7185af5a71f94a1b7Heiko Stuebner DMACH_SPI0_TX, /* s3c2443/2416/2450 hsspi0 */ 51ad6c1d43964dcba57bfe20b7185af5a71f94a1b7Heiko Stuebner DMACH_SPI0_RX, /* s3c2443/2416/2450 hsspi0 */ 52ad6c1d43964dcba57bfe20b7185af5a71f94a1b7Heiko Stuebner DMACH_SPI1_TX, /* s3c2443/2450 hsspi1 */ 53ad6c1d43964dcba57bfe20b7185af5a71f94a1b7Heiko Stuebner DMACH_SPI1_RX, /* s3c2443/2450 hsspi1 */ 54505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks DMACH_MAX, /* the end entry */ 55505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks}; 56505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks 57344b4c48887a443f7478fc7047d1397b20821ed3Boojin Kimstatic inline bool samsung_dma_has_circular(void) 58344b4c48887a443f7478fc7047d1397b20821ed3Boojin Kim{ 59344b4c48887a443f7478fc7047d1397b20821ed3Boojin Kim return false; 60344b4c48887a443f7478fc7047d1397b20821ed3Boojin Kim} 61344b4c48887a443f7478fc7047d1397b20821ed3Boojin Kim 62c4e1662550a3bd23df7cff4611eff67ba2afe078Boojin Kimstatic inline bool samsung_dma_is_dmadev(void) 63c4e1662550a3bd23df7cff4611eff67ba2afe078Boojin Kim{ 64c4e1662550a3bd23df7cff4611eff67ba2afe078Boojin Kim return false; 65c4e1662550a3bd23df7cff4611eff67ba2afe078Boojin Kim} 66c4e1662550a3bd23df7cff4611eff67ba2afe078Boojin Kim 67c4e1662550a3bd23df7cff4611eff67ba2afe078Boojin Kim#include <plat/dma.h> 68c4e1662550a3bd23df7cff4611eff67ba2afe078Boojin Kim 69505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ 70505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* we have 4 dma channels */ 727cfdee9f6791fe9ec288e75ee746790ebf3b6c3bYauhen Kharuzhy#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416) 7397c1b145231730e62dd71921ec653315a1da3aadBen Dooks#define S3C_DMA_CHANNELS (4) 7415e4db7b8054ac171de946b9511655446dd29b8fBen Dooks#else 7597c1b145231730e62dd71921ec653315a1da3aadBen Dooks#define S3C_DMA_CHANNELS (6) 7615e4db7b8054ac171de946b9511655446dd29b8fBen Dooks#endif 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* types */ 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 80f105a7dfc5e81c28dd23ebf2328e42972e2cf240Ben Dooksenum s3c2410_dma_state { 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds S3C2410_DMA_IDLE, 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds S3C2410_DMA_RUNNING, 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds S3C2410_DMA_PAUSED 84f105a7dfc5e81c28dd23ebf2328e42972e2cf240Ben Dooks}; 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 86f105a7dfc5e81c28dd23ebf2328e42972e2cf240Ben Dooks/* enum s3c2410_dma_loadst 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This represents the state of the DMA engine, wrt to the loaded / running 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * transfers. Since we don't have any way of knowing exactly the state of 9048fc7f7e787dd65ffe88521bce31f4062ba273ebAdam Buchbinder * the DMA transfers, we need to know the state to make decisions on whether 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * we can 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * S3C2410_DMA_NONE 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * There are no buffers loaded (the channel should be inactive) 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * S3C2410_DMA_1LOADED 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * There is one buffer loaded, however it has not been confirmed to be 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * loaded by the DMA engine. This may be because the channel is not 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * yet running, or the DMA driver decided that it was too costly to 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * sit and wait for it to happen. 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * S3C2410_DMA_1RUNNING 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The buffer has been confirmed running, and not finisged 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * S3C2410_DMA_1LOADED_1RUNNING 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * There is a buffer waiting to be loaded by the DMA engine, and one 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * currently running. 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds*/ 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 114f105a7dfc5e81c28dd23ebf2328e42972e2cf240Ben Dooksenum s3c2410_dma_loadst { 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds S3C2410_DMALOAD_NONE, 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds S3C2410_DMALOAD_1LOADED, 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds S3C2410_DMALOAD_1RUNNING, 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds S3C2410_DMALOAD_1LOADED_1RUNNING, 119f105a7dfc5e81c28dd23ebf2328e42972e2cf240Ben Dooks}; 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* flags */ 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * waiting for reloads */ 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 128e3d8024891dbfec6cf36c9b76177650f48118462Ben Dooks#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */ 129e3d8024891dbfec6cf36c9b76177650f48118462Ben Dooks 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* dma buffer */ 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 132c133c290118bfc99cd7a23b5a00b5252d2be90c8Ben Dooksstruct s3c2410_dma_buf; 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 134c133c290118bfc99cd7a23b5a00b5252d2be90c8Ben Dooks/* s3c2410_dma_buf 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * internally used buffer structure to describe a queued or running 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * buffer. 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds*/ 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 140f105a7dfc5e81c28dd23ebf2328e42972e2cf240Ben Dooksstruct s3c2410_dma_buf { 14157bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks struct s3c2410_dma_buf *next; 14257bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks int magic; /* magic */ 14357bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks int size; /* buffer size in bytes */ 14457bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks dma_addr_t data; /* start of DMA data */ 14557bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks dma_addr_t ptr; /* where the DMA got to [1] */ 14657bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks void *id; /* client's id */ 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* [1] is this updated for both recv/send modes? */ 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 151f105a7dfc5e81c28dd23ebf2328e42972e2cf240Ben Dooksstruct s3c2410_dma_stats { 15257bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned long loads; 15357bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned long timeout_longest; 15457bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned long timeout_shortest; 15557bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned long timeout_avg; 15657bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned long timeout_failed; 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 159505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooksstruct s3c2410_dma_map; 160505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks 161f105a7dfc5e81c28dd23ebf2328e42972e2cf240Ben Dooks/* struct s3c2410_dma_chan 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * full state information for each DMA channel 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds*/ 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 166f105a7dfc5e81c28dd23ebf2328e42972e2cf240Ben Dooksstruct s3c2410_dma_chan { 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* channel state flags and information */ 16857bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned char number; /* number of this dma channel */ 16957bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned char in_use; /* channel allocated */ 17057bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned char irq_claimed; /* irq claimed for channel */ 17157bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned char irq_enabled; /* irq enabled for channel */ 17257bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned char xfer_unit; /* size of an transfer */ 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* channel state */ 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17657bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks enum s3c2410_dma_state state; 17757bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks enum s3c2410_dma_loadst load_state; 17857bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks struct s3c2410_dma_client *client; 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* channel configuration */ 18151ddf31da16b1ab9da861eafedad6d263faf4388Boojin Kim enum dma_data_direction source; 1828970ef47d56fd3db28ee798b9d400caf08abd924Ben Dooks enum dma_ch req_ch; 18357bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned long dev_addr; 18457bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned long load_timeout; 18557bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned int flags; /* channel flags */ 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 187505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks struct s3c24xx_dma_map *map; /* channel hw maps */ 188505788cccbb96cd496b646594c8a5fcdc26bc2d9Ben Dooks 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* channel's hardware position and configuration */ 19057bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks void __iomem *regs; /* channels registers */ 19157bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks void __iomem *addr_reg; /* data address register */ 19257bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned int irq; /* channel irq */ 19357bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks unsigned long dcon; /* default value of DCON */ 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* driver handles */ 19657bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ 19757bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks s3c2410_dma_opfn_t op_fn; /* channel op callback */ 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* stats gathering */ 20057bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks struct s3c2410_dma_stats *stats; 20157bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks struct s3c2410_dma_stats stats_store; 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* buffer list and information */ 20457bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks struct s3c2410_dma_buf *curr; /* current dma buffer */ 20557bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks struct s3c2410_dma_buf *next; /* next buffer to load */ 20657bcdafcb1e0782e7ae13471d9223c69e3a6cba2Ben Dooks struct s3c2410_dma_buf *end; /* end of queue */ 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* system device */ 2094a858cfc9af87cc60b3113c3b7b377a4305eac6aKay Sievers struct device dev; 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldstypedef unsigned long dma_device_t; 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* __ASM_ARCH_DMA_H */ 215