platsmp.c revision 7fa22bd5460bb2021729fa5a1012c60b9b3a56e2 
1/*
2 *  linux/arch/arm/mach-tegra/platsmp.c
3 *
4 *  Copyright (C) 2002 ARM Ltd.
5 *  All Rights Reserved
6 *
7 *  Copyright (C) 2009 Palm
8 *  All Rights Reserved
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/jiffies.h>
19#include <linux/smp.h>
20#include <linux/io.h>
21
22#include <asm/cacheflush.h>
23#include <asm/hardware/gic.h>
24#include <mach/hardware.h>
25#include <asm/mach-types.h>
26#include <asm/smp_scu.h>
27
28#include <mach/iomap.h>
29
30extern void tegra_secondary_startup(void);
31
32static DEFINE_SPINLOCK(boot_lock);
33static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
34
35#define EVP_CPU_RESET_VECTOR \
36	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
37#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
38	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
39#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
40	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
41
42void __cpuinit platform_secondary_init(unsigned int cpu)
43{
44	/*
45	 * if any interrupts are already enabled for the primary
46	 * core (e.g. timer irq), then they will not have been enabled
47	 * for us: do so
48	 */
49	gic_secondary_init(0);
50
51	/*
52	 * Synchronise with the boot thread.
53	 */
54	spin_lock(&boot_lock);
55	spin_unlock(&boot_lock);
56}
57
58int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
59{
60	unsigned long old_boot_vector;
61	unsigned long boot_vector;
62	unsigned long timeout;
63	u32 reg;
64
65	/*
66	 * set synchronisation state between this boot processor
67	 * and the secondary one
68	 */
69	spin_lock(&boot_lock);
70
71
72	/* set the reset vector to point to the secondary_startup routine */
73
74	boot_vector = virt_to_phys(tegra_secondary_startup);
75	old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
76	writel(boot_vector, EVP_CPU_RESET_VECTOR);
77
78	/* enable cpu clock on cpu1 */
79	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
80	writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
81
82	reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
83	writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
84
85	smp_wmb();
86	flush_cache_all();
87
88	/* unhalt the cpu */
89	writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
90
91	timeout = jiffies + (1 * HZ);
92	while (time_before(jiffies, timeout)) {
93		if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
94			break;
95		udelay(10);
96	}
97
98	/* put the old boot vector back */
99	writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
100
101	/*
102	 * now the secondary core is starting up let it run its
103	 * calibrations, then wait for it to finish
104	 */
105	spin_unlock(&boot_lock);
106
107	return 0;
108}
109
110/*
111 * Initialise the CPU possible map early - this describes the CPUs
112 * which may be present or become present in the system.
113 */
114void __init smp_init_cpus(void)
115{
116	unsigned int i, ncores = scu_get_core_count(scu_base);
117
118	if (ncores > NR_CPUS) {
119		printk(KERN_ERR "Tegra: no. of cores (%u) greater than configured (%u), clipping\n",
120			ncores, NR_CPUS);
121		ncores = NR_CPUS;
122	}
123
124	for (i = 0; i < ncores; i++)
125		cpu_set(i, cpu_possible_map);
126
127	set_smp_cross_call(gic_raise_softirq);
128}
129
130void __init platform_smp_prepare_cpus(unsigned int max_cpus)
131{
132
133	scu_enable(scu_base);
134}
135