cpu-db8500.c revision 1d5cc604f42ff1acdec0407247b2f720135ba0c2
1/* 2 * Copyright (C) 2008-2009 ST-Ericsson SA 3 * 4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2, as 8 * published by the Free Software Foundation. 9 * 10 */ 11#include <linux/types.h> 12#include <linux/init.h> 13#include <linux/device.h> 14#include <linux/amba/bus.h> 15#include <linux/interrupt.h> 16#include <linux/irq.h> 17#include <linux/platform_device.h> 18#include <linux/io.h> 19#include <linux/mfd/abx500/ab8500.h> 20#include <linux/mfd/dbx500-prcmu.h> 21#include <linux/of.h> 22#include <linux/of_platform.h> 23#include <linux/regulator/machine.h> 24#include <linux/platform_data/pinctrl-nomadik.h> 25#include <linux/random.h> 26 27#include <asm/pmu.h> 28#include <asm/mach/map.h> 29#include <asm/mach/arch.h> 30 31#include <mach/hardware.h> 32#include <mach/setup.h> 33#include <mach/devices.h> 34#include <mach/db8500-regs.h> 35#include <mach/irqs.h> 36 37#include "devices-db8500.h" 38#include "ste-dma40-db8500.h" 39#include "board-mop500.h" 40 41/* minimum static i/o mapping required to boot U8500 platforms */ 42static struct map_desc u8500_uart_io_desc[] __initdata = { 43 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), 44 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), 45}; 46/* U8500 and U9540 common io_desc */ 47static struct map_desc u8500_common_io_desc[] __initdata = { 48 /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ 49 __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), 50 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), 51 __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), 52 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 53 __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), 54 55 __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), 56 __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), 57 __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), 58 __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), 59 __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), 60 61 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), 62 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 63 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 64 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 65}; 66 67/* U8500 IO map specific description */ 68static struct map_desc u8500_io_desc[] __initdata = { 69 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), 70 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 71 72}; 73 74/* U9540 IO map specific description */ 75static struct map_desc u9540_io_desc[] __initdata = { 76 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K), 77 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K), 78}; 79 80void __init u8500_map_io(void) 81{ 82 /* 83 * Map the UARTs early so that the DEBUG_LL stuff continues to work. 84 */ 85 iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); 86 87 ux500_map_io(); 88 89 iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc)); 90 91 if (cpu_is_ux540_family()) 92 iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc)); 93 else 94 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 95 96 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); 97} 98 99static struct resource db8500_pmu_resources[] = { 100 [0] = { 101 .start = IRQ_DB8500_PMU, 102 .end = IRQ_DB8500_PMU, 103 .flags = IORESOURCE_IRQ, 104 }, 105}; 106 107/* 108 * The PMU IRQ lines of two cores are wired together into a single interrupt. 109 * Bounce the interrupt to the other core if it's not ours. 110 */ 111static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) 112{ 113 irqreturn_t ret = handler(irq, dev); 114 int other = !smp_processor_id(); 115 116 if (ret == IRQ_NONE && cpu_online(other)) 117 irq_set_affinity(irq, cpumask_of(other)); 118 119 /* 120 * We should be able to get away with the amount of IRQ_NONEs we give, 121 * while still having the spurious IRQ detection code kick in if the 122 * interrupt really starts hitting spuriously. 123 */ 124 return ret; 125} 126 127struct arm_pmu_platdata db8500_pmu_platdata = { 128 .handle_irq = db8500_pmu_handler, 129}; 130 131static struct platform_device db8500_pmu_device = { 132 .name = "arm-pmu", 133 .id = -1, 134 .num_resources = ARRAY_SIZE(db8500_pmu_resources), 135 .resource = db8500_pmu_resources, 136 .dev.platform_data = &db8500_pmu_platdata, 137}; 138 139static struct platform_device db8500_prcmu_device = { 140 .name = "db8500-prcmu", 141}; 142 143static struct platform_device *platform_devs[] __initdata = { 144 &u8500_dma40_device, 145 &db8500_pmu_device, 146 &db8500_prcmu_device, 147}; 148 149static resource_size_t __initdata db8500_gpio_base[] = { 150 U8500_GPIOBANK0_BASE, 151 U8500_GPIOBANK1_BASE, 152 U8500_GPIOBANK2_BASE, 153 U8500_GPIOBANK3_BASE, 154 U8500_GPIOBANK4_BASE, 155 U8500_GPIOBANK5_BASE, 156 U8500_GPIOBANK6_BASE, 157 U8500_GPIOBANK7_BASE, 158 U8500_GPIOBANK8_BASE, 159}; 160 161static void __init db8500_add_gpios(struct device *parent) 162{ 163 struct nmk_gpio_platform_data pdata = { 164 .supports_sleepmode = true, 165 }; 166 167 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), 168 IRQ_DB8500_GPIO0, &pdata); 169 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE); 170} 171 172static int usb_db8500_rx_dma_cfg[] = { 173 DB8500_DMA_DEV38_USB_OTG_IEP_1_9, 174 DB8500_DMA_DEV37_USB_OTG_IEP_2_10, 175 DB8500_DMA_DEV36_USB_OTG_IEP_3_11, 176 DB8500_DMA_DEV19_USB_OTG_IEP_4_12, 177 DB8500_DMA_DEV18_USB_OTG_IEP_5_13, 178 DB8500_DMA_DEV17_USB_OTG_IEP_6_14, 179 DB8500_DMA_DEV16_USB_OTG_IEP_7_15, 180 DB8500_DMA_DEV39_USB_OTG_IEP_8 181}; 182 183static int usb_db8500_tx_dma_cfg[] = { 184 DB8500_DMA_DEV38_USB_OTG_OEP_1_9, 185 DB8500_DMA_DEV37_USB_OTG_OEP_2_10, 186 DB8500_DMA_DEV36_USB_OTG_OEP_3_11, 187 DB8500_DMA_DEV19_USB_OTG_OEP_4_12, 188 DB8500_DMA_DEV18_USB_OTG_OEP_5_13, 189 DB8500_DMA_DEV17_USB_OTG_OEP_6_14, 190 DB8500_DMA_DEV16_USB_OTG_OEP_7_15, 191 DB8500_DMA_DEV39_USB_OTG_OEP_8 192}; 193 194static const char *db8500_read_soc_id(void) 195{ 196 void __iomem *uid = __io_address(U8500_BB_UID_BASE); 197 198 /* Throw these device-specific numbers into the entropy pool */ 199 add_device_randomness(uid, 0x14); 200 return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x", 201 readl((u32 *)uid+1), 202 readl((u32 *)uid+1), readl((u32 *)uid+2), 203 readl((u32 *)uid+3), readl((u32 *)uid+4)); 204} 205 206static struct device * __init db8500_soc_device_init(void) 207{ 208 const char *soc_id = db8500_read_soc_id(); 209 210 return ux500_soc_device_init(soc_id); 211} 212 213/* 214 * This function is called from the board init 215 */ 216struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) 217{ 218 struct device *parent; 219 int i; 220 221 parent = db8500_soc_device_init(); 222 223 db8500_add_rtc(parent); 224 db8500_add_gpios(parent); 225 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 226 227 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) 228 platform_devs[i]->dev.parent = parent; 229 230 db8500_prcmu_device.dev.platform_data = ab8500; 231 232 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 233 234 return parent; 235} 236 237#ifdef CONFIG_MACH_UX500_DT 238 239/* TODO: Once all pieces are DT:ed, remove completely. */ 240static struct device * __init u8500_of_init_devices(void) 241{ 242 struct device *parent = db8500_soc_device_init(); 243 244 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 245 246 u8500_dma40_device.dev.parent = parent; 247 248 /* 249 * Devices to be DT:ed: 250 * u8500_dma40_device = todo 251 * db8500_pmu_device = done 252 * db8500_prcmu_device = done 253 */ 254 platform_device_register(&u8500_dma40_device); 255 256 return parent; 257} 258 259static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { 260 /* Requires call-back bindings. */ 261 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), 262 /* Requires DMA bindings. */ 263 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), 264 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), 265 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), 266 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 267 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), 268 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), 269 OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data), 270 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), 271 /* Requires clock name bindings. */ 272 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), 273 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), 274 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL), 275 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL), 276 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL), 277 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL), 278 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), 279 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), 280 OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), 281 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL), 282 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL), 283 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), 284 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), 285 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), 286 /* Requires device name bindings. */ 287 OF_DEV_AUXDATA("stericsson,nmk_pinctrl", U8500_PRCMU_BASE, 288 "pinctrl-db8500", NULL), 289 /* Requires clock name and DMA bindings. */ 290 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, 291 "ux500-msp-i2s.0", &msp0_platform_data), 292 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, 293 "ux500-msp-i2s.1", &msp1_platform_data), 294 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000, 295 "ux500-msp-i2s.2", &msp2_platform_data), 296 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, 297 "ux500-msp-i2s.3", &msp3_platform_data), 298 {}, 299}; 300 301static const struct of_device_id u8500_local_bus_nodes[] = { 302 /* only create devices below soc node */ 303 { .compatible = "stericsson,db8500", }, 304 { .compatible = "stericsson,db8500-prcmu", }, 305 { .compatible = "simple-bus"}, 306 { }, 307}; 308 309static void __init u8500_init_machine(void) 310{ 311 struct device *parent = NULL; 312 313 /* Pinmaps must be in place before devices register */ 314 if (of_machine_is_compatible("st-ericsson,mop500")) 315 mop500_pinmaps_init(); 316 else if (of_machine_is_compatible("calaosystems,snowball-a9500")) 317 snowball_pinmaps_init(); 318 else if (of_machine_is_compatible("st-ericsson,hrefv60+")) 319 hrefv60_pinmaps_init(); 320 else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} 321 /* TODO: Add pinmaps for ccu9540 board. */ 322 323 /* TODO: Export SoC, USB, cpu-freq and DMA40 */ 324 parent = u8500_of_init_devices(); 325 326 /* automatically probe child nodes of db8500 device */ 327 of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); 328} 329 330static const char * stericsson_dt_platform_compat[] = { 331 "st-ericsson,u8500", 332 "st-ericsson,u8540", 333 "st-ericsson,u9500", 334 "st-ericsson,u9540", 335 NULL, 336}; 337 338DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)") 339 .smp = smp_ops(ux500_smp_ops), 340 .map_io = u8500_map_io, 341 .init_irq = ux500_init_irq, 342 /* we re-use nomadik timer here */ 343 .timer = &ux500_timer, 344 .init_machine = u8500_init_machine, 345 .init_late = NULL, 346 .dt_compat = stericsson_dt_platform_compat, 347MACHINE_END 348 349#endif 350