11e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij/* 21e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * Copyright (C) ST-Ericsson SA 2010-2013 31e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * Author: Rickard Andersson <rickard.andersson@stericsson.com> for 41e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * ST-Ericsson. 51e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro. 6ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson * Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro. 7ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson * 81e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * License terms: GNU General Public License (GPL) version 2 91e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * 101e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij */ 111e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 121e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#include <linux/kernel.h> 131e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#include <linux/irqchip/arm-gic.h> 141e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#include <linux/delay.h> 151e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#include <linux/io.h> 16ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson#include <linux/suspend.h> 171e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#include <linux/platform_data/arm-ux500-pm.h> 181e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 19174e7796624d2749359c3fdc673c1232b060d7f6Linus Walleij#include "db8500-regs.h" 201e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 211e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij/* ARM WFI Standby signal register */ 221e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130) 231e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARM_WFI_STANDBY_WFI0 0x08 241e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARM_WFI_STANDBY_WFI1 0x10 251e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_IOCR (prcmu_base + 0x310) 261e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_IOCR_IOFORCE 0x1 271e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 281e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij/* Dual A9 core interrupt management unit registers */ 291e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_A9_MASK_REQ (prcmu_base + 0x328) 301e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1 311e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 321e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_A9_MASK_ACK (prcmu_base + 0x32c) 331e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c) 341e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120) 351e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124) 361e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128) 371e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C) 381e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260) 391e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264) 401e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268) 411e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) 421e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 431e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleijstatic void __iomem *prcmu_base; 441e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 451e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij/* This function decouple the gic from the prcmu */ 461e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleijint prcmu_gic_decouple(void) 471e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij{ 481e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij u32 val = readl(PRCM_A9_MASK_REQ); 491e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 501e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij /* Set bit 0 register value to 1 */ 511e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, 521e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij PRCM_A9_MASK_REQ); 531e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 541e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij /* Make sure the register is updated */ 551e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij readl(PRCM_A9_MASK_REQ); 561e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 571e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij /* Wait a few cycles for the gic mask completion */ 581e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij udelay(1); 591e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 601e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij return 0; 611e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij} 621e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 631e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij/* This function recouple the gic with the prcmu */ 641e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleijint prcmu_gic_recouple(void) 651e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij{ 661e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij u32 val = readl(PRCM_A9_MASK_REQ); 671e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 681e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij /* Set bit 0 register value to 0 */ 691e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); 701e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 711e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij return 0; 721e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij} 731e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 741e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij#define PRCMU_GIC_NUMBER_REGS 5 751e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 761e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij/* 771e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * This function checks if there are pending irq on the gic. It only 781e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * makes sense if the gic has been decoupled before with the 791e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * db8500_prcmu_gic_decouple function. Disabling an interrupt only 801e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * disables the forwarding of the interrupt to any CPU interface. It 811e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * does not prevent the interrupt from changing state, for example 821e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * becoming pending, or active and pending if it is already 831e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * active. Hence, we have to check the interrupt is pending *and* is 841e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * active. 851e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij */ 861e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleijbool prcmu_gic_pending_irq(void) 871e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij{ 881e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij u32 pr; /* Pending register */ 891e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij u32 er; /* Enable register */ 901e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 911e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij int i; 921e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 931e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij /* 5 registers. STI & PPI not skipped */ 941e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { 951e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 961e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); 971e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 981e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 991e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij if (pr & er) 1001e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij return true; /* There is a pending interrupt */ 1011e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij } 1021e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 1031e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij return false; 1041e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij} 1051e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 1061e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij/* 1071e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * This function checks if there are pending interrupt on the 1081e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * prcmu which has been delegated to monitor the irqs with the 1091e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * db8500_prcmu_copy_gic_settings function. 1101e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij */ 1111e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleijbool prcmu_pending_irq(void) 1121e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij{ 1131e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij u32 it, im; 1141e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij int i; 1151e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 1161e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 1171e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij it = readl(PRCM_ARMITVAL31TO0 + i * 4); 1181e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij im = readl(PRCM_ARMITMSK31TO0 + i * 4); 1191e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij if (it & im) 1201e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij return true; /* There is a pending interrupt */ 1211e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij } 1221e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 1231e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij return false; 1241e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij} 1251e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 1261e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij/* 1271e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * This function checks if the specified cpu is in in WFI. It's usage 1281e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple 1291e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * function. Of course passing smp_processor_id() to this function will 1301e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * always return false... 1311e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij */ 1321e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleijbool prcmu_is_cpu_in_wfi(int cpu) 1331e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij{ 1341e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : 1351e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij PRCM_ARM_WFI_STANDBY_WFI0; 1361e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij} 1371e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 1381e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij/* 1391e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * This function copies the gic SPI settings to the prcmu in order to 1401e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * monitor them and abort/finish the retention/off sequence or state. 1411e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij */ 1421e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleijint prcmu_copy_gic_settings(void) 1431e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij{ 1441e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij u32 er; /* Enable register */ 1451e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); 1461e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij int i; 1471e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 1481e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij /* We skip the STI and PPI */ 1491e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { 1501e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij er = readl_relaxed(dist_base + 1511e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij GIC_DIST_ENABLE_SET + (i + 1) * 4); 1521e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij writel(er, PRCM_ARMITMSK31TO0 + i * 4); 1531e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij } 1541e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 1551e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij return 0; 1561e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij} 1571e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij 158ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson#ifdef CONFIG_SUSPEND 159ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hanssonstatic int ux500_suspend_enter(suspend_state_t state) 160ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson{ 161ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson cpu_do_idle(); 162ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson return 0; 163ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson} 164ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson 165ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hanssonstatic int ux500_suspend_valid(suspend_state_t state) 166ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson{ 167ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; 168ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson} 169ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson 170ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hanssonstatic const struct platform_suspend_ops ux500_suspend_ops = { 171ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson .enter = ux500_suspend_enter, 172ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson .valid = ux500_suspend_valid, 173ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson}; 174ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson#define UX500_SUSPEND_OPS (&ux500_suspend_ops) 175ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson#else 176ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson#define UX500_SUSPEND_OPS NULL 177ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson#endif 178ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson 1791e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleijvoid __init ux500_pm_init(u32 phy_base, u32 size) 1801e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij{ 1811e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij prcmu_base = ioremap(phy_base, size); 1821e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij if (!prcmu_base) { 1831e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij pr_err("could not remap PRCMU for PM functions\n"); 1841e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij return; 1851e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij } 1861e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij /* 1871e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * On watchdog reboot the GIC is in some cases decoupled. 1881e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij * This will make sure that the GIC is correctly configured. 1891e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij */ 1901e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij prcmu_gic_recouple(); 191ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson 192ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson /* Set up ux500 suspend callbacks. */ 193ead9e2936b071a501f7c7ff709802ea4257cd23aUlf Hansson suspend_set_ops(UX500_SUSPEND_OPS); 1941e22a8c614a5d8c29d0882de21ce327673b71fcaLinus Walleij} 195