1bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 2bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * linux/arch/arm/mm/proc-v7.S 3bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 4bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 6bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This program is free software; you can redistribute it and/or modify 7bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * it under the terms of the GNU General Public License version 2 as 8bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * published by the Free Software Foundation. 9bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 10bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This is the "shell" of the ARMv7 processor support. 11bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 12991da17ec0b9f396154c8120ffd10e5d7d7aa361Tim Abbott#include <linux/init.h> 13bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <linux/linkage.h> 14bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/assembler.h> 15bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/asm-offsets.h> 165ec9407dd1196daaf12b427b351e2cd62d2a16a7Russell King#include <asm/hwcap.h> 17bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable-hwdef.h> 18bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable.h> 19bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 20bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include "proc-macros.S" 21bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 221b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#ifdef CONFIG_ARM_LPAE 231b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#include "proc-v7-3level.S" 241b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#else 258d2cd3a38fd663bd341507f5ac29002ffd81d986Catalin Marinas#include "proc-v7-2level.S" 261b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#endif 2773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan 28bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_init) 296ebbf2ce437b33022d30badd49dc94d33ecfa498Russell King ret lr 3093ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_init) 31bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 32bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_fin) 331f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mrc p15, 0, r0, c1, c0, 0 @ ctrl register 341f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x1000 @ ...i............ 351f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x0006 @ .............ca. 361f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mcr p15, 0, r0, c1, c0, 0 @ disable caches 376ebbf2ce437b33022d30badd49dc94d33ecfa498Russell King ret lr 3893ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_fin) 39bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 40bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 41bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_reset(loc) 42bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 43bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Perform a soft reset of the system. Put the CPU into the 44bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * same state as it would be if it had been reset, and branch 45bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * to what would be the reset vector. 46bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 47bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - loc - location to jump to for soft reset 48f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon * 49f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon * This code must be executed using a flat identity mapping with 50f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon * caches disabled. 51bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 52bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 5 531a4baafa7d203da1cceb302c2df38f0fea1c17a1Will Deacon .pushsection .idmap.text, "ax" 54bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_reset) 55f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon mrc p15, 0, r1, c1, c0, 0 @ ctrl register 56f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon bic r1, r1, #0x1 @ ...............m 570f81bb6b051ad760686b5b0fef8c731282c16ef5Will Deacon THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) 58f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon mcr p15, 0, r1, c1, c0, 0 @ disable MMU 59f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon isb 60153cd8e839b5729358d4e5c3371e7509ee5ac96aDave Martin bx r0 6193ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_reset) 621a4baafa7d203da1cceb302c2df38f0fea1c17a1Will Deacon .popsection 63bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 64bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 65bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_do_idle() 66bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 67bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Idle the processor (eg, wait for interrupt). 68bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 69bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * IRQs are already disabled. 70bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 71bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_do_idle) 728553cb67d2318db327071018fc81084cbabccc46Catalin Marinas dsb @ WFI may enter a low-power mode 73000b50259271c9c14f6e175795f5164e1d51d35bCatalin Marinas wfi 746ebbf2ce437b33022d30badd49dc94d33ecfa498Russell King ret lr 7593ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_do_idle) 76bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 77bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_dcache_clean_area) 78bf3f0f332f76a85ff3a0b393aaded5a8533769c0Will Deacon ALT_SMP(W(nop)) @ MP extensions imply L1 PTW 79bf3f0f332f76a85ff3a0b393aaded5a8533769c0Will Deacon ALT_UP_B(1f) 806ebbf2ce437b33022d30badd49dc94d33ecfa498Russell King ret lr 81bf3f0f332f76a85ff3a0b393aaded5a8533769c0Will Deacon1: dcache_line_size r2, r3 82bf3f0f332f76a85ff3a0b393aaded5a8533769c0Will Deacon2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 83bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas add r0, r0, r2 84bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas subs r1, r1, r2 85bf3f0f332f76a85ff3a0b393aaded5a8533769c0Will Deacon bhi 2b 866abdd491698a27f7df04a32ca12cc453810e4396Will Deacon dsb ishst 876ebbf2ce437b33022d30badd49dc94d33ecfa498Russell King ret lr 8893ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_dcache_clean_area) 89bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 9078a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin string cpu_v7_name, "ARMv7 Processor" 91bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 92bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 93f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 94f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King.globl cpu_v7_suspend_size 95f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian.equ cpu_v7_suspend_size, 4 * 9 9615e0d9e37c7fe9711b60f47221c394d45553ad8cArnd Bergmann#ifdef CONFIG_ARM_CPU_SUSPEND 97f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_v7_do_suspend) 98de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King stmfd sp!, {r4 - r10, lr} 99f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 1001aede681ac159884c77817d33230eed9185b6f6cRussell King mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 1011aede681ac159884c77817d33230eed9185b6f6cRussell King stmia r0!, {r4 - r5} 102aa1aadc3305c4917c39f0291613a5ec81dd4c73bWill Deacon#ifdef CONFIG_MMU 103f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r6, c3, c0, 0 @ Domain ID 104f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian#ifdef CONFIG_ARM_LPAE 105f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian mrrc p15, 1, r5, r7, c2 @ TTB 1 106f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian#else 107de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r7, c2, c0, 1 @ TTB 1 108f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian#endif 1091b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas mrc p15, 0, r11, c2, c0, 2 @ TTB control register 110aa1aadc3305c4917c39f0291613a5ec81dd4c73bWill Deacon#endif 111de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r8, c1, c0, 0 @ Control register 112de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register 113de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control 114f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian stmia r0, {r5 - r11} 115de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ldmfd sp!, {r4 - r10, pc} 116f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_v7_do_suspend) 117f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 118f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_v7_do_resume) 119f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mov ip, #0 120f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 1211aede681ac159884c77817d33230eed9185b6f6cRussell King mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 1221aede681ac159884c77817d33230eed9185b6f6cRussell King ldmia r0!, {r4 - r5} 123f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 1241aede681ac159884c77817d33230eed9185b6f6cRussell King mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID 125f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian ldmia r0, {r5 - r11} 126aa1aadc3305c4917c39f0291613a5ec81dd4c73bWill Deacon#ifdef CONFIG_MMU 127aa1aadc3305c4917c39f0291613a5ec81dd4c73bWill Deacon mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 128f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r6, c3, c0, 0 @ Domain ID 129f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian#ifdef CONFIG_ARM_LPAE 130f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian mcrr p15, 0, r1, ip, c2 @ TTB 0 131f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian mcrr p15, 1, r5, r7, c2 @ TTB 1 132f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian#else 133de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 134de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 135de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r1, c2, c0, 0 @ TTB 0 136de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r7, c2, c0, 1 @ TTB 1 137f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8Mahesh Sivasubramanian#endif 1381b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas mcr p15, 0, r11, c2, c0, 2 @ TTB control register 139f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r4, =PRRR @ PRRR 140f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r5, =NMRR @ NMRR 141f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r4, c10, c2, 0 @ write PRRR 142f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r5, c10, c2, 1 @ write NMRR 143aa1aadc3305c4917c39f0291613a5ec81dd4c73bWill Deacon#endif /* CONFIG_MMU */ 144aa1aadc3305c4917c39f0291613a5ec81dd4c73bWill Deacon mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register 145aa1aadc3305c4917c39f0291613a5ec81dd4c73bWill Deacon teq r4, r9 @ Is it already set? 146aa1aadc3305c4917c39f0291613a5ec81dd4c73bWill Deacon mcrne p15, 0, r9, c1, c0, 1 @ No, so write it 147aa1aadc3305c4917c39f0291613a5ec81dd4c73bWill Deacon mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control 148f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King isb 149f35235a315a167e38e8e5bc9e476dcd7c932612cRussell King dsb 150de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mov r0, r8 @ control register 151f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King b cpu_resume_mmu 152f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_v7_do_resume) 153f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King#endif 154f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 155ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo/* 156ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo * Cortex-A9 processor functions 157ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo */ 158ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init 159ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin 160ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo globl_equ cpu_ca9mp_reset, cpu_v7_reset 161ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle 162ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area 163ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm 164ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext 165ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo.globl cpu_ca9mp_suspend_size 166ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo.equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2 167ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo#ifdef CONFIG_ARM_CPU_SUSPEND 168ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn GuoENTRY(cpu_ca9mp_do_suspend) 169ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo stmfd sp!, {r4 - r5} 170ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register 171ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo mrc p15, 0, r5, c15, c0, 0 @ Power register 172ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo stmia r0!, {r4 - r5} 173ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo ldmfd sp!, {r4 - r5} 174ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo b cpu_v7_do_suspend 175ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn GuoENDPROC(cpu_ca9mp_do_suspend) 176ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo 177ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn GuoENTRY(cpu_ca9mp_do_resume) 178ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo ldmia r0!, {r4 - r5} 179ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register 180ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo teq r4, r10 @ Already restored? 181ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it 182ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo mrc p15, 0, r10, c15, c0, 0 @ Read Power register 183ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo teq r5, r10 @ Already restored? 184ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it 185ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo b cpu_v7_do_resume 186ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn GuoENDPROC(cpu_ca9mp_do_resume) 187ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo#endif 188ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo 1893e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT#ifdef CONFIG_CPU_PJ4B 1903e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm 1913e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext 1923e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init 1933e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin 1943e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT globl_equ cpu_pj4b_reset, cpu_v7_reset 1953e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT#ifdef CONFIG_PJ4B_ERRATA_4742 1963e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENTENTRY(cpu_pj4b_do_idle) 1973e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT dsb @ WFI may enter a low-power mode 1983e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT wfi 1993e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT dsb @barrier 2006ebbf2ce437b33022d30badd49dc94d33ecfa498Russell King ret lr 2013e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENTENDPROC(cpu_pj4b_do_idle) 2023e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT#else 2033e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle 2043e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT#endif 2053e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area 20616c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT#ifdef CONFIG_ARM_CPU_SUSPEND 20716c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENTENTRY(cpu_pj4b_do_suspend) 20816c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT stmfd sp!, {r6 - r10} 20916c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features 21016c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0 21116c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2 21216c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1 21316c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC 21416c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT stmia r0!, {r6 - r10} 21516c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT ldmfd sp!, {r6 - r10} 21616c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT b cpu_v7_do_suspend 21716c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENTENDPROC(cpu_pj4b_do_suspend) 21816c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT 21916c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENTENTRY(cpu_pj4b_do_resume) 22016c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT ldmia r0!, {r6 - r10} 2217ca791c59dda75715088d91788bf6989b5a1945aShawn Guo mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features 2227ca791c59dda75715088d91788bf6989b5a1945aShawn Guo mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0 2237ca791c59dda75715088d91788bf6989b5a1945aShawn Guo mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2 2247ca791c59dda75715088d91788bf6989b5a1945aShawn Guo mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1 2257ca791c59dda75715088d91788bf6989b5a1945aShawn Guo mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC 22616c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT b cpu_v7_do_resume 22716c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENTENDPROC(cpu_pj4b_do_resume) 22816c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT#endif 22916c79a3776c17965dedab4732d925f6098df91c1Gregory CLEMENT.globl cpu_pj4b_suspend_size 2307ca791c59dda75715088d91788bf6989b5a1945aShawn Guo.equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5 2313e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT 2323e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT#endif 2333e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT 234bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 235bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * __v7_setup 236bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 237bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Initialise TLB, Caches, and MMU state ready to switch the MMU 238bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * on. Return in r0 the new CP15 C1 control register setting. 239bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 240bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This should be able to cover all ARMv7 cores. 241bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 242bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 243bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - cache type register is implemented 244bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 24515eb169bfec291faf25b158cfa9842b72f7803adPawel Moll__v7_ca5mp_setup: 24614eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker__v7_ca9mp_setup: 247c90ad5c940583525f46938149b91187e75acc546Jonathan Austin__v7_cr7mp_setup: 248c90ad5c940583525f46938149b91187e75acc546Jonathan Austin mov r10, #(1 << 0) @ Cache/TLB ops broadcasting 2497665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon b 1f 250b4244738d20a631cd27fa105a2db71622618ab4ePawel Moll__v7_ca7mp_setup: 251ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin__v7_ca12mp_setup: 2527665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon__v7_ca15mp_setup: 253c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino__v7_b15mp_setup: 254cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon__v7_ca17mp_setup: 2557665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon mov r10, #0 2567665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon1: 25773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifdef CONFIG_SMP 258f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_SMP(mrc p15, 0, r0, c1, c0, 1) 259f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_UP(mov r0, #(1 << 6)) @ fake it for UP 2601b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 2617665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode 2627665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon orreq r0, r0, r10 @ Enable CPU-specific SMP bits 2637665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon mcreq p15, 0, r0, c1, c0, 1 26473b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 265d106de38ca927f2a53cd56ef94c506e8f6bd37e1Haojian Zhuang b __v7_setup 266de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 267de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT__v7_pj4b_setup: 268de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#ifdef CONFIG_CPU_PJ4B 269de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 270de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT/* Auxiliary Debug Modes Control 1 Register */ 271de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */ 272de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */ 273de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */ 274de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 275de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT/* Auxiliary Debug Modes Control 2 Register */ 276de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */ 277de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */ 278de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */ 279de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */ 280de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */ 281de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\ 282de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR) 283de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 284de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT/* Auxiliary Functional Modes Control Register 0 */ 285de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */ 286de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */ 287de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */ 288de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 289de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT/* Auxiliary Debug Modes Control 0 Register */ 290de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */ 291de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 292de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* Auxiliary Debug Modes Control 1 Register */ 293de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mrc p15, 1, r0, c15, c1, 1 294de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_CLEAN_LINE 295de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_INTER_PARITY 296de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT bic r0, r0, #PJ4B_STATIC_BP 297de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mcr p15, 1, r0, c15, c1, 1 298de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 299de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* Auxiliary Debug Modes Control 2 Register */ 300de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mrc p15, 1, r0, c15, c1, 2 301de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT bic r0, r0, #PJ4B_FAST_LDR 302de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_AUX_DBG_CTRL2 303de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mcr p15, 1, r0, c15, c1, 2 304de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 305de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* Auxiliary Functional Modes Control Register 0 */ 306de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mrc p15, 1, r0, c15, c2, 0 307de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#ifdef CONFIG_SMP 308de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_SMP_CFB 309de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#endif 310de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_L1_PAR_CHK 311de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_BROADCAST_CACHE 312de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mcr p15, 1, r0, c15, c2, 0 313de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 314de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* Auxiliary Debug Modes Control 0 Register */ 315de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mrc p15, 1, r0, c15, c1, 0 316de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_WFI_WFE 317de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mcr p15, 1, r0, c15, c1, 0 318de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 319de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#endif /* CONFIG_CPU_PJ4B */ 320de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 32114eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker__v7_setup: 322bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas adr r12, __v7_setup_stack @ the local stack 323bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas stmia r12, {r0-r5, r7, r9, r11, lr} 3246323fa2256baa73d6a960ee57ec086b66aeecd0bSantosh Shilimkar bl v7_flush_dcache_louis 325bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldmia r12, {r0-r5, r7, r9, r11, lr} 3261946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 3271946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrc p15, 0, r0, c0, c0, 0 @ read main ID register 3281946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r10, r0, #0xff000000 @ ARM? 3291946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r10, #0x41000000 3309f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon bne 3f 3311946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r5, r0, #0x00f00000 @ variant 3321946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r6, r0, #0x0000000f @ revision 3336491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon orr r6, r6, r5, lsr #20-4 @ combine variant and revision 3346491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon ubfx r0, r0, #4, #12 @ primary part number 3351946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 3366491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon /* Cortex-A8 Errata */ 3376491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon ldr r10, =0x00000c08 @ Cortex-A8 primary part number 3386491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r0, r10 3396491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon bne 2f 34062e4d357aae0c7438c537bdb1c86909d7cac2663Rob Herring#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM) 34162e4d357aae0c7438c537bdb1c86909d7cac2663Rob Herring 3421946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r5, #0x00100000 @ only present in r1p* 3431946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 3441946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 6) @ set IBE to 1 3451946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 3467ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 347855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#ifdef CONFIG_ARM_ERRATA_458693 3486491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r6, #0x20 @ only present in r2p0 3491946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 3501946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 5) @ set L1NEON to 1 3511946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 3521946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 353855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#endif 3540516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#ifdef CONFIG_ARM_ERRATA_460075 3556491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r6, #0x20 @ only present in r2p0 3561946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 3571946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King tsteq r10, #1 << 22 3581946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 3591946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 3600516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#endif 3619f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon b 3f 3629f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon 3639f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon /* Cortex-A9 Errata */ 3649f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number 3659f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon teq r0, r10 3669f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon bne 3f 3679f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon#ifdef CONFIG_ARM_ERRATA_742230 3689f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon cmp r6, #0x22 @ only present up to r2p2 3699f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register 3709f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon orrle r10, r10, #1 << 4 @ set bit #4 3719f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register 3729f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon#endif 373a672e99b129e286df2e2697a1b603d82321117f3Will Deacon#ifdef CONFIG_ARM_ERRATA_742231 374a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teq r6, #0x20 @ present in r2p0 375a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teqne r6, #0x21 @ present in r2p1 376a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teqne r6, #0x22 @ present in r2p2 377a672e99b129e286df2e2697a1b603d82321117f3Will Deacon mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 378a672e99b129e286df2e2697a1b603d82321117f3Will Deacon orreq r10, r10, #1 << 12 @ set bit #12 379a672e99b129e286df2e2697a1b603d82321117f3Will Deacon orreq r10, r10, #1 << 22 @ set bit #22 380a672e99b129e286df2e2697a1b603d82321117f3Will Deacon mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 381a672e99b129e286df2e2697a1b603d82321117f3Will Deacon#endif 382475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon#ifdef CONFIG_ARM_ERRATA_743622 383efbc74ace95338484f8d732037b99c7c77098fceWill Deacon teq r5, #0x00200000 @ only present in r2p* 384475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 385475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon orreq r10, r10, #1 << 6 @ set bit #6 386475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 387475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon#endif 388ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) 389ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 390ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin ALT_UP_B(1f) 3919a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register 3929a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon orrlt r10, r10, #1 << 11 @ set bit #11 3939a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register 394ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin1: 3959a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon#endif 3961946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 39784b6504f560157ff2077dd3757eee481b81dc39bWill Deacon /* Cortex-A15 Errata */ 39884b6504f560157ff2077dd3757eee481b81dc39bWill Deacon3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number 39984b6504f560157ff2077dd3757eee481b81dc39bWill Deacon teq r0, r10 40084b6504f560157ff2077dd3757eee481b81dc39bWill Deacon bne 4f 40184b6504f560157ff2077dd3757eee481b81dc39bWill Deacon 40284b6504f560157ff2077dd3757eee481b81dc39bWill Deacon#ifdef CONFIG_ARM_ERRATA_773022 40384b6504f560157ff2077dd3757eee481b81dc39bWill Deacon cmp r6, #0x4 @ only present up to r0p4 40484b6504f560157ff2077dd3757eee481b81dc39bWill Deacon mrcle p15, 0, r10, c1, c0, 1 @ read aux control register 40584b6504f560157ff2077dd3757eee481b81dc39bWill Deacon orrle r10, r10, #1 << 1 @ disable loop buffer 40684b6504f560157ff2077dd3757eee481b81dc39bWill Deacon mcrle p15, 0, r10, c1, c0, 1 @ write aux control register 40784b6504f560157ff2077dd3757eee481b81dc39bWill Deacon#endif 40884b6504f560157ff2077dd3757eee481b81dc39bWill Deacon 40984b6504f560157ff2077dd3757eee481b81dc39bWill Deacon4: mov r10, #0 410bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 4112eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 412bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 4138d2cd3a38fd663bd341507f5ac29002ffd81d986Catalin Marinas v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup 414f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r5, =PRRR @ PRRR 415f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r6, =NMRR @ NMRR 4163f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r5, c10, c2, 0 @ write PRRR 4173f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r6, c10, c2, 1 @ write NMRR 418bdaaaec39792ee0035d6c5a5ad2520991e090a3cCatalin Marinas#endif 419bae0ca2bc550d1ec6a118fb8f2696f18c4da3d8eWill Deacon dsb @ Complete invalidations 420078c04545ba56da21567728a909a496df5ff730dJonathan Austin#ifndef CONFIG_ARM_THUMBEE 421078c04545ba56da21567728a909a496df5ff730dJonathan Austin mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE 422078c04545ba56da21567728a909a496df5ff730dJonathan Austin and r0, r0, #(0xf << 12) @ ThumbEE enabled field 423078c04545ba56da21567728a909a496df5ff730dJonathan Austin teq r0, #(1 << 12) @ check if ThumbEE is present 424078c04545ba56da21567728a909a496df5ff730dJonathan Austin bne 1f 425078c04545ba56da21567728a909a496df5ff730dJonathan Austin mov r5, #0 426078c04545ba56da21567728a909a496df5ff730dJonathan Austin mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 427078c04545ba56da21567728a909a496df5ff730dJonathan Austin mrc p14, 6, r0, c0, c0, 0 @ load TEECR 428078c04545ba56da21567728a909a496df5ff730dJonathan Austin orr r0, r0, #1 @ set the 1st bit in order to 429078c04545ba56da21567728a909a496df5ff730dJonathan Austin mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access 430078c04545ba56da21567728a909a496df5ff730dJonathan Austin1: 431078c04545ba56da21567728a909a496df5ff730dJonathan Austin#endif 4322eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas adr r5, v7_crval 4332eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas ldmia r5, {r5, r6} 434457c2403c513c74f60d5757fd11ae927e5554a38Ben Dooks ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables 43564d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm#ifdef CONFIG_SWP_EMULATE 43664d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm orr r5, r5, #(1 << 10) @ set SW bit in "clear" 43764d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm bic r6, r6, #(1 << 10) @ clear it in "mmuset" 43864d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm#endif 4392eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas mrc p15, 0, r0, c1, c0, 0 @ read control register 4402eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas bic r0, r0, r5 @ clear bits them 4412eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas orr r0, r0, r6 @ set them 442347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 4436ebbf2ce437b33022d30badd49dc94d33ecfa498Russell King ret lr @ return to head.S:__ret 44493ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(__v7_setup) 445bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 4468d2cd3a38fd663bd341507f5ac29002ffd81d986Catalin Marinas .align 2 447bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup_stack: 448bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .space 4 * 11 @ 11 registers 449bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 4505085f3ff458521045f7e43da62b8c30ea7df2e82Russell King __INITDATA 4515085f3ff458521045f7e43da62b8c30ea7df2e82Russell King 45278a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 45378a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 454ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 4553e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT#ifdef CONFIG_CPU_PJ4B 4563e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 4573e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT#endif 458bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 4595085f3ff458521045f7e43da62b8c30ea7df2e82Russell King .section ".rodata" 4605085f3ff458521045f7e43da62b8c30ea7df2e82Russell King 46178a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin string cpu_arch_name, "armv7" 46278a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin string cpu_elf_name, "v7" 463bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 464bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 465bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".proc.info.init", #alloc, #execinstr 466bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 467dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll /* 468dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll * Standard v7 proc info content 469dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll */ 4703e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions 471dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 4721b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) 473dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 4741b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags) 4751b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \ 4761b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags 477dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll W(b) \initfunc 47814eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_arch_name 47914eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_elf_name 480dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ 481dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll HWCAP_EDSP | HWCAP_TLS | \hwcaps 48214eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_v7_name 4833e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT .long \proc_fns 48414eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7wbi_tlb_fns 48514eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v6_user_fns 48614eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7_cache_fns 487dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll.endm 488dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll 4891b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#ifndef CONFIG_ARM_LPAE 490dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll /* 49115eb169bfec291faf25b158cfa9842b72f7803adPawel Moll * ARM Ltd. Cortex A5 processor. 49215eb169bfec291faf25b158cfa9842b72f7803adPawel Moll */ 49315eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .type __v7_ca5mp_proc_info, #object 49415eb169bfec291faf25b158cfa9842b72f7803adPawel Moll__v7_ca5mp_proc_info: 49515eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .long 0x410fc050 49615eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .long 0xff0ffff0 49715eb169bfec291faf25b158cfa9842b72f7803adPawel Moll __v7_proc __v7_ca5mp_setup 49815eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info 49915eb169bfec291faf25b158cfa9842b72f7803adPawel Moll 50015eb169bfec291faf25b158cfa9842b72f7803adPawel Moll /* 501dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll * ARM Ltd. Cortex A9 processor. 502dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll */ 503dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .type __v7_ca9mp_proc_info, #object 504dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll__v7_ca9mp_proc_info: 505dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long 0x410fc090 506dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long 0xff0ffff0 507ddd0c53018222df6bd9b2f61c881887b56b75d88Shawn Guo __v7_proc __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions 50814eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 509de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 510b361d61dc1aaa9bdac0a0995e443c12146d916fdGregory CLEMENT#endif /* CONFIG_ARM_LPAE */ 511b361d61dc1aaa9bdac0a0995e443c12146d916fdGregory CLEMENT 512de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* 513de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT * Marvell PJ4B processor. 514de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT */ 5153e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT#ifdef CONFIG_CPU_PJ4B 516de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT .type __v7_pj4b_proc_info, #object 517de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT__v7_pj4b_proc_info: 518049be07053ebbf0ee8543caea23ae7bdf0765bb2Gregory CLEMENT .long 0x560f5800 519049be07053ebbf0ee8543caea23ae7bdf0765bb2Gregory CLEMENT .long 0xff0fff00 5203e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions 521de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info 5223e0a07f8c401bb43e0f964c5f1285b2cb2028645Gregory CLEMENT#endif 52314eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker 524bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 525c90ad5c940583525f46938149b91187e75acc546Jonathan Austin * ARM Ltd. Cortex R7 processor. 526c90ad5c940583525f46938149b91187e75acc546Jonathan Austin */ 527c90ad5c940583525f46938149b91187e75acc546Jonathan Austin .type __v7_cr7mp_proc_info, #object 528c90ad5c940583525f46938149b91187e75acc546Jonathan Austin__v7_cr7mp_proc_info: 529c90ad5c940583525f46938149b91187e75acc546Jonathan Austin .long 0x410fc170 530c90ad5c940583525f46938149b91187e75acc546Jonathan Austin .long 0xff0ffff0 531c90ad5c940583525f46938149b91187e75acc546Jonathan Austin __v7_proc __v7_cr7mp_setup 532c90ad5c940583525f46938149b91187e75acc546Jonathan Austin .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info 533c90ad5c940583525f46938149b91187e75acc546Jonathan Austin 534c90ad5c940583525f46938149b91187e75acc546Jonathan Austin /* 535868dbf905245a524496a0535982ed21ad3be5585Will Deacon * ARM Ltd. Cortex A7 processor. 536868dbf905245a524496a0535982ed21ad3be5585Will Deacon */ 537868dbf905245a524496a0535982ed21ad3be5585Will Deacon .type __v7_ca7mp_proc_info, #object 538868dbf905245a524496a0535982ed21ad3be5585Will Deacon__v7_ca7mp_proc_info: 539868dbf905245a524496a0535982ed21ad3be5585Will Deacon .long 0x410fc070 540868dbf905245a524496a0535982ed21ad3be5585Will Deacon .long 0xff0ffff0 5418164f7af88d9ad3a757bd14f634b23997ee77f6bStephen Boyd __v7_proc __v7_ca7mp_setup 542868dbf905245a524496a0535982ed21ad3be5585Will Deacon .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info 543868dbf905245a524496a0535982ed21ad3be5585Will Deacon 544868dbf905245a524496a0535982ed21ad3be5585Will Deacon /* 545ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin * ARM Ltd. Cortex A12 processor. 546ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin */ 547ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin .type __v7_ca12mp_proc_info, #object 548ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin__v7_ca12mp_proc_info: 549ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin .long 0x410fc0d0 550ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin .long 0xff0ffff0 551ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin __v7_proc __v7_ca12mp_setup 552ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info 553ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin 554ddb2ff731b53ae28ec3a2af0da96a108b8bad814Jonathan Austin /* 5557665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon * ARM Ltd. Cortex A15 processor. 5567665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon */ 5577665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .type __v7_ca15mp_proc_info, #object 5587665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon__v7_ca15mp_proc_info: 5597665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .long 0x410fc0f0 5607665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .long 0xff0ffff0 5618164f7af88d9ad3a757bd14f634b23997ee77f6bStephen Boyd __v7_proc __v7_ca15mp_setup 5627665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info 5637665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon 5647665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon /* 565c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino * Broadcom Corporation Brahma-B15 processor. 566c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino */ 567c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino .type __v7_b15mp_proc_info, #object 568c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino__v7_b15mp_proc_info: 569c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino .long 0x420f00f0 570c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino .long 0xff0ffff0 571fbf10641487d0c6938e580d143e4519e7ea90acfBrian Norris __v7_proc __v7_b15mp_setup 572c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info 573c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino 574c51e78ed58e4e4e772bdd7897470ab2e7142f9c2Marc Carino /* 575cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon * ARM Ltd. Cortex A17 processor. 576cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon */ 577cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon .type __v7_ca17mp_proc_info, #object 578cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon__v7_ca17mp_proc_info: 579cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon .long 0x410fc0e0 580cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon .long 0xff0ffff0 581cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon __v7_proc __v7_ca17mp_setup 582cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info 583cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon 584cd000cf650cd43dc0dc37032cb4016985c9dda6cWill Deacon /* 585120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko * Qualcomm Inc. Krait processors. 586120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko */ 587120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko .type __krait_proc_info, #object 588120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko__krait_proc_info: 589120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko .long 0x510f0400 @ Required ID value 590120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko .long 0xff0ffc00 @ Mask for ID 591120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko /* 592120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko * Some Krait processors don't indicate support for SDIV and UDIV 593120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko * instructions in the ARM instruction set, even though they actually 594120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko * do support them. 595120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko */ 596120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko __v7_proc __v7_setup, hwcaps = HWCAP_IDIV 597120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko .size __krait_proc_info, . - __krait_proc_info 598120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko 599120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko /* 600bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Match any ARMv7 processor core. 601bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 602bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type __v7_proc_info, #object 603bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_proc_info: 604bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Required ID value 605bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Mask for ID 606dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll __v7_proc __v7_setup 607bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size __v7_proc_info, . - __v7_proc_info 608