proc-v7.S revision 0516e4643cd22fc9f535aef02ad1de66c382c93b
1bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 2bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * linux/arch/arm/mm/proc-v7.S 3bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 4bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 6bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This program is free software; you can redistribute it and/or modify 7bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * it under the terms of the GNU General Public License version 2 as 8bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * published by the Free Software Foundation. 9bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 10bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This is the "shell" of the ARMv7 processor support. 11bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 12bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <linux/linkage.h> 13bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/assembler.h> 14bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/asm-offsets.h> 155ec9407dd1196daaf12b427b351e2cd62d2a16a7Russell King#include <asm/hwcap.h> 16bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable-hwdef.h> 17bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable.h> 18bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 19bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include "proc-macros.S" 20bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 21bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_C (1 << 0) 22bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_S (1 << 1) 2373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_NC (0 << 3) 2473b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_OC_WBWA (1 << 3) 25bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WT (2 << 3) 26bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WB (3 << 3) 27bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 2873b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifndef CONFIG_SMP 2973b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB 3073b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#else 3173b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA 3273b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 3373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan 34bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_init) 35bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 3693ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_init) 37bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 38bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_fin) 39bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 4093ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_fin) 41bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 42bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 43bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_reset(loc) 44bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 45bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Perform a soft reset of the system. Put the CPU into the 46bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * same state as it would be if it had been reset, and branch 47bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * to what would be the reset vector. 48bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 49bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - loc - location to jump to for soft reset 50bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 51bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 52bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 53bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 5 54bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_reset) 55bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, r0 5693ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_reset) 57bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 58bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 59bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_do_idle() 60bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 61bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Idle the processor (eg, wait for interrupt). 62bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 63bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * IRQs are already disabled. 64bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 65bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_do_idle) 668553cb67d2318db327071018fc81084cbabccc46Catalin Marinas dsb @ WFI may enter a low-power mode 67000b50259271c9c14f6e175795f5164e1d51d35bCatalin Marinas wfi 68bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 6993ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_do_idle) 70bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 71bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_dcache_clean_area) 72bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifndef TLB_CAN_READ_FROM_L1_CACHE 73bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dcache_line_size r2, r3 74bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 75bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas add r0, r0, r2 76bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas subs r1, r1, r2 77bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bhi 1b 78bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 79bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 80bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 8193ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_dcache_clean_area) 82bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 83bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 84bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_switch_mm(pgd_phys, tsk) 85bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 86bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set the translation table base pointer to be pgd_phys 87bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 88bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pgd_phys - physical address of new TTB 89bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 90bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 91bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - we are not using split page tables 92bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 93bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_switch_mm) 942eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 95bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r2, #0 96bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 9773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r0, r0, #TTB_FLAGS 987ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#ifdef CONFIG_ARM_ERRATA_430973 997ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 1007ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 101bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 102bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 103bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 104bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 105bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r1, c13, c0, 1 @ set context ID 106bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 1072eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 108bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 10993ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_switch_mm) 110bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 111bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 112bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_set_pte_ext(ptep, pte) 113bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 114bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set a level 2 translation table entry. 115bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 116bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ptep - pointer to level 2 translation table entry 117bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * (hardware version is stored at -1024 bytes) 118bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pte - PTE value to store 119bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ext - value for extended PTE bits 120bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 121bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_set_pte_ext) 1222eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 123bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas str r1, [r0], #-2048 @ linux version 124bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 125bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bic r3, r1, #0x000003f0 1263f69c0c1af288d6b124d0a928a33b51061ebf850Russell King bic r3, r3, #PTE_TYPE_MASK 127bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, r2 128bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, #PTE_EXT_AP0 | 2 129bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 130b1cce6b1b2785fd61454b47ceacb461815407662Russell King tst r1, #1 << 4 1313f69c0c1af288d6b124d0a928a33b51061ebf850Russell King orrne r3, r3, #PTE_EXT_TEX(1) 1323f69c0c1af288d6b124d0a928a33b51061ebf850Russell King 133bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_WRITE 134bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r1, #L_PTE_DIRTY 135bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_APX 136bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 137bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_USER 138bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orrne r3, r3, #PTE_EXT_AP1 139bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r3, #PTE_EXT_APX 140bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 141bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 142bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_EXEC 143bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_XN 144bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 1453f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tst r1, #L_PTE_YOUNG 1463f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tstne r1, #L_PTE_PRESENT 147bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas moveq r3, #0 148bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 149bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas str r3, [r0] 150bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r0, c7, c10, 1 @ flush_pte 1512eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 152bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 15393ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_set_pte_ext) 154bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 155bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_v7_name: 156bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .ascii "ARMv7 Processor" 157bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 158bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 159bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".text.init", #alloc, #execinstr 160bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 161bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 162bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * __v7_setup 163bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 164bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Initialise TLB, Caches, and MMU state ready to switch the MMU 165bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * on. Return in r0 the new CP15 C1 control register setting. 166bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 167bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * We automatically detect if we have a Harvard cache, and use the 168bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Harvard cache control instructions insead of the unified cache 169bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * control instructions. 170bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 171bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This should be able to cover all ARMv7 cores. 172bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 173bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 174bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - cache type register is implemented 175bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 176bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup: 17773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifdef CONFIG_SMP 17873b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode 17973b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r0, r0, #(0x1 << 6) 18073b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan mcr p15, 0, r0, c1, c0, 1 18173b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 182bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas adr r12, __v7_setup_stack @ the local stack 183bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas stmia r12, {r0-r5, r7, r9, r11, lr} 184bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bl v7_flush_dcache_all 185bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldmia r12, {r0-r5, r7, r9, r11, lr} 1867ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#ifdef CONFIG_ARM_ERRATA_430973 1877ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas mrc p15, 0, r10, c1, c0, 1 @ read aux control register 1887ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas orr r10, r10, #(1 << 6) @ set IBE to 1 1897ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas mcr p15, 0, r10, c1, c0, 1 @ write aux control register 1907ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 191855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#ifdef CONFIG_ARM_ERRATA_458693 192855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas mrc p15, 0, r10, c1, c0, 1 @ read aux control register 193855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas orr r10, r10, #(1 << 5) @ set L1NEON to 1 194855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas orr r10, r10, #(1 << 9) @ set PLDNOP to 1 195855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas mcr p15, 0, r10, c1, c0, 1 @ write aux control register 196855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#endif 1970516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#ifdef CONFIG_ARM_ERRATA_460075 1980516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 1990516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit 2000516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 2010516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#endif 202bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r10, #0 203bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifdef HARVARD_CACHE 204bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 205bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 206bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 2072eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 208bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 209bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c2, c0, 2 @ TTB control register 21073b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r4, r4, #TTB_FLAGS 211bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r4, c2, c0, 1 @ load TTB1 212bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r10, #0x1f @ domains 0, 1 = manager 213bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c3, c0, 0 @ load domain access register 2142eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 215f80a3bb252cbb0959259328b9ab02b019123ed05Catalin Marinas ldr r5, =0xff0aa1a8 216f80a3bb252cbb0959259328b9ab02b019123ed05Catalin Marinas ldr r6, =0x40e040e0 2173f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r5, c10, c2, 0 @ write PRRR 2183f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r6, c10, c2, 1 @ write NMRR 2192eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas adr r5, v7_crval 2202eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas ldmia r5, {r5, r6} 2212eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas mrc p15, 0, r0, c1, c0, 0 @ read control register 2222eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas bic r0, r0, r5 @ clear bits them 2232eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas orr r0, r0, r6 @ set them 224bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr @ return to head.S:__ret 22593ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(__v7_setup) 226bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 227b1cce6b1b2785fd61454b47ceacb461815407662Russell King /* AT 228b1cce6b1b2785fd61454b47ceacb461815407662Russell King * TFR EV X F I D LR 229b1cce6b1b2785fd61454b47ceacb461815407662Russell King * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM 230b1cce6b1b2785fd61454b47ceacb461815407662Russell King * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 231b1cce6b1b2785fd61454b47ceacb461815407662Russell King * 1 0 110 0011 1.00 .111 1101 < we want 232bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 2332eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas .type v7_crval, #object 2342eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinasv7_crval: 2353f69c0c1af288d6b124d0a928a33b51061ebf850Russell King crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c 236bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 237bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup_stack: 238bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .space 4 * 11 @ 11 registers 239bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 240bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type v7_processor_functions, #object 241bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(v7_processor_functions) 242bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word v7_early_abort 2434a1fd556c1f1fbd6d9d6739efec042324732b697Catalin Marinas .word pabort_ifar 244bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_init 245bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_fin 246bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_reset 247bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_do_idle 248bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_dcache_clean_area 249bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_switch_mm 250bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_set_pte_ext 251bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size v7_processor_functions, . - v7_processor_functions 252bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 253bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_arch_name, #object 254bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_arch_name: 255bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "armv7" 256bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_arch_name, . - cpu_arch_name 257bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 258bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_elf_name, #object 259bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_elf_name: 260bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "v7" 261bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_elf_name, . - cpu_elf_name 262bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 263bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 264bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".proc.info.init", #alloc, #execinstr 265bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 266bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 267bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Match any ARMv7 processor core. 268bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 269bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type __v7_proc_info, #object 270bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_proc_info: 271bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Required ID value 272bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Mask for ID 273bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 274bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_BUFFERABLE | \ 275bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_CACHEABLE | \ 276bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 277bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_READ 278bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 279bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_XN | \ 280bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 281bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_READ 282bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas b __v7_setup 283bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_arch_name 284bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_elf_name 285bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 286bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_v7_name 287bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_processor_functions 2882ccdd1e77da52ad494e9af46bf272d816830cb28Catalin Marinas .long v7wbi_tlb_fns 289bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v6_user_fns 290bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_cache_fns 291bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size __v7_proc_info, . - __v7_proc_info 292