proc-v7.S revision 120ecfafabec382c4feb79ff159ef42a39b6d33b
1bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 2bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * linux/arch/arm/mm/proc-v7.S 3bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 4bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 6bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This program is free software; you can redistribute it and/or modify 7bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * it under the terms of the GNU General Public License version 2 as 8bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * published by the Free Software Foundation. 9bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 10bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This is the "shell" of the ARMv7 processor support. 11bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 12991da17ec0b9f396154c8120ffd10e5d7d7aa361Tim Abbott#include <linux/init.h> 13bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <linux/linkage.h> 14bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/assembler.h> 15bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/asm-offsets.h> 165ec9407dd1196daaf12b427b351e2cd62d2a16a7Russell King#include <asm/hwcap.h> 17bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable-hwdef.h> 18bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable.h> 19bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 20bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include "proc-macros.S" 21bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 221b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#ifdef CONFIG_ARM_LPAE 231b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#include "proc-v7-3level.S" 241b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#else 258d2cd3a38fd663bd341507f5ac29002ffd81d986Catalin Marinas#include "proc-v7-2level.S" 261b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#endif 2773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan 28bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_init) 29bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 3093ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_init) 31bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 32bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_fin) 331f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mrc p15, 0, r0, c1, c0, 0 @ ctrl register 341f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x1000 @ ...i............ 351f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x0006 @ .............ca. 361f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mcr p15, 0, r0, c1, c0, 0 @ disable caches 379ca03a21e320a6bf44559323527aba704bcc8772Russell King mov pc, lr 3893ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_fin) 39bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 40bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 41bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_reset(loc) 42bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 43bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Perform a soft reset of the system. Put the CPU into the 44bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * same state as it would be if it had been reset, and branch 45bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * to what would be the reset vector. 46bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 47bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - loc - location to jump to for soft reset 48f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon * 49f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon * This code must be executed using a flat identity mapping with 50f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon * caches disabled. 51bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 52bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 5 531a4baafa7d203da1cceb302c2df38f0fea1c17a1Will Deacon .pushsection .idmap.text, "ax" 54bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_reset) 55f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon mrc p15, 0, r1, c1, c0, 0 @ ctrl register 56f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon bic r1, r1, #0x1 @ ...............m 570f81bb6b051ad760686b5b0fef8c731282c16ef5Will Deacon THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) 58f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon mcr p15, 0, r1, c1, c0, 0 @ disable MMU 59f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon isb 60153cd8e839b5729358d4e5c3371e7509ee5ac96aDave Martin bx r0 6193ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_reset) 621a4baafa7d203da1cceb302c2df38f0fea1c17a1Will Deacon .popsection 63bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 64bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 65bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_do_idle() 66bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 67bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Idle the processor (eg, wait for interrupt). 68bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 69bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * IRQs are already disabled. 70bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 71bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_do_idle) 728553cb67d2318db327071018fc81084cbabccc46Catalin Marinas dsb @ WFI may enter a low-power mode 73000b50259271c9c14f6e175795f5164e1d51d35bCatalin Marinas wfi 74bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 7593ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_do_idle) 76bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 77bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_dcache_clean_area) 78bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifndef TLB_CAN_READ_FROM_L1_CACHE 79bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dcache_line_size r2, r3 80bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 81bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas add r0, r0, r2 82bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas subs r1, r1, r2 83bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bhi 1b 84bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 85bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 86bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 8793ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_dcache_clean_area) 88bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 8978a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin string cpu_v7_name, "ARMv7 Processor" 90bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 91bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 92f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 93f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King.globl cpu_v7_suspend_size 941b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas.equ cpu_v7_suspend_size, 4 * 8 9515e0d9e37c7fe9711b60f47221c394d45553ad8cArnd Bergmann#ifdef CONFIG_ARM_CPU_SUSPEND 96f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_v7_do_suspend) 97de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King stmfd sp!, {r4 - r10, lr} 98f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 991aede681ac159884c77817d33230eed9185b6f6cRussell King mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 1001aede681ac159884c77817d33230eed9185b6f6cRussell King stmia r0!, {r4 - r5} 101f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r6, c3, c0, 0 @ Domain ID 102de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r7, c2, c0, 1 @ TTB 1 1031b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas mrc p15, 0, r11, c2, c0, 2 @ TTB control register 104de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r8, c1, c0, 0 @ Control register 105de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register 106de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control 1071b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas stmia r0, {r6 - r11} 108de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ldmfd sp!, {r4 - r10, pc} 109f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_v7_do_suspend) 110f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 111f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_v7_do_resume) 112f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mov ip, #0 113f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 114f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 1151aede681ac159884c77817d33230eed9185b6f6cRussell King mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 1161aede681ac159884c77817d33230eed9185b6f6cRussell King ldmia r0!, {r4 - r5} 117f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 1181aede681ac159884c77817d33230eed9185b6f6cRussell King mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID 1191b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas ldmia r0, {r6 - r11} 120f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r6, c3, c0, 0 @ Domain ID 1211b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#ifndef CONFIG_ARM_LPAE 122de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 123de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 1241b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#endif 125de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r1, c2, c0, 0 @ TTB 0 126de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r7, c2, c0, 1 @ TTB 1 1271b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas mcr p15, 0, r11, c2, c0, 2 @ TTB control register 12825904157168ddc8841748a729914f00e53d7e049Russell King mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register 129de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King teq r4, r9 @ Is it already set? 130de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcrne p15, 0, r9, c1, c0, 1 @ No, so write it 131de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control 132f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r4, =PRRR @ PRRR 133f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r5, =NMRR @ NMRR 134f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r4, c10, c2, 0 @ write PRRR 135f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r5, c10, c2, 1 @ write NMRR 136f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King isb 137f35235a315a167e38e8e5bc9e476dcd7c932612cRussell King dsb 138de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mov r0, r8 @ control register 139f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King b cpu_resume_mmu 140f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_v7_do_resume) 141f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King#endif 142f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 1435085f3ff458521045f7e43da62b8c30ea7df2e82Russell King __CPUINIT 144bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 145bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 146bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * __v7_setup 147bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 148bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Initialise TLB, Caches, and MMU state ready to switch the MMU 149bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * on. Return in r0 the new CP15 C1 control register setting. 150bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 151bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This should be able to cover all ARMv7 cores. 152bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 153bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 154bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - cache type register is implemented 155bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 15615eb169bfec291faf25b158cfa9842b72f7803adPawel Moll__v7_ca5mp_setup: 15714eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker__v7_ca9mp_setup: 1587665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon mov r10, #(1 << 0) @ TLB ops broadcasting 1597665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon b 1f 160b4244738d20a631cd27fa105a2db71622618ab4ePawel Moll__v7_ca7mp_setup: 1617665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon__v7_ca15mp_setup: 1627665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon mov r10, #0 1637665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon1: 16473b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifdef CONFIG_SMP 165f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_SMP(mrc p15, 0, r0, c1, c0, 1) 166f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_UP(mov r0, #(1 << 6)) @ fake it for UP 1671b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 1687665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode 1697665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon orreq r0, r0, r10 @ Enable CPU-specific SMP bits 1707665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon mcreq p15, 0, r0, c1, c0, 1 17173b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 172d106de38ca927f2a53cd56ef94c506e8f6bd37e1Haojian Zhuang b __v7_setup 173de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 174de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT__v7_pj4b_setup: 175de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#ifdef CONFIG_CPU_PJ4B 176de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 177de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT/* Auxiliary Debug Modes Control 1 Register */ 178de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */ 179de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */ 180de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */ 181de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */ 182de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 183de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT/* Auxiliary Debug Modes Control 2 Register */ 184de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */ 185de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */ 186de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */ 187de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */ 188de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */ 189de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\ 190de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR) 191de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 192de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT/* Auxiliary Functional Modes Control Register 0 */ 193de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */ 194de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */ 195de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */ 196de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 197de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT/* Auxiliary Debug Modes Control 0 Register */ 198de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */ 199de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 200de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* Auxiliary Debug Modes Control 1 Register */ 201de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mrc p15, 1, r0, c15, c1, 1 202de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_CLEAN_LINE 203de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_BCK_OFF_STREX 204de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_INTER_PARITY 205de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT bic r0, r0, #PJ4B_STATIC_BP 206de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mcr p15, 1, r0, c15, c1, 1 207de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 208de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* Auxiliary Debug Modes Control 2 Register */ 209de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mrc p15, 1, r0, c15, c1, 2 210de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT bic r0, r0, #PJ4B_FAST_LDR 211de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_AUX_DBG_CTRL2 212de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mcr p15, 1, r0, c15, c1, 2 213de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 214de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* Auxiliary Functional Modes Control Register 0 */ 215de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mrc p15, 1, r0, c15, c2, 0 216de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#ifdef CONFIG_SMP 217de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_SMP_CFB 218de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#endif 219de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_L1_PAR_CHK 220de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_BROADCAST_CACHE 221de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mcr p15, 1, r0, c15, c2, 0 222de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 223de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* Auxiliary Debug Modes Control 0 Register */ 224de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mrc p15, 1, r0, c15, c1, 0 225de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT orr r0, r0, #PJ4B_WFI_WFE 226de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT mcr p15, 1, r0, c15, c1, 0 227de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 228de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT#endif /* CONFIG_CPU_PJ4B */ 229de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 23014eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker__v7_setup: 231bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas adr r12, __v7_setup_stack @ the local stack 232bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas stmia r12, {r0-r5, r7, r9, r11, lr} 2336323fa2256baa73d6a960ee57ec086b66aeecd0bSantosh Shilimkar bl v7_flush_dcache_louis 234bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldmia r12, {r0-r5, r7, r9, r11, lr} 2351946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 2361946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrc p15, 0, r0, c0, c0, 0 @ read main ID register 2371946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r10, r0, #0xff000000 @ ARM? 2381946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r10, #0x41000000 2399f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon bne 3f 2401946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r5, r0, #0x00f00000 @ variant 2411946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r6, r0, #0x0000000f @ revision 2426491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon orr r6, r6, r5, lsr #20-4 @ combine variant and revision 2436491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon ubfx r0, r0, #4, #12 @ primary part number 2441946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 2456491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon /* Cortex-A8 Errata */ 2466491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon ldr r10, =0x00000c08 @ Cortex-A8 primary part number 2476491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r0, r10 2486491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon bne 2f 24962e4d357aae0c7438c537bdb1c86909d7cac2663Rob Herring#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM) 25062e4d357aae0c7438c537bdb1c86909d7cac2663Rob Herring 2511946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r5, #0x00100000 @ only present in r1p* 2521946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 2531946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 6) @ set IBE to 1 2541946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 2557ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 256855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#ifdef CONFIG_ARM_ERRATA_458693 2576491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r6, #0x20 @ only present in r2p0 2581946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 2591946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 5) @ set L1NEON to 1 2601946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 2611946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 262855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#endif 2630516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#ifdef CONFIG_ARM_ERRATA_460075 2646491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r6, #0x20 @ only present in r2p0 2651946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 2661946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King tsteq r10, #1 << 22 2671946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 2681946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 2690516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#endif 2709f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon b 3f 2719f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon 2729f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon /* Cortex-A9 Errata */ 2739f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number 2749f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon teq r0, r10 2759f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon bne 3f 2769f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon#ifdef CONFIG_ARM_ERRATA_742230 2779f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon cmp r6, #0x22 @ only present up to r2p2 2789f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register 2799f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon orrle r10, r10, #1 << 4 @ set bit #4 2809f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register 2819f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon#endif 282a672e99b129e286df2e2697a1b603d82321117f3Will Deacon#ifdef CONFIG_ARM_ERRATA_742231 283a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teq r6, #0x20 @ present in r2p0 284a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teqne r6, #0x21 @ present in r2p1 285a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teqne r6, #0x22 @ present in r2p2 286a672e99b129e286df2e2697a1b603d82321117f3Will Deacon mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 287a672e99b129e286df2e2697a1b603d82321117f3Will Deacon orreq r10, r10, #1 << 12 @ set bit #12 288a672e99b129e286df2e2697a1b603d82321117f3Will Deacon orreq r10, r10, #1 << 22 @ set bit #22 289a672e99b129e286df2e2697a1b603d82321117f3Will Deacon mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 290a672e99b129e286df2e2697a1b603d82321117f3Will Deacon#endif 291475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon#ifdef CONFIG_ARM_ERRATA_743622 292efbc74ace95338484f8d732037b99c7c77098fceWill Deacon teq r5, #0x00200000 @ only present in r2p* 293475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 294475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon orreq r10, r10, #1 << 6 @ set bit #6 295475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 296475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon#endif 297ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) 298ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 299ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin ALT_UP_B(1f) 3009a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register 3019a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon orrlt r10, r10, #1 << 11 @ set bit #11 3029a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register 303ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin1: 3049a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon#endif 3051946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 3069f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon3: mov r10, #0 307bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 308bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 3092eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 310bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 3118d2cd3a38fd663bd341507f5ac29002ffd81d986Catalin Marinas v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup 312f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r5, =PRRR @ PRRR 313f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r6, =NMRR @ NMRR 3143f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r5, c10, c2, 0 @ write PRRR 3153f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r6, c10, c2, 1 @ write NMRR 316bdaaaec39792ee0035d6c5a5ad2520991e090a3cCatalin Marinas#endif 317078c04545ba56da21567728a909a496df5ff730dJonathan Austin#ifndef CONFIG_ARM_THUMBEE 318078c04545ba56da21567728a909a496df5ff730dJonathan Austin mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE 319078c04545ba56da21567728a909a496df5ff730dJonathan Austin and r0, r0, #(0xf << 12) @ ThumbEE enabled field 320078c04545ba56da21567728a909a496df5ff730dJonathan Austin teq r0, #(1 << 12) @ check if ThumbEE is present 321078c04545ba56da21567728a909a496df5ff730dJonathan Austin bne 1f 322078c04545ba56da21567728a909a496df5ff730dJonathan Austin mov r5, #0 323078c04545ba56da21567728a909a496df5ff730dJonathan Austin mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 324078c04545ba56da21567728a909a496df5ff730dJonathan Austin mrc p14, 6, r0, c0, c0, 0 @ load TEECR 325078c04545ba56da21567728a909a496df5ff730dJonathan Austin orr r0, r0, #1 @ set the 1st bit in order to 326078c04545ba56da21567728a909a496df5ff730dJonathan Austin mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access 327078c04545ba56da21567728a909a496df5ff730dJonathan Austin1: 328078c04545ba56da21567728a909a496df5ff730dJonathan Austin#endif 3292eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas adr r5, v7_crval 3302eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas ldmia r5, {r5, r6} 33126584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#ifdef CONFIG_CPU_ENDIAN_BE8 33226584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas orr r6, r6, #1 << 25 @ big-endian page tables 33326584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#endif 33464d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm#ifdef CONFIG_SWP_EMULATE 33564d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm orr r5, r5, #(1 << 10) @ set SW bit in "clear" 33664d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm bic r6, r6, #(1 << 10) @ clear it in "mmuset" 33764d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm#endif 3382eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas mrc p15, 0, r0, c1, c0, 0 @ read control register 3392eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas bic r0, r0, r5 @ clear bits them 3402eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas orr r0, r0, r6 @ set them 341347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 342bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr @ return to head.S:__ret 34393ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(__v7_setup) 344bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 3458d2cd3a38fd663bd341507f5ac29002ffd81d986Catalin Marinas .align 2 346bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup_stack: 347bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .space 4 * 11 @ 11 registers 348bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 3495085f3ff458521045f7e43da62b8c30ea7df2e82Russell King __INITDATA 3505085f3ff458521045f7e43da62b8c30ea7df2e82Russell King 35178a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 35278a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 353bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 3545085f3ff458521045f7e43da62b8c30ea7df2e82Russell King .section ".rodata" 3555085f3ff458521045f7e43da62b8c30ea7df2e82Russell King 35678a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin string cpu_arch_name, "armv7" 35778a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin string cpu_elf_name, "v7" 358bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 359bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 360bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".proc.info.init", #alloc, #execinstr 361bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 362dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll /* 363dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll * Standard v7 proc info content 364dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll */ 365dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 366dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 3671b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) 368dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 3691b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags) 3701b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \ 3711b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags 372dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll W(b) \initfunc 37314eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_arch_name 37414eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_elf_name 375dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ 376dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll HWCAP_EDSP | HWCAP_TLS | \hwcaps 37714eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_v7_name 37814eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7_processor_functions 37914eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7wbi_tlb_fns 38014eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v6_user_fns 38114eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7_cache_fns 382dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll.endm 383dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll 3841b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#ifndef CONFIG_ARM_LPAE 385dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll /* 38615eb169bfec291faf25b158cfa9842b72f7803adPawel Moll * ARM Ltd. Cortex A5 processor. 38715eb169bfec291faf25b158cfa9842b72f7803adPawel Moll */ 38815eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .type __v7_ca5mp_proc_info, #object 38915eb169bfec291faf25b158cfa9842b72f7803adPawel Moll__v7_ca5mp_proc_info: 39015eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .long 0x410fc050 39115eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .long 0xff0ffff0 39215eb169bfec291faf25b158cfa9842b72f7803adPawel Moll __v7_proc __v7_ca5mp_setup 39315eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info 39415eb169bfec291faf25b158cfa9842b72f7803adPawel Moll 39515eb169bfec291faf25b158cfa9842b72f7803adPawel Moll /* 396dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll * ARM Ltd. Cortex A9 processor. 397dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll */ 398dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .type __v7_ca9mp_proc_info, #object 399dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll__v7_ca9mp_proc_info: 400dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long 0x410fc090 401dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long 0xff0ffff0 402dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll __v7_proc __v7_ca9mp_setup 40314eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 404de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT 405de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT /* 406de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT * Marvell PJ4B processor. 407de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT */ 408de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT .type __v7_pj4b_proc_info, #object 409de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT__v7_pj4b_proc_info: 410de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT .long 0x562f5840 411de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT .long 0xfffffff0 412de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT __v7_proc __v7_pj4b_setup 413de4901933f6dfc0180f761790d3f47fc64e6270fGregory CLEMENT .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info 4141b6ba46b7efa31055eb993a6f2c6bbcb8b35b001Catalin Marinas#endif /* CONFIG_ARM_LPAE */ 41514eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker 416bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 417868dbf905245a524496a0535982ed21ad3be5585Will Deacon * ARM Ltd. Cortex A7 processor. 418868dbf905245a524496a0535982ed21ad3be5585Will Deacon */ 419868dbf905245a524496a0535982ed21ad3be5585Will Deacon .type __v7_ca7mp_proc_info, #object 420868dbf905245a524496a0535982ed21ad3be5585Will Deacon__v7_ca7mp_proc_info: 421868dbf905245a524496a0535982ed21ad3be5585Will Deacon .long 0x410fc070 422868dbf905245a524496a0535982ed21ad3be5585Will Deacon .long 0xff0ffff0 4238164f7af88d9ad3a757bd14f634b23997ee77f6bStephen Boyd __v7_proc __v7_ca7mp_setup 424868dbf905245a524496a0535982ed21ad3be5585Will Deacon .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info 425868dbf905245a524496a0535982ed21ad3be5585Will Deacon 426868dbf905245a524496a0535982ed21ad3be5585Will Deacon /* 4277665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon * ARM Ltd. Cortex A15 processor. 4287665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon */ 4297665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .type __v7_ca15mp_proc_info, #object 4307665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon__v7_ca15mp_proc_info: 4317665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .long 0x410fc0f0 4327665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .long 0xff0ffff0 4338164f7af88d9ad3a757bd14f634b23997ee77f6bStephen Boyd __v7_proc __v7_ca15mp_setup 4347665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info 4357665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon 4367665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon /* 437120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko * Qualcomm Inc. Krait processors. 438120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko */ 439120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko .type __krait_proc_info, #object 440120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko__krait_proc_info: 441120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko .long 0x510f0400 @ Required ID value 442120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko .long 0xff0ffc00 @ Mask for ID 443120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko /* 444120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko * Some Krait processors don't indicate support for SDIV and UDIV 445120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko * instructions in the ARM instruction set, even though they actually 446120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko * do support them. 447120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko */ 448120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko __v7_proc __v7_setup, hwcaps = HWCAP_IDIV 449120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko .size __krait_proc_info, . - __krait_proc_info 450120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko 451120ecfafabec382c4feb79ff159ef42a39b6d33bStepan Moskovchenko /* 452bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Match any ARMv7 processor core. 453bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 454bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type __v7_proc_info, #object 455bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_proc_info: 456bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Required ID value 457bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Mask for ID 458dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll __v7_proc __v7_setup 459bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size __v7_proc_info, . - __v7_proc_info 460