proc-v7.S revision 1f667c690be3ab71036c436d8391105eee23f65b
1bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 2bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * linux/arch/arm/mm/proc-v7.S 3bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 4bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 6bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This program is free software; you can redistribute it and/or modify 7bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * it under the terms of the GNU General Public License version 2 as 8bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * published by the Free Software Foundation. 9bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 10bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This is the "shell" of the ARMv7 processor support. 11bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 12991da17ec0b9f396154c8120ffd10e5d7d7aa361Tim Abbott#include <linux/init.h> 13bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <linux/linkage.h> 14bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/assembler.h> 15bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/asm-offsets.h> 165ec9407dd1196daaf12b427b351e2cd62d2a16a7Russell King#include <asm/hwcap.h> 17bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable-hwdef.h> 18bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable.h> 19bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 20bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include "proc-macros.S" 21bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 22bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_S (1 << 1) 2373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_NC (0 << 3) 2473b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_OC_WBWA (1 << 3) 25bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WT (2 << 3) 26bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WB (3 << 3) 27ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_NOS (1 << 5) 28ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 29ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 30ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 31ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 32bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 3373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifndef CONFIG_SMP 34ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 35ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB 364b46d6416548fb6a0940dfd9911fd895eb6247b3Russell King#define PMD_FLAGS PMD_SECT_WB 3773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#else 38ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 39ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 404b46d6416548fb6a0940dfd9911fd895eb6247b3Russell King#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S 4173b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 4273b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan 43bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_init) 44bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 4593ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_init) 46bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 47bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_fin) 481f667c690be3ab71036c436d8391105eee23f65bTony Lindgren stmfd sp!, {lr} 491f667c690be3ab71036c436d8391105eee23f65bTony Lindgren cpsid if @ disable interrupts 501f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bl v7_flush_kern_cache_all 511f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mrc p15, 0, r0, c1, c0, 0 @ ctrl register 521f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x1000 @ ...i............ 531f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x0006 @ .............ca. 541f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mcr p15, 0, r0, c1, c0, 0 @ disable caches 551f667c690be3ab71036c436d8391105eee23f65bTony Lindgren ldmfd sp!, {pc} 5693ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_fin) 57bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 58bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 59bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_reset(loc) 60bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 61bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Perform a soft reset of the system. Put the CPU into the 62bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * same state as it would be if it had been reset, and branch 63bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * to what would be the reset vector. 64bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 65bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - loc - location to jump to for soft reset 66bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 67bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 68bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 69bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 5 70bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_reset) 71bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, r0 7293ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_reset) 73bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 74bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 75bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_do_idle() 76bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 77bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Idle the processor (eg, wait for interrupt). 78bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 79bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * IRQs are already disabled. 80bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 81bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_do_idle) 828553cb67d2318db327071018fc81084cbabccc46Catalin Marinas dsb @ WFI may enter a low-power mode 83000b50259271c9c14f6e175795f5164e1d51d35bCatalin Marinas wfi 84bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 8593ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_do_idle) 86bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 87bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_dcache_clean_area) 88bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifndef TLB_CAN_READ_FROM_L1_CACHE 89bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dcache_line_size r2, r3 90bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 91bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas add r0, r0, r2 92bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas subs r1, r1, r2 93bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bhi 1b 94bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 95bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 96bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 9793ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_dcache_clean_area) 98bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 99bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 100bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_switch_mm(pgd_phys, tsk) 101bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 102bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set the translation table base pointer to be pgd_phys 103bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 104bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pgd_phys - physical address of new TTB 105bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 106bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 107bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - we are not using split page tables 108bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 109bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_switch_mm) 1102eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 111bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r2, #0 112bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 11373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r0, r0, #TTB_FLAGS 1147ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#ifdef CONFIG_ARM_ERRATA_430973 1157ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 1167ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 117bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 118bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 119bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 120bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 121bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r1, c13, c0, 1 @ set context ID 122bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 1232eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 124bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 12593ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_switch_mm) 126bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 127bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 128bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_set_pte_ext(ptep, pte) 129bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 130bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set a level 2 translation table entry. 131bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 132bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ptep - pointer to level 2 translation table entry 133bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * (hardware version is stored at -1024 bytes) 134bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pte - PTE value to store 135bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ext - value for extended PTE bits 136bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 137bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_set_pte_ext) 1382eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 139347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas ARM( str r1, [r0], #-2048 ) @ linux version 140347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas THUMB( str r1, [r0] ) @ linux version 141347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas THUMB( sub r0, r0, #2048 ) 142bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 143bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bic r3, r1, #0x000003f0 1443f69c0c1af288d6b124d0a928a33b51061ebf850Russell King bic r3, r3, #PTE_TYPE_MASK 145bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, r2 146bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, #PTE_EXT_AP0 | 2 147bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 148b1cce6b1b2785fd61454b47ceacb461815407662Russell King tst r1, #1 << 4 1493f69c0c1af288d6b124d0a928a33b51061ebf850Russell King orrne r3, r3, #PTE_EXT_TEX(1) 1503f69c0c1af288d6b124d0a928a33b51061ebf850Russell King 151bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_WRITE 152bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r1, #L_PTE_DIRTY 153bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_APX 154bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 155bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_USER 156bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orrne r3, r3, #PTE_EXT_AP1 157bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r3, #PTE_EXT_APX 158bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 159bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 160bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_EXEC 161bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_XN 162bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 1633f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tst r1, #L_PTE_YOUNG 1643f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tstne r1, #L_PTE_PRESENT 165bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas moveq r3, #0 166bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 167bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas str r3, [r0] 168bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r0, c7, c10, 1 @ flush_pte 1692eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 170bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 17193ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_set_pte_ext) 172bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 173bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_v7_name: 174bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .ascii "ARMv7 Processor" 175bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 176bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 177991da17ec0b9f396154c8120ffd10e5d7d7aa361Tim Abbott __INIT 178bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 179bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 180bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * __v7_setup 181bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 182bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Initialise TLB, Caches, and MMU state ready to switch the MMU 183bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * on. Return in r0 the new CP15 C1 control register setting. 184bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 185bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * We automatically detect if we have a Harvard cache, and use the 186bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Harvard cache control instructions insead of the unified cache 187bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * control instructions. 188bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 189bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This should be able to cover all ARMv7 cores. 190bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 191bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 192bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - cache type register is implemented 193bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 194bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup: 19573b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifdef CONFIG_SMP 1961b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson mrc p15, 0, r0, c1, c0, 1 1971b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 1981b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and 1991b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting 20073b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 201bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas adr r12, __v7_setup_stack @ the local stack 202bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas stmia r12, {r0-r5, r7, r9, r11, lr} 203bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bl v7_flush_dcache_all 204bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldmia r12, {r0-r5, r7, r9, r11, lr} 2051946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 2061946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrc p15, 0, r0, c0, c0, 0 @ read main ID register 2071946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r10, r0, #0xff000000 @ ARM? 2081946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r10, #0x41000000 2091946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King bne 2f 2101946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r5, r0, #0x00f00000 @ variant 2111946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r6, r0, #0x0000000f @ revision 2121946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orr r0, r6, r5, lsr #20-4 @ combine variant and revision 2131946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 2147ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#ifdef CONFIG_ARM_ERRATA_430973 2151946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r5, #0x00100000 @ only present in r1p* 2161946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 2171946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 6) @ set IBE to 1 2181946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 2197ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 220855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#ifdef CONFIG_ARM_ERRATA_458693 2211946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r0, #0x20 @ only present in r2p0 2221946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 2231946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 5) @ set L1NEON to 1 2241946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 2251946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 226855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#endif 2270516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#ifdef CONFIG_ARM_ERRATA_460075 2281946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r0, #0x20 @ only present in r2p0 2291946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 2301946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King tsteq r10, #1 << 22 2311946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 2321946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 2330516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#endif 2341946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 2351946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King2: mov r10, #0 236bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifdef HARVARD_CACHE 237bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 238bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 239bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 2402eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 241bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 242bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c2, c0, 2 @ TTB control register 24373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r4, r4, #TTB_FLAGS 244bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r4, c2, c0, 1 @ load TTB1 245bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r10, #0x1f @ domains 0, 1 = manager 246bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c3, c0, 0 @ load domain access register 24723d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas /* 24823d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * Memory region attributes with SCTLR.TRE=1 24923d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * 25023d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * n = TEX[0],C,B 25123d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * TR = PRRR[2n+1:2n] - memory type 25223d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * IR = NMRR[2n+1:2n] - inner cacheable property 25323d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * OR = NMRR[2n+17:2n+16] - outer cacheable property 25423d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * 25523d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * n TR IR OR 25623d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * UNCACHED 000 00 25723d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * BUFFERABLE 001 10 00 00 25823d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * WRITETHROUGH 010 10 10 10 25923d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * WRITEBACK 011 10 11 11 26023d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * reserved 110 26123d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * WRITEALLOC 111 10 01 01 26223d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DEV_SHARED 100 01 26323d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DEV_NONSHARED 100 01 26423d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DEV_WC 001 10 26523d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DEV_CACHED 011 10 26623d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * 26723d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * Other attributes: 26823d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * 26923d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DS0 = PRRR[16] = 0 - device shareable property 27023d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DS1 = PRRR[17] = 1 - device shareable property 27123d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * NS0 = PRRR[18] = 0 - normal shareable property 27223d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * NS1 = PRRR[19] = 1 - normal shareable property 27323d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * NOS = PRRR[24+n] = 1 - not outer shareable 27423d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas */ 27523d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas ldr r5, =0xff0a81a8 @ PRRR 27623d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas ldr r6, =0x40e040e0 @ NMRR 2773f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r5, c10, c2, 0 @ write PRRR 2783f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r6, c10, c2, 1 @ write NMRR 279bdaaaec39792ee0035d6c5a5ad2520991e090a3cCatalin Marinas#endif 2802eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas adr r5, v7_crval 2812eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas ldmia r5, {r5, r6} 28226584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#ifdef CONFIG_CPU_ENDIAN_BE8 28326584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas orr r6, r6, #1 << 25 @ big-endian page tables 28426584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#endif 2852eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas mrc p15, 0, r0, c1, c0, 0 @ read control register 2862eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas bic r0, r0, r5 @ clear bits them 2872eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas orr r0, r0, r6 @ set them 288347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 289bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr @ return to head.S:__ret 29093ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(__v7_setup) 291bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 292b1cce6b1b2785fd61454b47ceacb461815407662Russell King /* AT 293213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas * TFR EV X F I D LR S 294213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM 295b1cce6b1b2785fd61454b47ceacb461815407662Russell King * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 296213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas * 1 0 110 0011 1100 .111 1101 < we want 297bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 2982eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas .type v7_crval, #object 2992eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinasv7_crval: 300213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 301bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 302bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup_stack: 303bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .space 4 * 11 @ 11 registers 304bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 305bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type v7_processor_functions, #object 306bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(v7_processor_functions) 307bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word v7_early_abort 3084fb2847437d871fe579f820ceb18031db3359901Kirill A. Shutemov .word v7_pabort 309bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_init 310bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_fin 311bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_reset 312bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_do_idle 313bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_dcache_clean_area 314bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_switch_mm 315bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_set_pte_ext 316bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size v7_processor_functions, . - v7_processor_functions 317bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 318bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_arch_name, #object 319bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_arch_name: 320bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "armv7" 321bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_arch_name, . - cpu_arch_name 322bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 323bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_elf_name, #object 324bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_elf_name: 325bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "v7" 326bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_elf_name, . - cpu_elf_name 327bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 328bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 329bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".proc.info.init", #alloc, #execinstr 330bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 331bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 332bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Match any ARMv7 processor core. 333bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 334bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type __v7_proc_info, #object 335bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_proc_info: 336bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Required ID value 337bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Mask for ID 338bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 339bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 3404b46d6416548fb6a0940dfd9911fd895eb6247b3Russell King PMD_SECT_AP_READ | \ 3414b46d6416548fb6a0940dfd9911fd895eb6247b3Russell King PMD_FLAGS 342bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 343bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_XN | \ 344bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 345bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_READ 346bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas b __v7_setup 347bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_arch_name 348bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_elf_name 349bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 350bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_v7_name 351bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_processor_functions 3522ccdd1e77da52ad494e9af46bf272d816830cb28Catalin Marinas .long v7wbi_tlb_fns 353bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v6_user_fns 354bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_cache_fns 355bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size __v7_proc_info, . - __v7_proc_info 356