proc-v7.S revision 2eb8c82bc492d5f185150e63eba5eac4dff24178
1bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 2bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * linux/arch/arm/mm/proc-v7.S 3bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 4bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 6bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This program is free software; you can redistribute it and/or modify 7bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * it under the terms of the GNU General Public License version 2 as 8bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * published by the Free Software Foundation. 9bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 10bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This is the "shell" of the ARMv7 processor support. 11bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 12bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <linux/linkage.h> 13bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/assembler.h> 14bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/asm-offsets.h> 15bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/elf.h> 16bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable-hwdef.h> 17bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable.h> 18bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 19bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include "proc-macros.S" 20bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 21bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_C (1 << 0) 22bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_S (1 << 1) 23bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WT (2 << 3) 24bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WB (3 << 3) 25bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 26bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_init) 27bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 28bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 29bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_fin) 30bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 31bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 32bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 33bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_reset(loc) 34bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 35bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Perform a soft reset of the system. Put the CPU into the 36bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * same state as it would be if it had been reset, and branch 37bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * to what would be the reset vector. 38bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 39bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - loc - location to jump to for soft reset 40bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 41bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 42bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 43bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 5 44bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_reset) 45bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, r0 46bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 47bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 48bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_do_idle() 49bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 50bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Idle the processor (eg, wait for interrupt). 51bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 52bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * IRQs are already disabled. 53bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 54bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_do_idle) 55bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0xe320f003 @ ARM V7 WFI instruction 56bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 57bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 58bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_dcache_clean_area) 59bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifndef TLB_CAN_READ_FROM_L1_CACHE 60bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dcache_line_size r2, r3 61bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 62bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas add r0, r0, r2 63bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas subs r1, r1, r2 64bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bhi 1b 65bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 66bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 67bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 68bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 69bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 70bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_switch_mm(pgd_phys, tsk) 71bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 72bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set the translation table base pointer to be pgd_phys 73bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 74bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pgd_phys - physical address of new TTB 75bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 76bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 77bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - we are not using split page tables 78bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 79bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_switch_mm) 802eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 81bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r2, #0 82bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 83bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB 84bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 85bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 86bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 87bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 88bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r1, c13, c0, 1 @ set context ID 89bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 902eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 91bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 92bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 93bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 94bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_set_pte_ext(ptep, pte) 95bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 96bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set a level 2 translation table entry. 97bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 98bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ptep - pointer to level 2 translation table entry 99bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * (hardware version is stored at -1024 bytes) 100bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pte - PTE value to store 101bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ext - value for extended PTE bits 102bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 103bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Permissions: 104bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * YUWD APX AP1 AP0 SVC User 105bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 0xxx 0 0 0 no acc no acc 106bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 100x 1 0 1 r/o no acc 107bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 10x0 1 0 1 r/o no acc 108bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 1011 0 0 1 r/w no acc 109bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 110x 0 1 0 r/w r/o 110bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 11x0 0 1 0 r/w r/o 111bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 1111 0 1 1 r/w r/w 112bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 113bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_set_pte_ext) 1142eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 115bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas str r1, [r0], #-2048 @ linux version 116bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 117bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bic r3, r1, #0x000003f0 118bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bic r3, r3, #0x00000003 119bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, r2 120bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, #PTE_EXT_AP0 | 2 121bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 122bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_WRITE 123bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r1, #L_PTE_DIRTY 124bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_APX 125bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 126bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_USER 127bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orrne r3, r3, #PTE_EXT_AP1 128bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r3, #PTE_EXT_APX 129bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 130bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 131bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_YOUNG 132bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK 133bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 134bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_EXEC 135bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_XN 136bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 137bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_PRESENT 138bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas moveq r3, #0 139bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 140bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas str r3, [r0] 141bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r0, c7, c10, 1 @ flush_pte 1422eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 143bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 144bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 145bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_v7_name: 146bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .ascii "ARMv7 Processor" 147bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 148bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 149bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".text.init", #alloc, #execinstr 150bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 151bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 152bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * __v7_setup 153bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 154bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Initialise TLB, Caches, and MMU state ready to switch the MMU 155bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * on. Return in r0 the new CP15 C1 control register setting. 156bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 157bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * We automatically detect if we have a Harvard cache, and use the 158bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Harvard cache control instructions insead of the unified cache 159bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * control instructions. 160bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 161bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This should be able to cover all ARMv7 cores. 162bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 163bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 164bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - cache type register is implemented 165bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 166bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup: 167bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas adr r12, __v7_setup_stack @ the local stack 168bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas stmia r12, {r0-r5, r7, r9, r11, lr} 169bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bl v7_flush_dcache_all 170bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldmia r12, {r0-r5, r7, r9, r11, lr} 171bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r10, #0 172bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifdef HARVARD_CACHE 173bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 174bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 175bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 1762eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 177bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 178bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c2, c0, 2 @ TTB control register 179bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB 180bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r4, c2, c0, 0 @ load TTB0 181bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r4, c2, c0, 1 @ load TTB1 182bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r10, #0x1f @ domains 0, 1 = manager 183bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c3, c0, 0 @ load domain access register 1842eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 1852eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas adr r5, v7_crval 1862eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas ldmia r5, {r5, r6} 1872eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas mrc p15, 0, r0, c1, c0, 0 @ read control register 1882eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas bic r0, r0, r5 @ clear bits them 1892eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas orr r0, r0, r6 @ set them 190bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr @ return to head.S:__ret 191bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 192bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 193bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * V X F I D LR 194bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM 195bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 196bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 0 110 0011 1.00 .111 1101 < we want 197bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 1982eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas .type v7_crval, #object 1992eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinasv7_crval: 2002eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c 201bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 202bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup_stack: 203bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .space 4 * 11 @ 11 registers 204bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 205bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type v7_processor_functions, #object 206bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(v7_processor_functions) 207bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word v7_early_abort 208bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_init 209bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_fin 210bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_reset 211bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_do_idle 212bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_dcache_clean_area 213bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_switch_mm 214bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_set_pte_ext 215bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size v7_processor_functions, . - v7_processor_functions 216bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 217bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_arch_name, #object 218bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_arch_name: 219bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "armv7" 220bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_arch_name, . - cpu_arch_name 221bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 222bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_elf_name, #object 223bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_elf_name: 224bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "v7" 225bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_elf_name, . - cpu_elf_name 226bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 227bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 228bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".proc.info.init", #alloc, #execinstr 229bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 230bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 231bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Match any ARMv7 processor core. 232bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 233bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type __v7_proc_info, #object 234bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_proc_info: 235bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Required ID value 236bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Mask for ID 237bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 238bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_BUFFERABLE | \ 239bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_CACHEABLE | \ 240bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 241bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_READ 242bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 243bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_XN | \ 244bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 245bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_READ 246bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas b __v7_setup 247bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_arch_name 248bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_elf_name 249bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 250bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_v7_name 251bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_processor_functions 2522ccdd1e77da52ad494e9af46bf272d816830cb28Catalin Marinas .long v7wbi_tlb_fns 253bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v6_user_fns 254bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_cache_fns 255bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size __v7_proc_info, . - __v7_proc_info 256