proc-v7.S revision 475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2d
1bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 2bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * linux/arch/arm/mm/proc-v7.S 3bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 4bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 6bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This program is free software; you can redistribute it and/or modify 7bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * it under the terms of the GNU General Public License version 2 as 8bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * published by the Free Software Foundation. 9bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 10bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This is the "shell" of the ARMv7 processor support. 11bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 12991da17ec0b9f396154c8120ffd10e5d7d7aa361Tim Abbott#include <linux/init.h> 13bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <linux/linkage.h> 14bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/assembler.h> 15bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/asm-offsets.h> 165ec9407dd1196daaf12b427b351e2cd62d2a16a7Russell King#include <asm/hwcap.h> 17bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable-hwdef.h> 18bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable.h> 19bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 20bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include "proc-macros.S" 21bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 22bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_S (1 << 1) 2373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_NC (0 << 3) 2473b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_OC_WBWA (1 << 3) 25bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WT (2 << 3) 26bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WB (3 << 3) 27ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_NOS (1 << 5) 28ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 29ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 30ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 31ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 32bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 3373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifndef CONFIG_SMP 34ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 35ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB 364b46d6416548fb6a0940dfd9911fd895eb6247b3Russell King#define PMD_FLAGS PMD_SECT_WB 3773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#else 38ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 39ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 404b46d6416548fb6a0940dfd9911fd895eb6247b3Russell King#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S 4173b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 4273b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan 43bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_init) 44bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 4593ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_init) 46bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 47bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_fin) 481f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mrc p15, 0, r0, c1, c0, 0 @ ctrl register 491f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x1000 @ ...i............ 501f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x0006 @ .............ca. 511f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mcr p15, 0, r0, c1, c0, 0 @ disable caches 529ca03a21e320a6bf44559323527aba704bcc8772Russell King mov pc, lr 5393ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_fin) 54bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 55bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 56bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_reset(loc) 57bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 58bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Perform a soft reset of the system. Put the CPU into the 59bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * same state as it would be if it had been reset, and branch 60bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * to what would be the reset vector. 61bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 62bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - loc - location to jump to for soft reset 63bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 64bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 5 65bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_reset) 66bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, r0 6793ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_reset) 68bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 69bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 70bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_do_idle() 71bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 72bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Idle the processor (eg, wait for interrupt). 73bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 74bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * IRQs are already disabled. 75bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 76bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_do_idle) 778553cb67d2318db327071018fc81084cbabccc46Catalin Marinas dsb @ WFI may enter a low-power mode 78000b50259271c9c14f6e175795f5164e1d51d35bCatalin Marinas wfi 79bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 8093ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_do_idle) 81bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 82bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_dcache_clean_area) 83bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifndef TLB_CAN_READ_FROM_L1_CACHE 84bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dcache_line_size r2, r3 85bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 86bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas add r0, r0, r2 87bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas subs r1, r1, r2 88bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bhi 1b 89bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 90bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 91bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 9293ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_dcache_clean_area) 93bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 94bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 95bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_switch_mm(pgd_phys, tsk) 96bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 97bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set the translation table base pointer to be pgd_phys 98bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 99bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pgd_phys - physical address of new TTB 100bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 101bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 102bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - we are not using split page tables 103bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 104bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_switch_mm) 1052eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 106bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r2, #0 107bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 10873b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r0, r0, #TTB_FLAGS 1097ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#ifdef CONFIG_ARM_ERRATA_430973 1107ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 1117ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 112bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 113bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 114bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 115bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 116bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r1, c13, c0, 1 @ set context ID 117bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 1182eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 119bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 12093ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_switch_mm) 121bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 122bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 123bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_set_pte_ext(ptep, pte) 124bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 125bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set a level 2 translation table entry. 126bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 127bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ptep - pointer to level 2 translation table entry 128bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * (hardware version is stored at -1024 bytes) 129bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pte - PTE value to store 130bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ext - value for extended PTE bits 131bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 132bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_set_pte_ext) 1332eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 134347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas ARM( str r1, [r0], #-2048 ) @ linux version 135347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas THUMB( str r1, [r0] ) @ linux version 136347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas THUMB( sub r0, r0, #2048 ) 137bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 138bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bic r3, r1, #0x000003f0 1393f69c0c1af288d6b124d0a928a33b51061ebf850Russell King bic r3, r3, #PTE_TYPE_MASK 140bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, r2 141bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, #PTE_EXT_AP0 | 2 142bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 143b1cce6b1b2785fd61454b47ceacb461815407662Russell King tst r1, #1 << 4 1443f69c0c1af288d6b124d0a928a33b51061ebf850Russell King orrne r3, r3, #PTE_EXT_TEX(1) 1453f69c0c1af288d6b124d0a928a33b51061ebf850Russell King 146bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_WRITE 147bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r1, #L_PTE_DIRTY 148bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_APX 149bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 150bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_USER 151bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orrne r3, r3, #PTE_EXT_AP1 152bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r3, #PTE_EXT_APX 153bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 154bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 155bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_EXEC 156bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_XN 157bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 1583f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tst r1, #L_PTE_YOUNG 1593f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tstne r1, #L_PTE_PRESENT 160bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas moveq r3, #0 161bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 162bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas str r3, [r0] 163bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r0, c7, c10, 1 @ flush_pte 1642eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 165bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 16693ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_set_pte_ext) 167bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 168bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_v7_name: 169bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .ascii "ARMv7 Processor" 170bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 171bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 172991da17ec0b9f396154c8120ffd10e5d7d7aa361Tim Abbott __INIT 173bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 174bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 175bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * __v7_setup 176bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 177bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Initialise TLB, Caches, and MMU state ready to switch the MMU 178bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * on. Return in r0 the new CP15 C1 control register setting. 179bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 180bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * We automatically detect if we have a Harvard cache, and use the 181bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Harvard cache control instructions insead of the unified cache 182bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * control instructions. 183bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 184bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This should be able to cover all ARMv7 cores. 185bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 186bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 187bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - cache type register is implemented 188bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 18914eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker__v7_ca9mp_setup: 19073b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifdef CONFIG_SMP 1911b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson mrc p15, 0, r0, c1, c0, 1 1921b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 1931b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and 1941b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting 19573b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 19614eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker__v7_setup: 197bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas adr r12, __v7_setup_stack @ the local stack 198bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas stmia r12, {r0-r5, r7, r9, r11, lr} 199bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bl v7_flush_dcache_all 200bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldmia r12, {r0-r5, r7, r9, r11, lr} 2011946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 2021946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrc p15, 0, r0, c0, c0, 0 @ read main ID register 2031946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r10, r0, #0xff000000 @ ARM? 2041946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r10, #0x41000000 2059f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon bne 3f 2061946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r5, r0, #0x00f00000 @ variant 2071946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r6, r0, #0x0000000f @ revision 2086491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon orr r6, r6, r5, lsr #20-4 @ combine variant and revision 2096491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon ubfx r0, r0, #4, #12 @ primary part number 2101946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 2116491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon /* Cortex-A8 Errata */ 2126491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon ldr r10, =0x00000c08 @ Cortex-A8 primary part number 2136491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r0, r10 2146491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon bne 2f 2157ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#ifdef CONFIG_ARM_ERRATA_430973 2161946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r5, #0x00100000 @ only present in r1p* 2171946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 2181946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 6) @ set IBE to 1 2191946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 2207ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 221855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#ifdef CONFIG_ARM_ERRATA_458693 2226491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r6, #0x20 @ only present in r2p0 2231946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 2241946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 5) @ set L1NEON to 1 2251946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 2261946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 227855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#endif 2280516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#ifdef CONFIG_ARM_ERRATA_460075 2296491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r6, #0x20 @ only present in r2p0 2301946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 2311946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King tsteq r10, #1 << 22 2321946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 2331946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 2340516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#endif 2359f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon b 3f 2369f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon 2379f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon /* Cortex-A9 Errata */ 2389f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number 2399f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon teq r0, r10 2409f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon bne 3f 2419f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon#ifdef CONFIG_ARM_ERRATA_742230 2429f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon cmp r6, #0x22 @ only present up to r2p2 2439f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register 2449f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon orrle r10, r10, #1 << 4 @ set bit #4 2459f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register 2469f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon#endif 247a672e99b129e286df2e2697a1b603d82321117f3Will Deacon#ifdef CONFIG_ARM_ERRATA_742231 248a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teq r6, #0x20 @ present in r2p0 249a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teqne r6, #0x21 @ present in r2p1 250a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teqne r6, #0x22 @ present in r2p2 251a672e99b129e286df2e2697a1b603d82321117f3Will Deacon mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 252a672e99b129e286df2e2697a1b603d82321117f3Will Deacon orreq r10, r10, #1 << 12 @ set bit #12 253a672e99b129e286df2e2697a1b603d82321117f3Will Deacon orreq r10, r10, #1 << 22 @ set bit #22 254a672e99b129e286df2e2697a1b603d82321117f3Will Deacon mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 255a672e99b129e286df2e2697a1b603d82321117f3Will Deacon#endif 256475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon#ifdef CONFIG_ARM_ERRATA_743622 257475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon teq r6, #0x20 @ present in r2p0 258475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon teqne r6, #0x21 @ present in r2p1 259475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon teqne r6, #0x22 @ present in r2p2 260475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 261475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon orreq r10, r10, #1 << 6 @ set bit #6 262475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 263475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon#endif 2641946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 2659f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon3: mov r10, #0 266bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifdef HARVARD_CACHE 267bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 268bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 269bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 2702eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 271bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 272bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c2, c0, 2 @ TTB control register 27373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r4, r4, #TTB_FLAGS 274bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r4, c2, c0, 1 @ load TTB1 275bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r10, #0x1f @ domains 0, 1 = manager 276bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c3, c0, 0 @ load domain access register 27723d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas /* 27823d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * Memory region attributes with SCTLR.TRE=1 27923d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * 28023d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * n = TEX[0],C,B 28123d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * TR = PRRR[2n+1:2n] - memory type 28223d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * IR = NMRR[2n+1:2n] - inner cacheable property 28323d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * OR = NMRR[2n+17:2n+16] - outer cacheable property 28423d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * 28523d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * n TR IR OR 28623d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * UNCACHED 000 00 28723d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * BUFFERABLE 001 10 00 00 28823d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * WRITETHROUGH 010 10 10 10 28923d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * WRITEBACK 011 10 11 11 29023d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * reserved 110 29123d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * WRITEALLOC 111 10 01 01 29223d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DEV_SHARED 100 01 29323d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DEV_NONSHARED 100 01 29423d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DEV_WC 001 10 29523d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DEV_CACHED 011 10 29623d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * 29723d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * Other attributes: 29823d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * 29923d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DS0 = PRRR[16] = 0 - device shareable property 30023d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * DS1 = PRRR[17] = 1 - device shareable property 30123d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * NS0 = PRRR[18] = 0 - normal shareable property 30223d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * NS1 = PRRR[19] = 1 - normal shareable property 30323d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas * NOS = PRRR[24+n] = 1 - not outer shareable 30423d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas */ 30523d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas ldr r5, =0xff0a81a8 @ PRRR 30623d1c515d8fc6d74bea442a4b687c3b5b8627ec4Catalin Marinas ldr r6, =0x40e040e0 @ NMRR 3073f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r5, c10, c2, 0 @ write PRRR 3083f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r6, c10, c2, 1 @ write NMRR 309bdaaaec39792ee0035d6c5a5ad2520991e090a3cCatalin Marinas#endif 3102eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas adr r5, v7_crval 3112eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas ldmia r5, {r5, r6} 31226584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#ifdef CONFIG_CPU_ENDIAN_BE8 31326584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas orr r6, r6, #1 << 25 @ big-endian page tables 31426584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#endif 3152eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas mrc p15, 0, r0, c1, c0, 0 @ read control register 3162eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas bic r0, r0, r5 @ clear bits them 3172eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas orr r0, r0, r6 @ set them 318347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 319bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr @ return to head.S:__ret 32093ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(__v7_setup) 321bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 322b1cce6b1b2785fd61454b47ceacb461815407662Russell King /* AT 323213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas * TFR EV X F I D LR S 324213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM 325b1cce6b1b2785fd61454b47ceacb461815407662Russell King * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 326213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas * 1 0 110 0011 1100 .111 1101 < we want 327bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 3282eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas .type v7_crval, #object 3292eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinasv7_crval: 330213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 331bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 332bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup_stack: 333bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .space 4 * 11 @ 11 registers 334bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 335bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type v7_processor_functions, #object 336bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(v7_processor_functions) 337bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word v7_early_abort 3384fb2847437d871fe579f820ceb18031db3359901Kirill A. Shutemov .word v7_pabort 339bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_init 340bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_fin 341bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_reset 342bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_do_idle 343bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_dcache_clean_area 344bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_switch_mm 345bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_set_pte_ext 346bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size v7_processor_functions, . - v7_processor_functions 347bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 348bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_arch_name, #object 349bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_arch_name: 350bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "armv7" 351bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_arch_name, . - cpu_arch_name 352bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 353bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_elf_name, #object 354bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_elf_name: 355bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "v7" 356bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_elf_name, . - cpu_elf_name 357bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 358bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 359bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".proc.info.init", #alloc, #execinstr 360bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 36114eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .type __v7_ca9mp_proc_info, #object 36214eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker__v7_ca9mp_proc_info: 36314eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long 0x410fc090 @ Required ID value 36414eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long 0xff0ffff0 @ Mask for ID 36514eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long PMD_TYPE_SECT | \ 36614eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker PMD_SECT_AP_WRITE | \ 36714eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker PMD_SECT_AP_READ | \ 36814eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker PMD_FLAGS 36914eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long PMD_TYPE_SECT | \ 37014eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker PMD_SECT_XN | \ 37114eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker PMD_SECT_AP_WRITE | \ 37214eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker PMD_SECT_AP_READ 37314eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker b __v7_ca9mp_setup 37414eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_arch_name 37514eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_elf_name 37614eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 37714eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_v7_name 37814eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7_processor_functions 37914eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7wbi_tlb_fns 38014eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v6_user_fns 38114eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7_cache_fns 38214eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 38314eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker 384bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 385bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Match any ARMv7 processor core. 386bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 387bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type __v7_proc_info, #object 388bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_proc_info: 389bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Required ID value 390bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Mask for ID 391bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 392bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 3934b46d6416548fb6a0940dfd9911fd895eb6247b3Russell King PMD_SECT_AP_READ | \ 3944b46d6416548fb6a0940dfd9911fd895eb6247b3Russell King PMD_FLAGS 395bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 396bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_XN | \ 397bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 398bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_READ 399bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas b __v7_setup 400bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_arch_name 401bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_elf_name 402f159f4ed55bb0fa5470800641e03a13a7e0eae6eTony Lindgren .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS 403bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_v7_name 404bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_processor_functions 4052ccdd1e77da52ad494e9af46bf272d816830cb28Catalin Marinas .long v7wbi_tlb_fns 406bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v6_user_fns 407bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_cache_fns 408bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size __v7_proc_info, . - __v7_proc_info 409