proc-v7.S revision 8553cb67d2318db327071018fc81084cbabccc46
1bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 2bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * linux/arch/arm/mm/proc-v7.S 3bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 4bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 6bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This program is free software; you can redistribute it and/or modify 7bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * it under the terms of the GNU General Public License version 2 as 8bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * published by the Free Software Foundation. 9bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 10bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This is the "shell" of the ARMv7 processor support. 11bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 12bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <linux/linkage.h> 13bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/assembler.h> 14bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/asm-offsets.h> 155ec9407dd1196daaf12b427b351e2cd62d2a16a7Russell King#include <asm/hwcap.h> 16bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable-hwdef.h> 17bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable.h> 18bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 19bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include "proc-macros.S" 20bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 21bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_C (1 << 0) 22bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_S (1 << 1) 2373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_NC (0 << 3) 2473b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_OC_WBWA (1 << 3) 25bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WT (2 << 3) 26bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WB (3 << 3) 27bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 2873b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifndef CONFIG_SMP 2973b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB 3073b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#else 3173b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA 3273b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 3373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan 34bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_init) 35bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 3693ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_init) 37bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 38bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_fin) 39bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 4093ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_fin) 41bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 42bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 43bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_reset(loc) 44bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 45bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Perform a soft reset of the system. Put the CPU into the 46bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * same state as it would be if it had been reset, and branch 47bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * to what would be the reset vector. 48bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 49bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - loc - location to jump to for soft reset 50bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 51bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 52bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 53bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 5 54bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_reset) 55bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, r0 5693ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_reset) 57bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 58bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 59bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_do_idle() 60bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 61bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Idle the processor (eg, wait for interrupt). 62bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 63bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * IRQs are already disabled. 64bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 65bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_do_idle) 668553cb67d2318db327071018fc81084cbabccc46Catalin Marinas dsb @ WFI may enter a low-power mode 67000b50259271c9c14f6e175795f5164e1d51d35bCatalin Marinas wfi 68bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 6993ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_do_idle) 70bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 71bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_dcache_clean_area) 72bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifndef TLB_CAN_READ_FROM_L1_CACHE 73bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dcache_line_size r2, r3 74bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 75bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas add r0, r0, r2 76bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas subs r1, r1, r2 77bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bhi 1b 78bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 79bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 80bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 8193ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_dcache_clean_area) 82bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 83bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 84bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_switch_mm(pgd_phys, tsk) 85bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 86bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set the translation table base pointer to be pgd_phys 87bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 88bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pgd_phys - physical address of new TTB 89bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 90bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 91bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - we are not using split page tables 92bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 93bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_switch_mm) 942eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 95bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r2, #0 96bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 9773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r0, r0, #TTB_FLAGS 98bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 99bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 100bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 101bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 102bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r1, c13, c0, 1 @ set context ID 103bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 1042eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 105bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 10693ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_switch_mm) 107bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 108bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 109bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_set_pte_ext(ptep, pte) 110bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 111bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set a level 2 translation table entry. 112bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 113bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ptep - pointer to level 2 translation table entry 114bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * (hardware version is stored at -1024 bytes) 115bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pte - PTE value to store 116bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ext - value for extended PTE bits 117bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 118bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_set_pte_ext) 1192eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 120bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas str r1, [r0], #-2048 @ linux version 121bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 122bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bic r3, r1, #0x000003f0 1233f69c0c1af288d6b124d0a928a33b51061ebf850Russell King bic r3, r3, #PTE_TYPE_MASK 124bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, r2 125bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, #PTE_EXT_AP0 | 2 126bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 1273f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tst r2, #1 << 4 1283f69c0c1af288d6b124d0a928a33b51061ebf850Russell King orrne r3, r3, #PTE_EXT_TEX(1) 1293f69c0c1af288d6b124d0a928a33b51061ebf850Russell King 130bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_WRITE 131bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r1, #L_PTE_DIRTY 132bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_APX 133bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 134bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_USER 135bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orrne r3, r3, #PTE_EXT_AP1 136bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r3, #PTE_EXT_APX 137bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 138bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 139bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_EXEC 140bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orreq r3, r3, #PTE_EXT_XN 141bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 1423f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tst r1, #L_PTE_YOUNG 1433f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tstne r1, #L_PTE_PRESENT 144bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas moveq r3, #0 145bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 146bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas str r3, [r0] 147bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r0, c7, c10, 1 @ flush_pte 1482eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 149bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 15093ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_set_pte_ext) 151bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 152bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_v7_name: 153bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .ascii "ARMv7 Processor" 154bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 155bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 156bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".text.init", #alloc, #execinstr 157bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 158bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 159bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * __v7_setup 160bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 161bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Initialise TLB, Caches, and MMU state ready to switch the MMU 162bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * on. Return in r0 the new CP15 C1 control register setting. 163bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 164bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * We automatically detect if we have a Harvard cache, and use the 165bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Harvard cache control instructions insead of the unified cache 166bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * control instructions. 167bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 168bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This should be able to cover all ARMv7 cores. 169bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 170bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 171bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - cache type register is implemented 172bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 173bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup: 17473b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifdef CONFIG_SMP 17573b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode 17673b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r0, r0, #(0x1 << 6) 17773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan mcr p15, 0, r0, c1, c0, 1 17873b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 179bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas adr r12, __v7_setup_stack @ the local stack 180bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas stmia r12, {r0-r5, r7, r9, r11, lr} 181bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bl v7_flush_dcache_all 182bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldmia r12, {r0-r5, r7, r9, r11, lr} 183bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r10, #0 184bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifdef HARVARD_CACHE 185bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 186bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 187bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 1882eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 189bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 190bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c2, c0, 2 @ TTB control register 19173b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan orr r4, r4, #TTB_FLAGS 192bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r4, c2, c0, 1 @ load TTB1 193bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r10, #0x1f @ domains 0, 1 = manager 194bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c3, c0, 0 @ load domain access register 1952eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 196f80a3bb252cbb0959259328b9ab02b019123ed05Catalin Marinas ldr r5, =0xff0aa1a8 197f80a3bb252cbb0959259328b9ab02b019123ed05Catalin Marinas ldr r6, =0x40e040e0 1983f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r5, c10, c2, 0 @ write PRRR 1993f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r6, c10, c2, 1 @ write NMRR 2002eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas adr r5, v7_crval 2012eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas ldmia r5, {r5, r6} 2022eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas mrc p15, 0, r0, c1, c0, 0 @ read control register 2032eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas bic r0, r0, r5 @ clear bits them 2042eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas orr r0, r0, r6 @ set them 205bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr @ return to head.S:__ret 20693ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(__v7_setup) 207bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 208bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 209bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * V X F I D LR 210bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM 211bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 212bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 0 110 0011 1.00 .111 1101 < we want 213bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 2142eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas .type v7_crval, #object 2152eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinasv7_crval: 2163f69c0c1af288d6b124d0a928a33b51061ebf850Russell King crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c 217bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 218bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup_stack: 219bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .space 4 * 11 @ 11 registers 220bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 221bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type v7_processor_functions, #object 222bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(v7_processor_functions) 223bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word v7_early_abort 2244a1fd556c1f1fbd6d9d6739efec042324732b697Catalin Marinas .word pabort_ifar 225bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_init 226bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_proc_fin 227bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_reset 228bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_do_idle 229bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_dcache_clean_area 230bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_switch_mm 231bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .word cpu_v7_set_pte_ext 232bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size v7_processor_functions, . - v7_processor_functions 233bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 234bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_arch_name, #object 235bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_arch_name: 236bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "armv7" 237bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_arch_name, . - cpu_arch_name 238bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 239bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type cpu_elf_name, #object 240bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinascpu_elf_name: 241bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .asciz "v7" 242bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size cpu_elf_name, . - cpu_elf_name 243bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 244bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 245bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".proc.info.init", #alloc, #execinstr 246bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 247bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 248bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Match any ARMv7 processor core. 249bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 250bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type __v7_proc_info, #object 251bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_proc_info: 252bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Required ID value 253bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Mask for ID 254bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 255bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_BUFFERABLE | \ 256bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_CACHEABLE | \ 257bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 258bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_READ 259bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long PMD_TYPE_SECT | \ 260bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_XN | \ 261bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_WRITE | \ 262bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas PMD_SECT_AP_READ 263bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas b __v7_setup 264bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_arch_name 265bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_elf_name 266bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 267bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long cpu_v7_name 268bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_processor_functions 2692ccdd1e77da52ad494e9af46bf272d816830cb28Catalin Marinas .long v7wbi_tlb_fns 270bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v6_user_fns 271bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long v7_cache_fns 272bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size __v7_proc_info, . - __v7_proc_info 273