proc-v7.S revision ba90c516bae79b5f8184d915bfce7eb280af61b1
1bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 2bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * linux/arch/arm/mm/proc-v7.S 3bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 4bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 6bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This program is free software; you can redistribute it and/or modify 7bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * it under the terms of the GNU General Public License version 2 as 8bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * published by the Free Software Foundation. 9bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 10bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This is the "shell" of the ARMv7 processor support. 11bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 12991da17ec0b9f396154c8120ffd10e5d7d7aa361Tim Abbott#include <linux/init.h> 13bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <linux/linkage.h> 14bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/assembler.h> 15bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/asm-offsets.h> 165ec9407dd1196daaf12b427b351e2cd62d2a16a7Russell King#include <asm/hwcap.h> 17bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable-hwdef.h> 18bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include <asm/pgtable.h> 19bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 20bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#include "proc-macros.S" 21bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 22bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_S (1 << 1) 2373b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_NC (0 << 3) 2473b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#define TTB_RGN_OC_WBWA (1 << 3) 25bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WT (2 << 3) 26bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#define TTB_RGN_OC_WB (3 << 3) 27ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_NOS (1 << 5) 28ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 29ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 30ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 31ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 32bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 33ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 34f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB 35f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King#define PMD_FLAGS_UP PMD_SECT_WB 36f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King 37ba3c02636a0743a62cb50b920d36e1c046ab88cfTony Thompson/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 38f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 39f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S 4073b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan 41bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_init) 42bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 4393ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_init) 44bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 45bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_proc_fin) 461f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mrc p15, 0, r0, c1, c0, 0 @ ctrl register 471f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x1000 @ ...i............ 481f667c690be3ab71036c436d8391105eee23f65bTony Lindgren bic r0, r0, #0x0006 @ .............ca. 491f667c690be3ab71036c436d8391105eee23f65bTony Lindgren mcr p15, 0, r0, c1, c0, 0 @ disable caches 509ca03a21e320a6bf44559323527aba704bcc8772Russell King mov pc, lr 5193ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_proc_fin) 52bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 53bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 54bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_reset(loc) 55bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 56bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Perform a soft reset of the system. Put the CPU into the 57bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * same state as it would be if it had been reset, and branch 58bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * to what would be the reset vector. 59bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 60bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - loc - location to jump to for soft reset 61f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon * 62f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon * This code must be executed using a flat identity mapping with 63f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon * caches disabled. 64bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 65bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 5 66bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_reset) 67f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon mrc p15, 0, r1, c1, c0, 0 @ ctrl register 68f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon bic r1, r1, #0x1 @ ...............m 690f81bb6b051ad760686b5b0fef8c731282c16ef5Will Deacon THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) 70f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon mcr p15, 0, r1, c1, c0, 0 @ disable MMU 71f4daf06fc23b99df5ca5b3e892428b91e148cc52Will Deacon isb 72bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, r0 7393ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_reset) 74bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 75bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 76bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_do_idle() 77bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 78bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Idle the processor (eg, wait for interrupt). 79bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 80bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * IRQs are already disabled. 81bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 82bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_do_idle) 838553cb67d2318db327071018fc81084cbabccc46Catalin Marinas dsb @ WFI may enter a low-power mode 84000b50259271c9c14f6e175795f5164e1d51d35bCatalin Marinas wfi 85bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 8693ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_do_idle) 87bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 88bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_dcache_clean_area) 89bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifndef TLB_CAN_READ_FROM_L1_CACHE 90bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dcache_line_size r2, r3 91bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 92bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas add r0, r0, r2 93bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas subs r1, r1, r2 94bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bhi 1b 95bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 96bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 97bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 9893ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_dcache_clean_area) 99bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 100bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 101bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_switch_mm(pgd_phys, tsk) 102bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 103bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set the translation table base pointer to be pgd_phys 104bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 105bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pgd_phys - physical address of new TTB 106bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 107bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 108bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - we are not using split page tables 109bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 110bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_switch_mm) 1112eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 112bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov r2, #0 113bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 114f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 115f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 1167ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#ifdef CONFIG_ARM_ERRATA_430973 1177ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 1187ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 11907989b7ad63af424886ff922fd3bcca9e00ffa78Russell King#ifdef CONFIG_ARM_ERRATA_754322 12007989b7ad63af424886ff922fd3bcca9e00ffa78Russell King dsb 12107989b7ad63af424886ff922fd3bcca9e00ffa78Russell King#endif 12207989b7ad63af424886ff922fd3bcca9e00ffa78Russell King mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 12307989b7ad63af424886ff922fd3bcca9e00ffa78Russell King isb 12407989b7ad63af424886ff922fd3bcca9e00ffa78Russell King1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 125bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 126fcbdc5fe6ebe07d502c9b652cb63376bcc4227acWill Deacon#ifdef CONFIG_ARM_ERRATA_754322 127fcbdc5fe6ebe07d502c9b652cb63376bcc4227acWill Deacon dsb 128fcbdc5fe6ebe07d502c9b652cb63376bcc4227acWill Deacon#endif 129bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r1, c13, c0, 1 @ set context ID 130bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas isb 1312eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 132bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 13393ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_switch_mm) 134bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 135bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 136bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * cpu_v7_set_pte_ext(ptep, pte) 137bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 138bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Set a level 2 translation table entry. 139bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 140bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ptep - pointer to level 2 translation table entry 141d30e45eeabefadc6039d7f876a59e5f5f6cb11c6Russell King * (hardware version is stored at +2048 bytes) 142bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - pte - PTE value to store 143bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - ext - value for extended PTE bits 144bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 145bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin MarinasENTRY(cpu_v7_set_pte_ext) 1462eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 147d30e45eeabefadc6039d7f876a59e5f5f6cb11c6Russell King str r1, [r0] @ linux version 148bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 149bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bic r3, r1, #0x000003f0 1503f69c0c1af288d6b124d0a928a33b51061ebf850Russell King bic r3, r3, #PTE_TYPE_MASK 151bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, r2 152bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orr r3, r3, #PTE_EXT_AP0 | 2 153bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 154b1cce6b1b2785fd61454b47ceacb461815407662Russell King tst r1, #1 << 4 1553f69c0c1af288d6b124d0a928a33b51061ebf850Russell King orrne r3, r3, #PTE_EXT_TEX(1) 1563f69c0c1af288d6b124d0a928a33b51061ebf850Russell King 15736bb94ba36f332de767cfaa3af6a5136435a3a9cRussell King eor r1, r1, #L_PTE_DIRTY 15836bb94ba36f332de767cfaa3af6a5136435a3a9cRussell King tst r1, #L_PTE_RDONLY | L_PTE_DIRTY 15936bb94ba36f332de767cfaa3af6a5136435a3a9cRussell King orrne r3, r3, #PTE_EXT_APX 160bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 161bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tst r1, #L_PTE_USER 162bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas orrne r3, r3, #PTE_EXT_AP1 163247055aa21ffef1c49dd64710d5e94c2aee19b58Catalin Marinas#ifdef CONFIG_CPU_USE_DOMAINS 164247055aa21ffef1c49dd64710d5e94c2aee19b58Catalin Marinas @ allow kernel read/write access to read-only user pages 165bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas tstne r3, #PTE_EXT_APX 166bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 167247055aa21ffef1c49dd64710d5e94c2aee19b58Catalin Marinas#endif 168bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 1699522d7e4cb5e0858122fc55d33a2c07728f0b10dRussell King tst r1, #L_PTE_XN 1709522d7e4cb5e0858122fc55d33a2c07728f0b10dRussell King orrne r3, r3, #PTE_EXT_XN 171bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 1723f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tst r1, #L_PTE_YOUNG 1733f69c0c1af288d6b124d0a928a33b51061ebf850Russell King tstne r1, #L_PTE_PRESENT 174bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas moveq r3, #0 175bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 176874d5d3ccc04c0659b76b05ee0c761f568062cb1Dave Martin ARM( str r3, [r0, #2048]! ) 177874d5d3ccc04c0659b76b05ee0c761f568062cb1Dave Martin THUMB( add r0, r0, #2048 ) 178874d5d3ccc04c0659b76b05ee0c761f568062cb1Dave Martin THUMB( str r3, [r0] ) 179bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r0, c7, c10, 1 @ flush_pte 1802eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#endif 181bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr 18293ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(cpu_v7_set_pte_ext) 183bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 18478a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin string cpu_v7_name, "ARMv7 Processor" 185bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 186bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 187f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King /* 188f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * Memory region attributes with SCTLR.TRE=1 189f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * 190f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * n = TEX[0],C,B 191f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * TR = PRRR[2n+1:2n] - memory type 192f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * IR = NMRR[2n+1:2n] - inner cacheable property 193f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * OR = NMRR[2n+17:2n+16] - outer cacheable property 194f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * 195f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * n TR IR OR 196f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * UNCACHED 000 00 197f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * BUFFERABLE 001 10 00 00 198f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * WRITETHROUGH 010 10 10 10 199f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * WRITEBACK 011 10 11 11 200f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * reserved 110 201f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * WRITEALLOC 111 10 01 01 202f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * DEV_SHARED 100 01 203f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * DEV_NONSHARED 100 01 204f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * DEV_WC 001 10 205f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * DEV_CACHED 011 10 206f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * 207f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * Other attributes: 208f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * 209f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * DS0 = PRRR[16] = 0 - device shareable property 210f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * DS1 = PRRR[17] = 1 - device shareable property 211f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * NS0 = PRRR[18] = 0 - normal shareable property 212f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * NS1 = PRRR[19] = 1 - normal shareable property 213f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King * NOS = PRRR[24+n] = 1 - not outer shareable 214f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King */ 215f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King.equ PRRR, 0xff0a81a8 216f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King.equ NMRR, 0x40e040e0 217f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 218f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 219f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King.globl cpu_v7_suspend_size 2201aede681ac159884c77817d33230eed9185b6f6cRussell King.equ cpu_v7_suspend_size, 4 * 7 22115e0d9e37c7fe9711b60f47221c394d45553ad8cArnd Bergmann#ifdef CONFIG_ARM_CPU_SUSPEND 222f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_v7_do_suspend) 223de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King stmfd sp!, {r4 - r10, lr} 224f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 2251aede681ac159884c77817d33230eed9185b6f6cRussell King mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 2261aede681ac159884c77817d33230eed9185b6f6cRussell King stmia r0!, {r4 - r5} 227f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r6, c3, c0, 0 @ Domain ID 228de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r7, c2, c0, 1 @ TTB 1 229de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r8, c1, c0, 0 @ Control register 230de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register 231de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control 232de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King stmia r0, {r6 - r10} 233de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ldmfd sp!, {r4 - r10, pc} 234f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_v7_do_suspend) 235f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 236f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_v7_do_resume) 237f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mov ip, #0 238f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 239f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 2401aede681ac159884c77817d33230eed9185b6f6cRussell King mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 2411aede681ac159884c77817d33230eed9185b6f6cRussell King ldmia r0!, {r4 - r5} 242f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 2431aede681ac159884c77817d33230eed9185b6f6cRussell King mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID 244de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ldmia r0, {r6 - r10} 245f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r6, c3, c0, 0 @ Domain ID 246de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 247de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 248de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r1, c2, c0, 0 @ TTB 0 249de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r7, c2, c0, 1 @ TTB 1 250f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c2, c0, 2 @ TTB control register 25125904157168ddc8841748a729914f00e53d7e049Russell King mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register 252de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King teq r4, r9 @ Is it already set? 253de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcrne p15, 0, r9, c1, c0, 1 @ No, so write it 254de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control 255f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r4, =PRRR @ PRRR 256f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r5, =NMRR @ NMRR 257f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r4, c10, c2, 0 @ write PRRR 258f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r5, c10, c2, 1 @ write NMRR 259f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King isb 260f35235a315a167e38e8e5bc9e476dcd7c932612cRussell King dsb 261de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mov r0, r8 @ control register 262f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King b cpu_resume_mmu 263f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_v7_do_resume) 264f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King#endif 265f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 2665085f3ff458521045f7e43da62b8c30ea7df2e82Russell King __CPUINIT 267bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 268bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas/* 269bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * __v7_setup 270bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 271bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Initialise TLB, Caches, and MMU state ready to switch the MMU 272bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * on. Return in r0 the new CP15 C1 control register setting. 273bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 274bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * We automatically detect if we have a Harvard cache, and use the 275bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Harvard cache control instructions insead of the unified cache 276bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * control instructions. 277bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 278bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * This should be able to cover all ARMv7 cores. 279bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * 280bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * It is assumed that: 281bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * - cache type register is implemented 282bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 28315eb169bfec291faf25b158cfa9842b72f7803adPawel Moll__v7_ca5mp_setup: 28414eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker__v7_ca9mp_setup: 2857665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon mov r10, #(1 << 0) @ TLB ops broadcasting 2867665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon b 1f 2877665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon__v7_ca15mp_setup: 2887665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon mov r10, #0 2897665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon1: 29073b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#ifdef CONFIG_SMP 291f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_SMP(mrc p15, 0, r0, c1, c0, 1) 292f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_UP(mov r0, #(1 << 6)) @ fake it for UP 2931b3a02eb452354fa9b36a7f33dc4c8307bbc40aaTony Thompson tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 2947665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode 2957665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon orreq r0, r0, r10 @ Enable CPU-specific SMP bits 2967665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon mcreq p15, 0, r0, c1, c0, 1 29773b63efaac7352c9e2bf1570fac98fd44a99f8f9Jon Callan#endif 29814eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker__v7_setup: 299bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas adr r12, __v7_setup_stack @ the local stack 300bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas stmia r12, {r0-r5, r7, r9, r11, lr} 301bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas bl v7_flush_dcache_all 302bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas ldmia r12, {r0-r5, r7, r9, r11, lr} 3031946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 3041946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrc p15, 0, r0, c0, c0, 0 @ read main ID register 3051946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r10, r0, #0xff000000 @ ARM? 3061946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r10, #0x41000000 3079f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon bne 3f 3081946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r5, r0, #0x00f00000 @ variant 3091946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King and r6, r0, #0x0000000f @ revision 3106491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon orr r6, r6, r5, lsr #20-4 @ combine variant and revision 3116491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon ubfx r0, r0, #4, #12 @ primary part number 3121946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 3136491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon /* Cortex-A8 Errata */ 3146491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon ldr r10, =0x00000c08 @ Cortex-A8 primary part number 3156491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r0, r10 3166491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon bne 2f 3177ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#ifdef CONFIG_ARM_ERRATA_430973 3181946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King teq r5, #0x00100000 @ only present in r1p* 3191946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 3201946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 6) @ set IBE to 1 3211946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 3227ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47Catalin Marinas#endif 323855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#ifdef CONFIG_ARM_ERRATA_458693 3246491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r6, #0x20 @ only present in r2p0 3251946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 3261946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 5) @ set L1NEON to 1 3271946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 3281946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 329855c551f5b8cc3815d58e1056c1f1e7c461e2d24Catalin Marinas#endif 3300516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#ifdef CONFIG_ARM_ERRATA_460075 3316491848d1ab246f6d243ddef25085fc1d836ff2cWill Deacon teq r6, #0x20 @ only present in r2p0 3321946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 3331946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King tsteq r10, #1 << 22 3341946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 3351946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 3360516e4643cd22fc9f535aef02ad1de66c382c93bCatalin Marinas#endif 3379f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon b 3f 3389f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon 3399f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon /* Cortex-A9 Errata */ 3409f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number 3419f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon teq r0, r10 3429f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon bne 3f 3439f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon#ifdef CONFIG_ARM_ERRATA_742230 3449f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon cmp r6, #0x22 @ only present up to r2p2 3459f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register 3469f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon orrle r10, r10, #1 << 4 @ set bit #4 3479f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register 3489f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon#endif 349a672e99b129e286df2e2697a1b603d82321117f3Will Deacon#ifdef CONFIG_ARM_ERRATA_742231 350a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teq r6, #0x20 @ present in r2p0 351a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teqne r6, #0x21 @ present in r2p1 352a672e99b129e286df2e2697a1b603d82321117f3Will Deacon teqne r6, #0x22 @ present in r2p2 353a672e99b129e286df2e2697a1b603d82321117f3Will Deacon mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 354a672e99b129e286df2e2697a1b603d82321117f3Will Deacon orreq r10, r10, #1 << 12 @ set bit #12 355a672e99b129e286df2e2697a1b603d82321117f3Will Deacon orreq r10, r10, #1 << 22 @ set bit #22 356a672e99b129e286df2e2697a1b603d82321117f3Will Deacon mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 357a672e99b129e286df2e2697a1b603d82321117f3Will Deacon#endif 358475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon#ifdef CONFIG_ARM_ERRATA_743622 359475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon teq r6, #0x20 @ present in r2p0 360475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon teqne r6, #0x21 @ present in r2p1 361475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon teqne r6, #0x22 @ present in r2p2 362475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 363475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon orreq r10, r10, #1 << 6 @ set bit #6 364475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 365475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2dWill Deacon#endif 366ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) 367ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 368ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin ALT_UP_B(1f) 3699a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register 3709a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon orrlt r10, r10, #1 << 11 @ set bit #11 3719a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register 372ba90c516bae79b5f8184d915bfce7eb280af61b1Dave Martin1: 3739a27c27ce49df72b1b0062e2ad192a804e1b069bWill Deacon#endif 3741946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7Russell King 3759f05027c7cb3cfe56a31892bd83391138d41a667Will Deacon3: mov r10, #0 376bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#ifdef HARVARD_CACHE 377bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 378bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas#endif 379bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas dsb 3802eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas#ifdef CONFIG_MMU 381bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 382bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mcr p15, 0, r10, c2, c0, 2 @ TTB control register 383f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 384f00ec48fadf5e37e7889f14cff900aa70d18b644Russell King ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 385d427958a46af24f75d0017c45eadd172273bbf33Catalin Marinas ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 386d427958a46af24f75d0017c45eadd172273bbf33Catalin Marinas ALT_UP(orr r8, r8, #TTB_FLAGS_UP) 387d427958a46af24f75d0017c45eadd172273bbf33Catalin Marinas mcr p15, 0, r8, c2, c0, 1 @ load TTB1 388f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r5, =PRRR @ PRRR 389f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r6, =NMRR @ NMRR 3903f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r5, c10, c2, 0 @ write PRRR 3913f69c0c1af288d6b124d0a928a33b51061ebf850Russell King mcr p15, 0, r6, c10, c2, 1 @ write NMRR 392bdaaaec39792ee0035d6c5a5ad2520991e090a3cCatalin Marinas#endif 3932eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas adr r5, v7_crval 3942eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas ldmia r5, {r5, r6} 39526584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#ifdef CONFIG_CPU_ENDIAN_BE8 39626584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas orr r6, r6, #1 << 25 @ big-endian page tables 39726584853a44c58f3d6ac7360d697a2ddcd1a3efaCatalin Marinas#endif 39864d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm#ifdef CONFIG_SWP_EMULATE 39964d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm orr r5, r5, #(1 << 10) @ set SW bit in "clear" 40064d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm bic r6, r6, #(1 << 10) @ clear it in "mmuset" 40164d2dc384e41e2b7acead6804593ddaaf8aad8e1Leif Lindholm#endif 4022eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas mrc p15, 0, r0, c1, c0, 0 @ read control register 4032eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas bic r0, r0, r5 @ clear bits them 4042eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas orr r0, r0, r6 @ set them 405347c8b70b1d5256e445e54e736f88d21877616cfCatalin Marinas THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 406bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas mov pc, lr @ return to head.S:__ret 40793ed3970114983543bbebd195bef65db84444ea2Catalin MarinasENDPROC(__v7_setup) 408bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 409b1cce6b1b2785fd61454b47ceacb461815407662Russell King /* AT 410213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas * TFR EV X F I D LR S 411213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM 412b1cce6b1b2785fd61454b47ceacb461815407662Russell King * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 413213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas * 1 0 110 0011 1100 .111 1101 < we want 414bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 4152eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinas .type v7_crval, #object 4162eb8c82bc492d5f185150e63eba5eac4dff24178Catalin Marinasv7_crval: 417213fb2a8ee81ec106b9b370a07ccad575e9d3748Catalin Marinas crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 418bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 419bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_setup_stack: 420bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .space 4 * 11 @ 11 registers 421bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 4225085f3ff458521045f7e43da62b8c30ea7df2e82Russell King __INITDATA 4235085f3ff458521045f7e43da62b8c30ea7df2e82Russell King 42478a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 42578a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 426bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 4275085f3ff458521045f7e43da62b8c30ea7df2e82Russell King .section ".rodata" 4285085f3ff458521045f7e43da62b8c30ea7df2e82Russell King 42978a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin string cpu_arch_name, "armv7" 43078a8f3c365b8851eb9862c54425e95bfd523f22dDave Martin string cpu_elf_name, "v7" 431bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .align 432bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 433bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .section ".proc.info.init", #alloc, #execinstr 434bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas 435dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll /* 436dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll * Standard v7 proc info content 437dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll */ 438dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 439dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 440dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll PMD_FLAGS_SMP | \mm_mmuflags) 441dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 442dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll PMD_FLAGS_UP | \mm_mmuflags) 443dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \ 444dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll PMD_SECT_AP_READ | \io_mmuflags 445dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll W(b) \initfunc 44614eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_arch_name 44714eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_elf_name 448dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ 449dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll HWCAP_EDSP | HWCAP_TLS | \hwcaps 45014eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long cpu_v7_name 45114eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7_processor_functions 45214eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7wbi_tlb_fns 45314eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v6_user_fns 45414eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .long v7_cache_fns 455dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll.endm 456dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll 457dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll /* 45815eb169bfec291faf25b158cfa9842b72f7803adPawel Moll * ARM Ltd. Cortex A5 processor. 45915eb169bfec291faf25b158cfa9842b72f7803adPawel Moll */ 46015eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .type __v7_ca5mp_proc_info, #object 46115eb169bfec291faf25b158cfa9842b72f7803adPawel Moll__v7_ca5mp_proc_info: 46215eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .long 0x410fc050 46315eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .long 0xff0ffff0 46415eb169bfec291faf25b158cfa9842b72f7803adPawel Moll __v7_proc __v7_ca5mp_setup 46515eb169bfec291faf25b158cfa9842b72f7803adPawel Moll .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info 46615eb169bfec291faf25b158cfa9842b72f7803adPawel Moll 46715eb169bfec291faf25b158cfa9842b72f7803adPawel Moll /* 468dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll * ARM Ltd. Cortex A9 processor. 469dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll */ 470dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .type __v7_ca9mp_proc_info, #object 471dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll__v7_ca9mp_proc_info: 472dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long 0x410fc090 473dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll .long 0xff0ffff0 474dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll __v7_proc __v7_ca9mp_setup 47514eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 47614eff1812679c76564b775aa95cdd378965f6cfbDaniel Walker 477bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas /* 4787665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon * ARM Ltd. Cortex A15 processor. 4797665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon */ 4807665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .type __v7_ca15mp_proc_info, #object 4817665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon__v7_ca15mp_proc_info: 4827665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .long 0x410fc0f0 4837665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .long 0xff0ffff0 4847665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV 4857665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info 4867665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon 4877665d9d2df2eb26284467c2f8591004bd511c75fWill Deacon /* 488bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas * Match any ARMv7 processor core. 489bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas */ 490bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .type __v7_proc_info, #object 491bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas__v7_proc_info: 492bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Required ID value 493bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .long 0x000f0000 @ Mask for ID 494dc939cd835d0e2d3ff4197d6e2c017d269616d20Pawel Moll __v7_proc __v7_setup 495bbe888864ec32435e93923c40b9d6ce2bb73844bCatalin Marinas .size __v7_proc_info, . - __v7_proc_info 496