1030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon/*
2030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * Based on arch/arm/include/asm/pmu.h
3030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon *
4030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
5030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * Copyright (C) 2012 ARM Ltd.
6030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon *
7030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * This program is free software; you can redistribute it and/or modify
8030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * it under the terms of the GNU General Public License version 2 as
9030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * published by the Free Software Foundation.
10030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon *
11030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * This program is distributed in the hope that it will be useful,
12030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * but WITHOUT ANY WARRANTY; without even the implied warranty of
13030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * GNU General Public License for more details.
15030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon *
16030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * You should have received a copy of the GNU General Public License
17030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon */
19030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon#ifndef __ASM_PMU_H
20030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon#define __ASM_PMU_H
21030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
22030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon#ifdef CONFIG_HW_PERF_EVENTS
23030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
24030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon/* The events for a given PMU register set. */
25030896885ade0a17c8638e1ede8d3ca7099f0302Will Deaconstruct pmu_hw_events {
26030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	/*
27030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	 * The events that are active on the PMU for the given index.
28030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	 */
29030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	struct perf_event	**events;
30030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
31030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	/*
32030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	 * A 1 bit for an index indicates that the counter is being used for
33030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	 * an event. A 0 means that the counter can be used.
34030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	 */
35030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	unsigned long           *used_mask;
36030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
37030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	/*
38030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	 * Hardware lock to serialize accesses to PMU registers. Needed for the
39030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	 * read/modify/write sequences.
40030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	 */
41030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	raw_spinlock_t		pmu_lock;
42030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon};
43030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
44030896885ade0a17c8638e1ede8d3ca7099f0302Will Deaconstruct arm_pmu {
45030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	struct pmu		pmu;
46030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	cpumask_t		active_irqs;
47030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	const char		*name;
48030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	irqreturn_t		(*handle_irq)(int irq_num, void *dev);
49030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	void			(*enable)(struct hw_perf_event *evt, int idx);
50030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	void			(*disable)(struct hw_perf_event *evt, int idx);
51030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	int			(*get_event_idx)(struct pmu_hw_events *hw_events,
52030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon						 struct hw_perf_event *hwc);
53030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	int			(*set_event_filter)(struct hw_perf_event *evt,
54030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon						    struct perf_event_attr *attr);
55030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	u32			(*read_counter)(int idx);
56030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	void			(*write_counter)(int idx, u32 val);
57030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	void			(*start)(void);
58030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	void			(*stop)(void);
59030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	void			(*reset)(void *);
60030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	int			(*map_event)(struct perf_event *event);
61030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	int			num_events;
62030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	atomic_t		active_events;
63030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	struct mutex		reserve_mutex;
64030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	u64			max_period;
65030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	struct platform_device	*plat_device;
66030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon	struct pmu_hw_events	*(*get_hw_events)(void);
67030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon};
68030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
69030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
70030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
71030896885ade0a17c8638e1ede8d3ca7099f0302Will Deaconint __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
72030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
73030896885ade0a17c8638e1ede8d3ca7099f0302Will Deaconu64 armpmu_event_update(struct perf_event *event,
74030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon			struct hw_perf_event *hwc,
75030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon			int idx);
76030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
77030896885ade0a17c8638e1ede8d3ca7099f0302Will Deaconint armpmu_event_set_period(struct perf_event *event,
78030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon			    struct hw_perf_event *hwc,
79030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon			    int idx);
80030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon
81030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon#endif /* CONFIG_HW_PERF_EVENTS */
82030896885ade0a17c8638e1ede8d3ca7099f0302Will Deacon#endif /* __ASM_PMU_H */
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