1b03f203986dcf51b556e5f86475338b1588d8652Mike Frysinger/* mach/dma.h - arch-specific DMA defines 2590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich * 3b03f203986dcf51b556e5f86475338b1588d8652Mike Frysinger * Copyright 2004-2008 Analog Devices Inc. 4590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich * 5b03f203986dcf51b556e5f86475338b1588d8652Mike Frysinger * Licensed under the GPL-2 or later. 6590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich */ 7590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich 8590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#ifndef _MACH_DMA_H_ 9590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define _MACH_DMA_H_ 10590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich 11211daf9d7252288ad88ab6b97268a8d828e6b696Mike Frysinger#define MAX_DMA_CHANNELS 16 12590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich 13590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_PPI 0 /* PPI receive/transmit or NFC */ 14590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */ 15590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */ 16590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */ 17590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_SPORT0_RX 3 /* SPORT0 receive */ 18590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_SPORT0_TX 4 /* SPORT0 transmit */ 19590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_SPORT1_RX 5 /* SPORT1 receive */ 20590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_SPORT1_TX 6 /* SPORT1 transmit */ 21590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_SPI 7 /* SPI transmit/receive */ 22590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_UART0_RX 8 /* UART0 receive */ 23590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_UART0_TX 9 /* UART0 transmit */ 24590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_UART1_RX 10 /* UART1 receive */ 25590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_UART1_TX 11 /* UART1 transmit */ 26590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich 27590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_MEM_STREAM0_DEST 12 /* TX */ 28590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_MEM_STREAM0_SRC 13 /* RX */ 29590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_MEM_STREAM1_DEST 14 /* TX */ 30590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#define CH_MEM_STREAM1_SRC 15 /* RX */ 31590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich 3264307f7db3690140a16c6748e65068f8a279877cMichael Hennerich#if defined(CONFIG_BF527_NAND_D_PORTF) 3364307f7db3690140a16c6748e65068f8a279877cMichael Hennerich#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */ 3464307f7db3690140a16c6748e65068f8a279877cMichael Hennerich#elif defined(CONFIG_BF527_NAND_D_PORTH) 3564307f7db3690140a16c6748e65068f8a279877cMichael Hennerich#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */ 3664307f7db3690140a16c6748e65068f8a279877cMichael Hennerich#endif 3764307f7db3690140a16c6748e65068f8a279877cMichael Hennerich 38590031450a52c373bf72f5fb156fbcc0c78c6f2cMichael Hennerich#endif 39