mem_map.h revision dbc895f95500a73ebf1ff12fe85f2e2b3790f52f 
1/*
2 * file:         include/asm-blackfin/mach-bf537/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 *	Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs:         enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose.  see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_537_H_
32#define _MEM_MAP_537_H_
33
34#define COREMMR_BASE           0xFFE00000	 /* Core MMRs */
35#define SYSMMR_BASE            0xFFC00000	 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE	0x20300000	 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE	0x00100000	/* 1M */
40#define ASYNC_BANK2_BASE	0x20200000	 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE	0x00100000	/* 1M */
42#define ASYNC_BANK1_BASE	0x20100000	 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE	0x00100000	/* 1M */
44#define ASYNC_BANK0_BASE	0x20000000	 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE	0x00100000	/* 1M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START		0xEF000000
50#define BOOT_ROM_LENGTH		0x800
51
52/* Level 1 Memory */
53
54/* Memory Map for ADSP-BF537 processors */
55
56#ifdef CONFIG_BFIN_ICACHE
57#define BFIN_ICACHESIZE	(16*1024)
58#else
59#define BFIN_ICACHESIZE	(0*1024)
60#endif
61
62
63#ifdef CONFIG_BF537
64#define L1_CODE_START       0xFFA00000
65#define L1_DATA_A_START     0xFF800000
66#define L1_DATA_B_START     0xFF900000
67
68#define L1_CODE_LENGTH      0xC000
69
70#ifdef CONFIG_BFIN_DCACHE
71
72#ifdef CONFIG_BFIN_DCACHE_BANKA
73#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
74#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
75#define L1_DATA_B_LENGTH      0x8000
76#define BFIN_DCACHESIZE	(16*1024)
77#define BFIN_DSUPBANKS	1
78#else
79#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
80#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
81#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
82#define BFIN_DCACHESIZE	(32*1024)
83#define BFIN_DSUPBANKS	2
84#endif
85
86#else
87#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
88#define L1_DATA_A_LENGTH      0x8000
89#define L1_DATA_B_LENGTH      0x8000
90#define BFIN_DCACHESIZE	(0*1024)
91#define BFIN_DSUPBANKS	0
92#endif /*CONFIG_BFIN_DCACHE*/
93
94#endif /*CONFIG_BF537*/
95
96/* Memory Map for ADSP-BF536 processors */
97
98#ifdef CONFIG_BF536
99#define L1_CODE_START       0xFFA00000
100#define L1_DATA_A_START     0xFF804000
101#define L1_DATA_B_START     0xFF904000
102
103#define L1_CODE_LENGTH      0xC000
104
105
106#ifdef CONFIG_BFIN_DCACHE
107
108#ifdef CONFIG_BFIN_DCACHE_BANKA
109#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
110#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
111#define L1_DATA_B_LENGTH      0x4000
112#define BFIN_DCACHESIZE	(16*1024)
113#define BFIN_DSUPBANKS	1
114
115#else
116#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
117#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
118#define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
119#define BFIN_DCACHESIZE	(32*1024)
120#define BFIN_DSUPBANKS	2
121#endif
122
123#else
124#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
125#define L1_DATA_A_LENGTH      0x4000
126#define L1_DATA_B_LENGTH      0x4000
127#define BFIN_DCACHESIZE	(0*1024)
128#define BFIN_DSUPBANKS	0
129#endif /*CONFIG_BFIN_DCACHE*/
130
131#endif
132
133/* Memory Map for ADSP-BF534 processors */
134
135#ifdef CONFIG_BF534
136#define L1_CODE_START       0xFFA00000
137#define L1_DATA_A_START     0xFF800000
138#define L1_DATA_B_START     0xFF900000
139
140#define L1_CODE_LENGTH      0xC000
141
142#ifdef CONFIG_BFIN_DCACHE
143
144#ifdef CONFIG_BFIN_DCACHE_BANKA
145#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
146#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
147#define L1_DATA_B_LENGTH      0x8000
148#define BFIN_DCACHESIZE	(16*1024)
149#define BFIN_DSUPBANKS	1
150
151#else
152#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
153#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
154#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
155#define BFIN_DCACHESIZE	(32*1024)
156#define BFIN_DSUPBANKS	2
157#endif
158
159#else
160#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
161#define L1_DATA_A_LENGTH      0x8000
162#define L1_DATA_B_LENGTH      0x8000
163#define BFIN_DCACHESIZE	(0*1024)
164#define BFIN_DSUPBANKS	0
165#endif /*CONFIG_BFIN_DCACHE*/
166
167#endif
168
169/* Level 2 Memory - none */
170
171#define L2_START	0
172#define L2_LENGTH	0
173
174/* Scratch Pad Memory */
175
176#define L1_SCRATCH_START	0xFFB00000
177#define L1_SCRATCH_LENGTH	0x1000
178
179#define GET_PDA_SAFE(preg)		\
180	preg.l = _cpu_pda;		\
181	preg.h = _cpu_pda;
182
183#define GET_PDA(preg, dreg)	GET_PDA_SAFE(preg)
184
185#endif				/* _MEM_MAP_537_H_ */
186