anomaly.h revision a413647bb5bbe5414cd68332ff77588db09d10be 
1/*
2 * File: include/asm-blackfin/mach-bf548/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
8
9/* This file should be up to date with:
10 *  - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* We do not support 0.0 or 0.1 silicon - sorry */
17#if __SILICON_REVISION__ < 2
18# error will not work on BF548 silicon version 0.0, or 0.1
19#endif
20
21/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
22#define ANOMALY_05000074 (1)
23/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
24#define ANOMALY_05000119 (1)
25/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
26#define ANOMALY_05000122 (1)
27/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
28#define ANOMALY_05000245 (1)
29/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
30#define ANOMALY_05000265 (1)
31/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
32#define ANOMALY_05000272 (1)
33/* False Hardware Error Exception When ISR Context Is Not Restored */
34#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
35/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
36#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
37/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
38#define ANOMALY_05000310 (1)
39/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
40#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
41/* TWI Slave Boot Mode Is Not Functional */
42#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
43/* External FIFO Boot Mode Is Not Functional */
44#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
45/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
46#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
47/* Incorrect Access of OTP_STATUS During otp_write() Function */
48#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
49/* Synchronous Burst Flash Boot Mode Is Not Functional */
50#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
51/* Host DMA Boot Modes Are Not Functional */
52#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
53/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
54#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
55/* Inadequate Rotary Debounce Logic Duration */
56#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
57/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
58#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
59/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
60#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
61/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
62#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
63/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
64#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
65/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
66#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
67/* USB Calibration Value Is Not Initialized */
68#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
69/* USB Calibration Value to use */
70#define ANOMALY_05000346_value 0x5411
71/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
72#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
73/* Data Lost when Core Reads SDH Data FIFO */
74#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
75/* PLL Status Register Is Inaccurate */
76#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
77/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
78#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
79/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
80#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
81/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
82#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
83/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
84#define ANOMALY_05000357 (1)
85/* External Memory Read Access Hangs Core With PLL Bypass */
86#define ANOMALY_05000360 (1)
87/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
88#define ANOMALY_05000365 (1)
89/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
90#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
91/* Addressing Conflict between Boot ROM and Asynchronous Memory */
92#define ANOMALY_05000369 (1)
93/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
94#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
95/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
96#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
97/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
98#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
99/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
100#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
101/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
102#define ANOMALY_05000379 (1)
103/* 8-Bit NAND Flash Boot Mode Not Functional */
104#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
105/* Some ATAPI Modes Are Not Functional */
106#define ANOMALY_05000383 (1)
107/* Boot from OTP Memory Not Functional */
108#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
109/* bfrom_SysControl() Firmware Routine Not Functional */
110#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
111/* Programmable Preboot Settings Not Functional */
112#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
113/* CRC32 Checksum Support Not Functional */
114#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
115/* Reset Vector Must Not Be in SDRAM Memory Space */
116#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
117/* Changed Meaning of BCODE Field in SYSCR Register */
118#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
119/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
120#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
121/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
122#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
123/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
124#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
125/* Log Buffer Not Functional */
126#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
127/* Hook Routine Not Functional */
128#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
129/* Header Indirect Bit Not Functional */
130#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
131/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
132#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
133/* Lockbox SESR Disallows Certain User Interrupts */
134#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
135/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
136#define ANOMALY_05000405 (1)
137/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
138#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
139/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
140#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
141/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
142#define ANOMALY_05000408 (1)
143/* Lockbox firmware leaves MDMA0 channel enabled */
144#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
145/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
146#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
147/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
148#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
149/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
150#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
151/* Speculative Fetches Can Cause Undesired External FIFO Operations */
152#define ANOMALY_05000416 (1)
153/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
154#define ANOMALY_05000425 (1)
155/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
156#define ANOMALY_05000426 (1)
157/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
158#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
159/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
160#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
161/* Software System Reset Corrupts PLL_LOCKCNT Register */
162#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
163/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
164#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
165/* OTP Write Accesses Not Supported */
166#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
167/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
168#define ANOMALY_05000443 (1)
169/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
170#define ANOMALY_05000446 (1)
171/* UART IrDA Receiver Fails on Extended Bit Pulses */
172#define ANOMALY_05000447 (1)
173/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
174#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
175/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
176#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
177/* USB DMA Mode 1 Short Packet Data Corruption */
178#define ANOMALY_05000450 (1)
179/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
180#define ANOMALY_05000456 (__SILICON_REVISION__ < 3)
181/* False Hardware Error when RETI points to invalid memory */
182#define ANOMALY_05000461 (1)
183
184/* Anomalies that don't exist on this proc */
185#define ANOMALY_05000099 (0)
186#define ANOMALY_05000120 (0)
187#define ANOMALY_05000125 (0)
188#define ANOMALY_05000149 (0)
189#define ANOMALY_05000158 (0)
190#define ANOMALY_05000171 (0)
191#define ANOMALY_05000179 (0)
192#define ANOMALY_05000183 (0)
193#define ANOMALY_05000198 (0)
194#define ANOMALY_05000215 (0)
195#define ANOMALY_05000220 (0)
196#define ANOMALY_05000227 (0)
197#define ANOMALY_05000230 (0)
198#define ANOMALY_05000231 (0)
199#define ANOMALY_05000233 (0)
200#define ANOMALY_05000242 (0)
201#define ANOMALY_05000244 (0)
202#define ANOMALY_05000248 (0)
203#define ANOMALY_05000250 (0)
204#define ANOMALY_05000254 (0)
205#define ANOMALY_05000261 (0)
206#define ANOMALY_05000263 (0)
207#define ANOMALY_05000266 (0)
208#define ANOMALY_05000273 (0)
209#define ANOMALY_05000274 (0)
210#define ANOMALY_05000278 (0)
211#define ANOMALY_05000287 (0)
212#define ANOMALY_05000301 (0)
213#define ANOMALY_05000305 (0)
214#define ANOMALY_05000307 (0)
215#define ANOMALY_05000311 (0)
216#define ANOMALY_05000323 (0)
217#define ANOMALY_05000362 (1)
218#define ANOMALY_05000363 (0)
219#define ANOMALY_05000380 (0)
220#define ANOMALY_05000400 (0)
221#define ANOMALY_05000412 (0)
222#define ANOMALY_05000432 (0)
223#define ANOMALY_05000435 (0)
224
225#endif
226