cdefBF561.h revision f5879fda09ea98d7aa845a0e0fa7e508452e5f9f
1/* 2 * File: include/asm-blackfin/mach-bf561/cdefBF561.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 8 * 9 * Rev: 10 * 11 * Modified: 12 * 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2, or (at your option) 18 * any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; see the file COPYING. 27 * If not, write to the Free Software Foundation, 28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 */ 30 31#ifndef _CDEF_BF561_H 32#define _CDEF_BF561_H 33 34#include <asm/blackfin.h> 35 36/* include all Core registers and bit definitions */ 37#include "defBF561.h" 38 39/*include core specific register pointer definitions*/ 40#include <asm/cdef_LPBlackfin.h> 41 42/*********************************************************************************** */ 43/* System MMR Register Map */ 44/*********************************************************************************** */ 45 46/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 47#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) 48#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 49#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 50#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 51#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 52#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 53#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 54#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) 55#define bfin_read_CHIPID() bfin_read32(CHIPID) 56 57/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 58#define bfin_read_SWRST() bfin_read_SICA_SWRST() 59#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) 60#define bfin_read_SYSCR() bfin_read_SICA_SYSCR() 61#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) 62 63/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ 64#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) 65#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) 66#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) 67#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) 68#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) 69#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) 70#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) 71#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) 72#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) 73#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) 74#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) 75#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) 76#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) 77#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) 78#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) 79#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) 80#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) 81#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) 82#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) 83#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) 84#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) 85#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) 86#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) 87#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) 88#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) 89#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) 90#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) 91#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) 92#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) 93#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) 94#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) 95#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) 96#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) 97#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) 98#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1) 99#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val) 100 101/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ 102#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) 103#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val) 104#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR) 105#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val) 106#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT) 107#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val) 108#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0) 109#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val) 110#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1) 111#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val) 112#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0) 113#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val) 114#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1) 115#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val) 116#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2) 117#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val) 118#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3) 119#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val) 120#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4) 121#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val) 122#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5) 123#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val) 124#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6) 125#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val) 126#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7) 127#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val) 128#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0) 129#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val) 130#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1) 131#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val) 132#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0) 133#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val) 134#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1) 135#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val) 136/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */ 137#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL) 138#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val) 139#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT) 140#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val) 141#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT) 142#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val) 143 144/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */ 145#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL) 146#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val) 147#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT) 148#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val) 149#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT) 150#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val) 151 152/* UART Controller (0xFFC00400 - 0xFFC004FF) */ 153#define bfin_read_UART_THR() bfin_read16(UART_THR) 154#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val) 155#define bfin_read_UART_RBR() bfin_read16(UART_RBR) 156#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val) 157#define bfin_read_UART_DLL() bfin_read16(UART_DLL) 158#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val) 159#define bfin_read_UART_IER() bfin_read16(UART_IER) 160#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val) 161#define bfin_read_UART_DLH() bfin_read16(UART_DLH) 162#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val) 163#define bfin_read_UART_IIR() bfin_read16(UART_IIR) 164#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val) 165#define bfin_read_UART_LCR() bfin_read16(UART_LCR) 166#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val) 167#define bfin_read_UART_MCR() bfin_read16(UART_MCR) 168#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val) 169#define bfin_read_UART_LSR() bfin_read16(UART_LSR) 170#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val) 171#define bfin_read_UART_MSR() bfin_read16(UART_MSR) 172#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val) 173#define bfin_read_UART_SCR() bfin_read16(UART_SCR) 174#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val) 175#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) 176#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val) 177 178/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 179#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) 180#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) 181#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) 182#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) 183#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) 184#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) 185#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) 186#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) 187#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) 188#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) 189#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) 190#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) 191#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) 192#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) 193 194/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */ 195#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) 196#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) 197#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) 198#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) 199#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) 200#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) 201#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) 202#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) 203#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) 204#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) 205#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) 206#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) 207#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) 208#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) 209#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) 210#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) 211#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) 212#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) 213#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) 214#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) 215#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) 216#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) 217#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) 218#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) 219#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) 220#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val) 221#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) 222#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val) 223#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) 224#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val) 225#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) 226#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val) 227#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) 228#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val) 229#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) 230#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val) 231#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) 232#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val) 233#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) 234#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val) 235#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) 236#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val) 237#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) 238#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val) 239#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) 240#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val) 241#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) 242#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val) 243#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) 244#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val) 245#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) 246#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val) 247#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) 248#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val) 249#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) 250#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val) 251#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) 252#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val) 253#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) 254#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val) 255#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) 256#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val) 257#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) 258#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val) 259 260/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */ 261#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE) 262#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val) 263#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE) 264#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val) 265#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS) 266#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val) 267#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) 268#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val) 269#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) 270#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val) 271#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) 272#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val) 273#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) 274#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val) 275#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) 276#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val) 277#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) 278#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val) 279#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) 280#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val) 281#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) 282#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val) 283#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) 284#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val) 285#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) 286#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val) 287#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) 288#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val) 289#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) 290#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val) 291#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG) 292#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val) 293#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER) 294#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val) 295#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD) 296#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val) 297#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH) 298#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val) 299#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE) 300#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val) 301#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE) 302#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val) 303#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS) 304#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val) 305 306/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */ 307#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D) 308#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val) 309#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C) 310#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val) 311#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S) 312#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val) 313#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T) 314#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val) 315#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D) 316#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val) 317#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C) 318#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val) 319#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S) 320#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val) 321#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T) 322#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val) 323#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D) 324#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val) 325#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C) 326#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val) 327#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S) 328#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val) 329#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T) 330#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val) 331#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR) 332#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val) 333#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR) 334#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val) 335#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE) 336#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val) 337#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH) 338#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val) 339#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN) 340#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val) 341/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */ 342#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D) 343#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val) 344#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C) 345#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val) 346#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S) 347#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val) 348#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T) 349#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val) 350#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D) 351#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val) 352#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C) 353#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val) 354#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S) 355#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val) 356#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T) 357#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val) 358#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D) 359#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val) 360#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C) 361#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val) 362#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S) 363#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val) 364#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T) 365#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val) 366#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR) 367#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val) 368#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR) 369#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val) 370#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE) 371#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val) 372#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH) 373#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val) 374#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN) 375#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val) 376/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */ 377#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D) 378#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val) 379#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C) 380#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val) 381#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S) 382#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val) 383#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T) 384#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val) 385#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D) 386#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val) 387#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C) 388#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val) 389#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S) 390#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val) 391#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T) 392#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val) 393#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D) 394#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val) 395#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C) 396#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val) 397#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S) 398#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val) 399#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T) 400#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val) 401#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR) 402#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val) 403#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR) 404#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val) 405#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE) 406#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val) 407#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH) 408#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val) 409#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN) 410#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val) 411/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ 412#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) 413#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) 414#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) 415#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) 416#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) 417#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) 418#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) 419#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) 420#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) 421#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) 422#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) 423#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) 424#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) 425#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) 426#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) 427#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) 428#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) 429#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) 430#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) 431#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) 432#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) 433#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) 434#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) 435#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) 436#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) 437#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) 438#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) 439#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) 440#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) 441#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) 442#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) 443#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) 444#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) 445#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) 446#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) 447#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) 448#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) 449#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) 450#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) 451#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) 452#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) 453#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) 454#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) 455#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) 456#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) 457#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) 458#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) 459#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) 460#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) 461#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) 462#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) 463#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) 464/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ 465#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) 466#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) 467#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) 468#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) 469#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) 470#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) 471#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) 472#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) 473#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) 474#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) 475#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) 476#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) 477#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) 478#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) 479#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) 480#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) 481#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) 482#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) 483#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) 484#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) 485#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) 486#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) 487#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) 488#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) 489#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) 490#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) 491#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) 492#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) 493#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) 494#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) 495#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) 496#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) 497#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) 498#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) 499#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) 500#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) 501#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) 502#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) 503#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) 504#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) 505#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) 506#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) 507#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) 508#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) 509#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) 510#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) 511#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) 512#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) 513#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) 514#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) 515#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) 516#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) 517/* Asynchronous Memory Controller - External Bus Interface Unit */ 518#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) 519#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) 520#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) 521#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) 522#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) 523#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) 524/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ 525#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) 526#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) 527#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL) 528#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val) 529#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) 530#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) 531#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) 532#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) 533/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */ 534#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL) 535#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val) 536#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS) 537#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val) 538#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS() 539#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT) 540#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val) 541#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY) 542#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val) 543#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME) 544#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val) 545/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */ 546#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL) 547#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val) 548#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS) 549#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val) 550#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS() 551#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT) 552#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val) 553#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY) 554#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val) 555#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME) 556#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val) 557/*DMA traffic control registers */ 558#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) 559#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER,val) 560#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) 561#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT,val) 562#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) 563#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER,val) 564#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) 565#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT,val) 566/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */ 567#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) 568#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val) 569#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR) 570#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val) 571#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR) 572#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val) 573#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT) 574#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val) 575#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT) 576#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val) 577#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY) 578#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val) 579#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY) 580#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val) 581#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR) 582#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val) 583#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR) 584#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val) 585#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT) 586#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val) 587#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT) 588#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val) 589#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS) 590#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val) 591#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP) 592#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val) 593#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG) 594#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val) 595#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR) 596#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val) 597#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR) 598#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val) 599#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT) 600#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val) 601#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT) 602#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val) 603#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY) 604#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val) 605#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY) 606#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val) 607#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR) 608#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val) 609#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR) 610#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val) 611#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT) 612#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val) 613#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT) 614#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val) 615#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS) 616#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val) 617#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP) 618#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val) 619#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG) 620#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val) 621#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR) 622#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val) 623#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR) 624#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val) 625#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT) 626#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val) 627#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT) 628#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val) 629#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY) 630#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val) 631#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY) 632#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val) 633#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR) 634#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val) 635#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR) 636#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val) 637#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT) 638#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val) 639#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT) 640#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val) 641#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS) 642#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val) 643#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP) 644#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val) 645#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG) 646#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val) 647#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR) 648#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val) 649#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR) 650#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val) 651#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT) 652#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val) 653#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT) 654#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val) 655#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY) 656#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val) 657#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY) 658#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val) 659#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR) 660#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val) 661#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR) 662#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val) 663#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT) 664#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val) 665#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT) 666#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val) 667#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS) 668#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val) 669#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP) 670#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val) 671#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG) 672#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val) 673#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR) 674#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val) 675#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR) 676#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val) 677#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT) 678#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val) 679#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT) 680#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val) 681#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY) 682#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val) 683#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY) 684#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val) 685#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR) 686#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val) 687#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR) 688#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val) 689#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT) 690#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val) 691#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT) 692#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val) 693#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS) 694#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val) 695#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP) 696#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val) 697#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG) 698#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val) 699#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR) 700#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val) 701#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR) 702#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val) 703#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT) 704#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val) 705#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT) 706#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val) 707#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY) 708#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val) 709#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY) 710#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val) 711#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR) 712#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val) 713#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR) 714#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val) 715#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT) 716#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val) 717#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT) 718#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val) 719#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS) 720#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val) 721#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP) 722#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val) 723#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG) 724#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val) 725#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR) 726#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val) 727#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR) 728#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val) 729#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT) 730#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val) 731#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT) 732#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val) 733#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY) 734#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val) 735#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY) 736#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val) 737#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR) 738#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val) 739#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR) 740#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val) 741#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT) 742#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val) 743#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT) 744#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val) 745#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS) 746#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val) 747#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP) 748#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val) 749#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG) 750#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val) 751#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR) 752#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val) 753#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR) 754#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val) 755#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT) 756#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val) 757#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT) 758#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val) 759#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY) 760#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val) 761#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY) 762#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val) 763#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR) 764#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val) 765#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR) 766#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val) 767#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT) 768#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val) 769#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT) 770#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val) 771#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS) 772#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val) 773#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP) 774#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val) 775#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG) 776#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val) 777#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR) 778#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val) 779#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR) 780#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val) 781#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT) 782#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val) 783#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT) 784#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val) 785#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY) 786#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val) 787#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY) 788#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val) 789#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR) 790#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val) 791#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR) 792#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val) 793#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT) 794#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val) 795#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT) 796#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val) 797#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS) 798#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val) 799#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP) 800#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val) 801#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG) 802#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val) 803#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR) 804#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val) 805#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR) 806#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val) 807#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT) 808#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val) 809#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT) 810#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val) 811#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY) 812#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val) 813#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY) 814#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val) 815#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR) 816#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val) 817#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR) 818#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val) 819#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT) 820#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val) 821#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT) 822#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val) 823#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS) 824#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val) 825#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP) 826#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val) 827#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG) 828#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val) 829#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR) 830#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val) 831#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR) 832#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val) 833#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT) 834#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val) 835#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT) 836#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val) 837#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY) 838#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val) 839#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY) 840#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val) 841#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR) 842#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val) 843#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR) 844#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val) 845#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT) 846#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val) 847#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT) 848#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val) 849#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS) 850#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val) 851#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP) 852#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val) 853#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG) 854#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val) 855#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR) 856#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val) 857#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR) 858#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val) 859#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT) 860#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val) 861#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT) 862#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val) 863#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY) 864#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val) 865#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY) 866#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val) 867#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR) 868#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val) 869#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR) 870#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val) 871#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT) 872#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val) 873#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT) 874#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val) 875#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS) 876#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val) 877#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) 878#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val) 879/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */ 880#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) 881#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG,val) 882#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_read32(MDMA1_D0_NEXT_DESC_PTR) 883#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val) 884#define bfin_read_MDMA1_D0_START_ADDR() bfin_read32(MDMA1_D0_START_ADDR) 885#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_write32(MDMA1_D0_START_ADDR,val) 886#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) 887#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT,val) 888#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) 889#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT,val) 890#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) 891#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY,val) 892#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) 893#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY,val) 894#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_read32(MDMA1_D0_CURR_DESC_PTR) 895#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val) 896#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_read32(MDMA1_D0_CURR_ADDR) 897#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_write32(MDMA1_D0_CURR_ADDR,val) 898#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) 899#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val) 900#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) 901#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val) 902#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) 903#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS,val) 904#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) 905#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val) 906#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) 907#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG,val) 908#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_read32(MDMA1_S0_NEXT_DESC_PTR) 909#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val) 910#define bfin_read_MDMA1_S0_START_ADDR() bfin_read32(MDMA1_S0_START_ADDR) 911#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_write32(MDMA1_S0_START_ADDR,val) 912#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) 913#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT,val) 914#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) 915#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT,val) 916#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) 917#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY,val) 918#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) 919#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY,val) 920#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_read32(MDMA1_S0_CURR_DESC_PTR) 921#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val) 922#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_read32(MDMA1_S0_CURR_ADDR) 923#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_write32(MDMA1_S0_CURR_ADDR,val) 924#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) 925#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val) 926#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) 927#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val) 928#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) 929#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS,val) 930#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) 931#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val) 932#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) 933#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG,val) 934#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_read32(MDMA1_D1_NEXT_DESC_PTR) 935#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val) 936#define bfin_read_MDMA1_D1_START_ADDR() bfin_read32(MDMA1_D1_START_ADDR) 937#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_write32(MDMA1_D1_START_ADDR,val) 938#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) 939#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT,val) 940#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) 941#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT,val) 942#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) 943#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY,val) 944#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) 945#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY,val) 946#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_read32(MDMA1_D1_CURR_DESC_PTR) 947#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val) 948#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_read32(MDMA1_D1_CURR_ADDR) 949#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_write32(MDMA1_D1_CURR_ADDR,val) 950#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) 951#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val) 952#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) 953#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val) 954#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) 955#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS,val) 956#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) 957#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val) 958#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) 959#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG,val) 960#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_read32(MDMA1_S1_NEXT_DESC_PTR) 961#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val) 962#define bfin_read_MDMA1_S1_START_ADDR() bfin_read32(MDMA1_S1_START_ADDR) 963#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_write32(MDMA1_S1_START_ADDR,val) 964#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) 965#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT,val) 966#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) 967#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT,val) 968#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) 969#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY,val) 970#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) 971#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY,val) 972#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_read32(MDMA1_S1_CURR_DESC_PTR) 973#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val) 974#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_read32(MDMA1_S1_CURR_ADDR) 975#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_write32(MDMA1_S1_CURR_ADDR,val) 976#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) 977#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val) 978#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) 979#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val) 980#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) 981#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS,val) 982#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) 983#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val) 984/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ 985#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) 986#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val) 987#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR) 988#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val) 989#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR) 990#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val) 991#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT) 992#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val) 993#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT) 994#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val) 995#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY) 996#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val) 997#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY) 998#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val) 999#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR) 1000#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val) 1001#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR) 1002#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val) 1003#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT) 1004#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val) 1005#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT) 1006#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val) 1007#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS) 1008#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val) 1009#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP) 1010#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val) 1011#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG) 1012#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val) 1013#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR) 1014#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val) 1015#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR) 1016#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val) 1017#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT) 1018#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val) 1019#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT) 1020#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val) 1021#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY) 1022#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val) 1023#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY) 1024#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val) 1025#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR) 1026#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val) 1027#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR) 1028#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val) 1029#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT) 1030#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val) 1031#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT) 1032#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val) 1033#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS) 1034#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val) 1035#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP) 1036#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val) 1037#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG) 1038#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val) 1039#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR) 1040#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val) 1041#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR) 1042#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val) 1043#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT) 1044#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val) 1045#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT) 1046#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val) 1047#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY) 1048#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val) 1049#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY) 1050#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val) 1051#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR) 1052#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val) 1053#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR) 1054#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val) 1055#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT) 1056#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val) 1057#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT) 1058#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val) 1059#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS) 1060#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val) 1061#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP) 1062#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val) 1063#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG) 1064#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val) 1065#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR) 1066#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val) 1067#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR) 1068#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val) 1069#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT) 1070#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val) 1071#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT) 1072#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val) 1073#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY) 1074#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val) 1075#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY) 1076#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val) 1077#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR) 1078#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val) 1079#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR) 1080#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val) 1081#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT) 1082#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val) 1083#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT) 1084#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val) 1085#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS) 1086#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val) 1087#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP) 1088#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val) 1089#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG) 1090#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val) 1091#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR) 1092#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val) 1093#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR) 1094#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val) 1095#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT) 1096#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val) 1097#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT) 1098#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val) 1099#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY) 1100#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val) 1101#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY) 1102#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val) 1103#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR) 1104#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val) 1105#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR) 1106#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val) 1107#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT) 1108#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val) 1109#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT) 1110#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val) 1111#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS) 1112#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val) 1113#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP) 1114#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val) 1115#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG) 1116#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val) 1117#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR) 1118#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val) 1119#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR) 1120#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val) 1121#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT) 1122#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val) 1123#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT) 1124#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val) 1125#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY) 1126#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val) 1127#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY) 1128#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val) 1129#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR) 1130#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val) 1131#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR) 1132#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val) 1133#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT) 1134#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val) 1135#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT) 1136#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val) 1137#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS) 1138#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val) 1139#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP) 1140#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val) 1141#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG) 1142#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val) 1143#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR) 1144#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val) 1145#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR) 1146#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val) 1147#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT) 1148#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val) 1149#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT) 1150#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val) 1151#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY) 1152#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val) 1153#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY) 1154#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val) 1155#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR) 1156#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val) 1157#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR) 1158#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val) 1159#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT) 1160#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val) 1161#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT) 1162#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val) 1163#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS) 1164#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val) 1165#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP) 1166#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val) 1167#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG) 1168#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val) 1169#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR) 1170#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val) 1171#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR) 1172#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val) 1173#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT) 1174#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val) 1175#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT) 1176#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val) 1177#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY) 1178#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val) 1179#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY) 1180#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val) 1181#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR) 1182#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val) 1183#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR) 1184#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val) 1185#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT) 1186#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val) 1187#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT) 1188#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val) 1189#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS) 1190#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val) 1191#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP) 1192#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val) 1193#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG) 1194#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val) 1195#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR) 1196#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val) 1197#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR) 1198#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val) 1199#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT) 1200#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val) 1201#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT) 1202#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val) 1203#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY) 1204#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val) 1205#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY) 1206#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val) 1207#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR) 1208#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val) 1209#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR) 1210#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val) 1211#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT) 1212#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val) 1213#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT) 1214#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val) 1215#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS) 1216#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val) 1217#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP) 1218#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val) 1219#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG) 1220#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val) 1221#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR) 1222#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val) 1223#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR) 1224#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val) 1225#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT) 1226#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val) 1227#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT) 1228#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val) 1229#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY) 1230#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val) 1231#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY) 1232#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val) 1233#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR) 1234#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val) 1235#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR) 1236#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val) 1237#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT) 1238#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val) 1239#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT) 1240#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val) 1241#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS) 1242#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val) 1243#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP) 1244#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val) 1245#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG) 1246#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val) 1247#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR) 1248#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val) 1249#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR) 1250#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val) 1251#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT) 1252#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val) 1253#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT) 1254#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val) 1255#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY) 1256#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val) 1257#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY) 1258#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val) 1259#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR) 1260#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val) 1261#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR) 1262#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val) 1263#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT) 1264#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val) 1265#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT) 1266#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val) 1267#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS) 1268#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val) 1269#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP) 1270#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val) 1271#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG) 1272#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val) 1273#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR) 1274#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val) 1275#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR) 1276#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val) 1277#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT) 1278#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val) 1279#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT) 1280#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val) 1281#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY) 1282#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val) 1283#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY) 1284#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val) 1285#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR) 1286#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val) 1287#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR) 1288#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val) 1289#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT) 1290#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val) 1291#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT) 1292#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val) 1293#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS) 1294#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val) 1295#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) 1296#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val) 1297/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */ 1298#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) 1299#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG,val) 1300#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_read32(MDMA2_D0_NEXT_DESC_PTR) 1301#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val) 1302#define bfin_read_MDMA2_D0_START_ADDR() bfin_read32(MDMA2_D0_START_ADDR) 1303#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_write32(MDMA2_D0_START_ADDR,val) 1304#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) 1305#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT,val) 1306#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) 1307#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT,val) 1308#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) 1309#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY,val) 1310#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) 1311#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY,val) 1312#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_read32(MDMA2_D0_CURR_DESC_PTR) 1313#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val) 1314#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_read32(MDMA2_D0_CURR_ADDR) 1315#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_write32(MDMA2_D0_CURR_ADDR,val) 1316#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) 1317#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val) 1318#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) 1319#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val) 1320#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) 1321#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS,val) 1322#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) 1323#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val) 1324#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) 1325#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG,val) 1326#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_read32(MDMA2_S0_NEXT_DESC_PTR) 1327#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val) 1328#define bfin_read_MDMA2_S0_START_ADDR() bfin_read32(MDMA2_S0_START_ADDR) 1329#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_write32(MDMA2_S0_START_ADDR,val) 1330#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) 1331#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT,val) 1332#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) 1333#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT,val) 1334#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) 1335#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY,val) 1336#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) 1337#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY,val) 1338#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_read32(MDMA2_S0_CURR_DESC_PTR) 1339#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val) 1340#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_read32(MDMA2_S0_CURR_ADDR) 1341#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_write32(MDMA2_S0_CURR_ADDR,val) 1342#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) 1343#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val) 1344#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) 1345#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val) 1346#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) 1347#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS,val) 1348#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) 1349#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val) 1350#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) 1351#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG,val) 1352#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_read32(MDMA2_D1_NEXT_DESC_PTR) 1353#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val) 1354#define bfin_read_MDMA2_D1_START_ADDR() bfin_read32(MDMA2_D1_START_ADDR) 1355#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_write32(MDMA2_D1_START_ADDR,val) 1356#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) 1357#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT,val) 1358#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) 1359#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT,val) 1360#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) 1361#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY,val) 1362#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) 1363#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY,val) 1364#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_read32(MDMA2_D1_CURR_DESC_PTR) 1365#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val) 1366#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_read32(MDMA2_D1_CURR_ADDR) 1367#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_write32(MDMA2_D1_CURR_ADDR,val) 1368#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) 1369#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val) 1370#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) 1371#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val) 1372#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) 1373#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS,val) 1374#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) 1375#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val) 1376#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) 1377#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG,val) 1378#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_read32(MDMA2_S1_NEXT_DESC_PTR) 1379#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val) 1380#define bfin_read_MDMA2_S1_START_ADDR() bfin_read32(MDMA2_S1_START_ADDR) 1381#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_write32(MDMA2_S1_START_ADDR,val) 1382#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) 1383#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT,val) 1384#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) 1385#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT,val) 1386#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) 1387#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY,val) 1388#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) 1389#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY,val) 1390#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_read32(MDMA2_S1_CURR_DESC_PTR) 1391#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val) 1392#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_read32(MDMA2_S1_CURR_ADDR) 1393#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_write32(MDMA2_S1_CURR_ADDR,val) 1394#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) 1395#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val) 1396#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) 1397#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val) 1398#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) 1399#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS,val) 1400#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) 1401#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val) 1402/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ 1403#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) 1404#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val) 1405#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR) 1406#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val) 1407#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR) 1408#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val) 1409#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT) 1410#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val) 1411#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT) 1412#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val) 1413#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY) 1414#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val) 1415#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY) 1416#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val) 1417#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR) 1418#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val) 1419#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR) 1420#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val) 1421#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT) 1422#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val) 1423#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT) 1424#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val) 1425#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS) 1426#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val) 1427#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG) 1428#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val) 1429#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR) 1430#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val) 1431#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR) 1432#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val) 1433#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT) 1434#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val) 1435#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT) 1436#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val) 1437#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY) 1438#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val) 1439#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY) 1440#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val) 1441#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR) 1442#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val) 1443#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR) 1444#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val) 1445#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT) 1446#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val) 1447#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT) 1448#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val) 1449#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS) 1450#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val) 1451#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG) 1452#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val) 1453#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR) 1454#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val) 1455#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR) 1456#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val) 1457#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT) 1458#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val) 1459#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT) 1460#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val) 1461#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY) 1462#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val) 1463#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY) 1464#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val) 1465#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR) 1466#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val) 1467#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR) 1468#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val) 1469#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT) 1470#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val) 1471#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT) 1472#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val) 1473#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS) 1474#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val) 1475#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG) 1476#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val) 1477#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR) 1478#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val) 1479#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR) 1480#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val) 1481#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT) 1482#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val) 1483#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT) 1484#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val) 1485#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY) 1486#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val) 1487#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY) 1488#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val) 1489#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR) 1490#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val) 1491#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR) 1492#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val) 1493#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT) 1494#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val) 1495#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT) 1496#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val) 1497#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) 1498#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val) 1499 1500#define bfin_read_MDMA_S0_CONFIG() bfin_read_MDMA1_S0_CONFIG() 1501#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val) 1502#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read_MDMA1_S0_IRQ_STATUS() 1503#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val) 1504#define bfin_read_MDMA_S0_X_MODIFY() bfin_read_MDMA1_S0_X_MODIFY() 1505#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val) 1506#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read_MDMA1_S0_Y_MODIFY() 1507#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val) 1508#define bfin_read_MDMA_S0_X_COUNT() bfin_read_MDMA1_S0_X_COUNT() 1509#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val) 1510#define bfin_read_MDMA_S0_Y_COUNT() bfin_read_MDMA1_S0_Y_COUNT() 1511#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val) 1512#define bfin_read_MDMA_S0_START_ADDR() bfin_read_MDMA1_S0_START_ADDR() 1513#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val) 1514#define bfin_read_MDMA_D0_CONFIG() bfin_read_MDMA1_D0_CONFIG() 1515#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val) 1516#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read_MDMA1_D0_IRQ_STATUS() 1517#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val) 1518#define bfin_read_MDMA_D0_X_MODIFY() bfin_read_MDMA1_D0_X_MODIFY() 1519#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val) 1520#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read_MDMA1_D0_Y_MODIFY() 1521#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val) 1522#define bfin_read_MDMA_D0_X_COUNT() bfin_read_MDMA1_D0_X_COUNT() 1523#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val) 1524#define bfin_read_MDMA_D0_Y_COUNT() bfin_read_MDMA1_D0_Y_COUNT() 1525#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val) 1526#define bfin_read_MDMA_D0_START_ADDR() bfin_read_MDMA1_D0_START_ADDR() 1527#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val) 1528 1529#define bfin_read_MDMA_S1_CONFIG() bfin_read_MDMA1_S1_CONFIG() 1530#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val) 1531#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read_MDMA1_S1_IRQ_STATUS() 1532#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val) 1533#define bfin_read_MDMA_S1_X_MODIFY() bfin_read_MDMA1_S1_X_MODIFY() 1534#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val) 1535#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read_MDMA1_S1_Y_MODIFY() 1536#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val) 1537#define bfin_read_MDMA_S1_X_COUNT() bfin_read_MDMA1_S1_X_COUNT() 1538#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val) 1539#define bfin_read_MDMA_S1_Y_COUNT() bfin_read_MDMA1_S1_Y_COUNT() 1540#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val) 1541#define bfin_read_MDMA_S1_START_ADDR() bfin_read_MDMA1_S1_START_ADDR() 1542#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val) 1543#define bfin_read_MDMA_D1_CONFIG() bfin_read_MDMA1_D1_CONFIG() 1544#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val) 1545#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read_MDMA1_D1_IRQ_STATUS() 1546#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val) 1547#define bfin_read_MDMA_D1_X_MODIFY() bfin_read_MDMA1_D1_X_MODIFY() 1548#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val) 1549#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read_MDMA1_D1_Y_MODIFY() 1550#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val) 1551#define bfin_read_MDMA_D1_X_COUNT() bfin_read_MDMA1_D1_X_COUNT() 1552#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val) 1553#define bfin_read_MDMA_D1_Y_COUNT() bfin_read_MDMA1_D1_Y_COUNT() 1554#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val) 1555#define bfin_read_MDMA_D1_START_ADDR() bfin_read_MDMA1_D1_START_ADDR() 1556#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val) 1557 1558/* These need to be last due to the cdef/linux inter-dependencies */ 1559#include <asm/irq.h> 1560 1561/* Writing to PLL_CTL initiates a PLL relock sequence. */ 1562static __inline__ void bfin_write_PLL_CTL(unsigned int val) 1563{ 1564 unsigned long flags, iwr0, iwr1; 1565 1566 if (val == bfin_read_PLL_CTL()) 1567 return; 1568 1569 local_irq_save_hw(flags); 1570 /* Enable the PLL Wakeup bit in SIC IWR */ 1571 iwr0 = bfin_read32(SICA_IWR0); 1572 iwr1 = bfin_read32(SICA_IWR1); 1573 /* Only allow PPL Wakeup) */ 1574 bfin_write32(SICA_IWR0, IWR_ENABLE(0)); 1575 bfin_write32(SICA_IWR1, 0); 1576 1577 bfin_write16(PLL_CTL, val); 1578 SSYNC(); 1579 asm("IDLE;"); 1580 1581 bfin_write32(SICA_IWR0, iwr0); 1582 bfin_write32(SICA_IWR1, iwr1); 1583 local_irq_restore_hw(flags); 1584} 1585 1586/* Writing to VR_CTL initiates a PLL relock sequence. */ 1587static __inline__ void bfin_write_VR_CTL(unsigned int val) 1588{ 1589 unsigned long flags, iwr0, iwr1; 1590 1591 if (val == bfin_read_VR_CTL()) 1592 return; 1593 1594 local_irq_save_hw(flags); 1595 /* Enable the PLL Wakeup bit in SIC IWR */ 1596 iwr0 = bfin_read32(SICA_IWR0); 1597 iwr1 = bfin_read32(SICA_IWR1); 1598 /* Only allow PPL Wakeup) */ 1599 bfin_write32(SICA_IWR0, IWR_ENABLE(0)); 1600 bfin_write32(SICA_IWR1, 0); 1601 1602 bfin_write16(VR_CTL, val); 1603 SSYNC(); 1604 asm("IDLE;"); 1605 1606 bfin_write32(SICA_IWR0, iwr0); 1607 bfin_write32(SICA_IWR1, iwr1); 1608 local_irq_restore_hw(flags); 1609} 1610 1611#endif /* _CDEF_BF561_H */ 1612