151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef __strcop_defs_asm_h 251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define __strcop_defs_asm_h 351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* 551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * This file is autogenerated from 651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * file: ../../inst/strcop/rtl/strcop_regs.r 751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp 851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * last modfied: Mon Apr 11 16:09:38 2005 951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * 1051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r 1151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ 1251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * Any changes here will be lost. 1351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * 1451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * -*- buffer-read-only: t -*- 1551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik */ 1651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 1751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_FIELD 1851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_FIELD( scope, reg, field, value ) \ 1951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 2051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_FIELD_X_( value, shift ) ((value) << shift) 2151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 2251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 2351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_STATE 2451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_STATE( scope, reg, field, symbolic_value ) \ 2551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 2651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_STATE_X_( k, shift ) (k << shift) 2751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 2851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 2951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_MASK 3051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_MASK( scope, reg, field ) \ 3151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 3251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 3351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 3451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 3551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_LSB 3651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 3751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 3851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 3951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_BIT 4051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 4151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 4251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 4351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_ADDR 4451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 4551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 4651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 4751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 4851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_ADDR_VECT 4951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_ADDR_VECT( scope, inst, reg, index ) \ 5051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 5151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik STRIDE_##scope##_##reg ) 5251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 5351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik ((inst) + offs + (index) * stride) 5451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 5551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 5651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_cfg, scope strcop, type rw */ 5751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___td3___lsb 0 5851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___td3___width 1 5951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___td3___bit 0 6051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___td2___lsb 1 6151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___td2___width 1 6251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___td2___bit 1 6351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___td1___lsb 2 6451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___td1___width 1 6551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___td1___bit 2 6651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___ipend___lsb 3 6751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___ipend___width 1 6851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___ipend___bit 3 6951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___ignore_sync___lsb 4 7051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___ignore_sync___width 1 7151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___ignore_sync___bit 4 7251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___en___lsb 5 7351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___en___width 1 7451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg___en___bit 5 7551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_strcop_rw_cfg_offset 0 7651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 7751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 7851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Constants */ 7951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_strcop_big 0x00000001 8051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_strcop_d 0x00000001 8151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_strcop_e 0x00000000 8251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_strcop_little 0x00000000 8351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_strcop_rw_cfg_default 0x00000002 8451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif /* __strcop_defs_asm_h */ 85