151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef __timer_defs_asm_h 251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define __timer_defs_asm_h 351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* 551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * This file is autogenerated from 651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * file: ../../inst/timer/rtl/timer_regs.r 751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp 851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * last modfied: Mon Apr 11 16:09:53 2005 951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * 1051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r 1151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ 1251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * Any changes here will be lost. 1351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * 1451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik * -*- buffer-read-only: t -*- 1551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik */ 1651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 1751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_FIELD 1851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_FIELD( scope, reg, field, value ) \ 1951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 2051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_FIELD_X_( value, shift ) ((value) << shift) 2151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 2251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 2351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_STATE 2451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_STATE( scope, reg, field, symbolic_value ) \ 2551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 2651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_STATE_X_( k, shift ) (k << shift) 2751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 2851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 2951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_MASK 3051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_MASK( scope, reg, field ) \ 3151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 3251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 3351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 3451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 3551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_LSB 3651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 3751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 3851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 3951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_BIT 4051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 4151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 4251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 4351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_ADDR 4451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 4551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 4651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 4751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 4851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#ifndef REG_ADDR_VECT 4951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_ADDR_VECT( scope, inst, reg, index ) \ 5051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 5151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik STRIDE_##scope##_##reg ) 5251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 5351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik ((inst) + offs + (index) * stride) 5451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif 5551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 5651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_tmr0_div, scope timer, type rw */ 5751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr0_div_offset 0 5851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 5951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register r_tmr0_data, scope timer, type r */ 6051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_tmr0_data_offset 4 6151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 6251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_tmr0_ctrl, scope timer, type rw */ 6351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr0_ctrl___op___lsb 0 6451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr0_ctrl___op___width 2 6551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 6651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr0_ctrl___freq___width 3 6751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr0_ctrl_offset 8 6851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 6951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_tmr1_div, scope timer, type rw */ 7051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr1_div_offset 16 7151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 7251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register r_tmr1_data, scope timer, type r */ 7351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_tmr1_data_offset 20 7451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 7551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_tmr1_ctrl, scope timer, type rw */ 7651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr1_ctrl___op___lsb 0 7751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr1_ctrl___op___width 2 7851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 7951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr1_ctrl___freq___width 3 8051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_tmr1_ctrl_offset 24 8151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 8251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rs_cnt_data, scope timer, type rs */ 8351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rs_cnt_data___tmr___lsb 0 8451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rs_cnt_data___tmr___width 24 8551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rs_cnt_data___cnt___lsb 24 8651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rs_cnt_data___cnt___width 8 8751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rs_cnt_data_offset 32 8851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 8951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register r_cnt_data, scope timer, type r */ 9051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_cnt_data___tmr___lsb 0 9151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_cnt_data___tmr___width 24 9251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_cnt_data___cnt___lsb 24 9351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_cnt_data___cnt___width 8 9451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_cnt_data_offset 36 9551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 9651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_cnt_cfg, scope timer, type rw */ 9751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_cnt_cfg___clk___lsb 0 9851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_cnt_cfg___clk___width 2 9951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_cnt_cfg_offset 40 10051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 10151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_trig, scope timer, type rw */ 10251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_trig_offset 48 10351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 10451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_trig_cfg, scope timer, type rw */ 10551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_trig_cfg___tmr___lsb 0 10651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_trig_cfg___tmr___width 2 10751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_trig_cfg_offset 52 10851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 10951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register r_time, scope timer, type r */ 11051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_time_offset 56 11151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 11251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_out, scope timer, type rw */ 11351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_out___tmr___lsb 0 11451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_out___tmr___width 2 11551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_out_offset 60 11651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 11751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_wd_ctrl, scope timer, type rw */ 11851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_wd_ctrl___cnt___lsb 0 11951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_wd_ctrl___cnt___width 8 12051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_wd_ctrl___cmd___lsb 8 12151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_wd_ctrl___cmd___width 1 12251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_wd_ctrl___cmd___bit 8 12351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_wd_ctrl___key___lsb 9 12451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_wd_ctrl___key___width 7 12551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_wd_ctrl_offset 64 12651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 12751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register r_wd_stat, scope timer, type r */ 12851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_wd_stat___cnt___lsb 0 12951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_wd_stat___cnt___width 8 13051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_wd_stat___cmd___lsb 8 13151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_wd_stat___cmd___width 1 13251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_wd_stat___cmd___bit 8 13351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_wd_stat_offset 68 13451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 13551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_intr_mask, scope timer, type rw */ 13651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___tmr0___lsb 0 13751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___tmr0___width 1 13851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___tmr0___bit 0 13951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___tmr1___lsb 1 14051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___tmr1___width 1 14151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___tmr1___bit 1 14251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___cnt___lsb 2 14351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___cnt___width 1 14451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___cnt___bit 2 14551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___trig___lsb 3 14651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___trig___width 1 14751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask___trig___bit 3 14851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_intr_mask_offset 72 14951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 15051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_ack_intr, scope timer, type rw */ 15151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___tmr0___lsb 0 15251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___tmr0___width 1 15351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___tmr0___bit 0 15451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___tmr1___lsb 1 15551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___tmr1___width 1 15651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___tmr1___bit 1 15751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___cnt___lsb 2 15851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___cnt___width 1 15951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___cnt___bit 2 16051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___trig___lsb 3 16151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___trig___width 1 16251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr___trig___bit 3 16351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_ack_intr_offset 76 16451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 16551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register r_intr, scope timer, type r */ 16651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___tmr0___lsb 0 16751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___tmr0___width 1 16851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___tmr0___bit 0 16951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___tmr1___lsb 1 17051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___tmr1___width 1 17151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___tmr1___bit 1 17251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___cnt___lsb 2 17351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___cnt___width 1 17451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___cnt___bit 2 17551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___trig___lsb 3 17651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___trig___width 1 17751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr___trig___bit 3 17851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_intr_offset 80 17951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 18051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register r_masked_intr, scope timer, type r */ 18151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___tmr0___lsb 0 18251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___tmr0___width 1 18351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___tmr0___bit 0 18451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___tmr1___lsb 1 18551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___tmr1___width 1 18651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___tmr1___bit 1 18751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___cnt___lsb 2 18851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___cnt___width 1 18951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___cnt___bit 2 19051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___trig___lsb 3 19151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___trig___width 1 19251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr___trig___bit 3 19351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_r_masked_intr_offset 84 19451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 19551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Register rw_test, scope timer, type rw */ 19651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_test___dis___lsb 0 19751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_test___dis___width 1 19851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_test___dis___bit 0 19951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_test___en___lsb 1 20051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_test___en___width 1 20151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_test___en___bit 1 20251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define reg_timer_rw_test_offset 88 20351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 20451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik 20551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik/* Constants */ 20651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_ext 0x00000001 20751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_f100 0x00000007 20851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_f29_493 0x00000004 20951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_f32 0x00000005 21051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_f32_768 0x00000006 21151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_hold 0x00000001 21251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_ld 0x00000000 21351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_no 0x00000000 21451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_off 0x00000000 21551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_run 0x00000002 21651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_rw_cnt_cfg_default 0x00000000 21751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_rw_intr_mask_default 0x00000000 21851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_rw_out_default 0x00000000 21951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_rw_test_default 0x00000000 22051533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_rw_tmr0_ctrl_default 0x00000000 22151533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_rw_tmr1_ctrl_default 0x00000000 22251533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_rw_trig_cfg_default 0x00000000 22351533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_start 0x00000001 22451533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_stop 0x00000000 22551533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_time 0x00000001 22651533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_tmr0 0x00000002 22751533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_tmr1 0x00000003 22851533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#define regk_timer_yes 0x00000001 22951533b615e605d86154ec1b4e585c8ca1b0b15b7Mikael Starvik#endif /* __timer_defs_asm_h */ 230