head-ram.S revision 2c31c341a827b99eef743753aa9adb917b9ea6db
181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer/* arch/m68knommu/platform/68360/head-ram.S 281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * 381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * Startup code for Motorola 68360 481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * 581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * Copyright 2001 (C) SED Systems, a Division of Calian Ltd. 681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S 781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7 881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * uClinux Kernel 981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * Copyright (C) Michael Leslie <mleslie@lineo.com> 1081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S 1181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>, 1281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * 1381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer */ 1481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define ASSEMBLY 1581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 1681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer.global _stext 1781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer.global _start 1881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 1981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer.global _rambase 2081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer.global _ramvec 2181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer.global _ramstart 2281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer.global _ramend 2381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 2481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer.global _quicc_base 2581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer.global _periph_base 2681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 27d046f6118bb2a207870e35db1411b958199a3750Greg Ungerer#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE) 28d773c660973560970a6b3697cb280ddc5389447dGreg Ungerer#define ROMEND (CONFIG_ROMBASE + CONFIG_ROMSIZE) 29d046f6118bb2a207870e35db1411b958199a3750Greg Ungerer 3081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define REGB 0x1000 3181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define PEPAR (_dprbase + REGB + 0x0016) 3281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define GMR (_dprbase + REGB + 0x0040) 3381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define OR0 (_dprbase + REGB + 0x0054) 3481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define BR0 (_dprbase + REGB + 0x0050) 3581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define OR1 (_dprbase + REGB + 0x0064) 3681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define BR1 (_dprbase + REGB + 0x0060) 3781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define OR4 (_dprbase + REGB + 0x0094) 3881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define BR4 (_dprbase + REGB + 0x0090) 3981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define OR6 (_dprbase + REGB + 0x00b4) 4081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define BR6 (_dprbase + REGB + 0x00b0) 4181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define OR7 (_dprbase + REGB + 0x00c4) 4281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define BR7 (_dprbase + REGB + 0x00c0) 4381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 4481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCR (_dprbase + REGB + 0x0000) 4581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define AVR (_dprbase + REGB + 0x0008) 4681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 4781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define SYPCR (_dprbase + REGB + 0x0022) 4881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 4981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define PLLCR (_dprbase + REGB + 0x0010) 5081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define CLKOCR (_dprbase + REGB + 0x000C) 5181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define CDVCR (_dprbase + REGB + 0x0014) 5281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 5381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define BKAR (_dprbase + REGB + 0x0030) 5481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define BKCR (_dprbase + REGB + 0x0034) 5581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define SWIV (_dprbase + REGB + 0x0023) 5681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define PICR (_dprbase + REGB + 0x0026) 5781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define PITR (_dprbase + REGB + 0x002A) 5881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 5981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer/* Define for all memory configuration */ 6081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_GMR 0x00000000 6181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define SIM_OR_MASK 0x0fffffff 6281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 6381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer/* Defines for chip select zero - the flash */ 6481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define SIM_OR0_MASK 0x20000002 6581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define SIM_BR0_MASK 0x00000001 6681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 6781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 6881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer/* Defines for chip select one - the RAM */ 6981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define SIM_OR1_MASK 0x10000000 7081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define SIM_BR1_MASK 0x00000001 7181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 7281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_MBAR_ADRS 0x0003ff00 7381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_MBAR_BA_MASK 0xfffff000 7481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_MBAR_AS_MASK 0x00000001 7581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 7681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_PEPAR 0x00B4 7781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 7881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_DISABLE_INTRPTS 0x2700 7981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_AVR 0x00 8081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 8181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_MCR 0x00005cff 8281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 8381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_CLKOCR 0x00 8481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_PLLCR 0x8000 8581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_CDVCR 0x0000 8681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 8781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_SYPCR 0x0000 8881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_SWIV 0x00 8981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_PICR 0x0000 9081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#define MCU_SIM_PITR 0x0000 9181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 9281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 9381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer#include <asm/m68360_regs.h> 9481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 9581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 9681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer/* 9781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * By the time this RAM specific code begins to execute, DPRAM 9881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * and DRAM should already be mapped and accessible. 9981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer */ 10081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 10181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .text 10281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_start: 10381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_stext: 10481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer nop 10581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */ 10681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* We should not need to setup the boot stack the reset should do it. */ 107d046f6118bb2a207870e35db1411b958199a3750Greg Ungerer movea.l #RAMEND, %sp /*set up stack at the end of DRAM:*/ 10881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 10981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererset_mbar_register: 11081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer moveq.l #0x07, %d1 /* Setup MBAR */ 11181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer movec %d1, %dfc 11281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 11381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer lea.l MCU_SIM_MBAR_ADRS, %a0 11481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #_dprbase, %d0 11581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer andi.l #MCU_SIM_MBAR_BA_MASK, %d0 11681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer ori.l #MCU_SIM_MBAR_AS_MASK, %d0 11781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer moves.l %d0, %a0@ 11881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 11981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer moveq.l #0x05, %d1 12081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer movec.l %d1, %dfc 12181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 12281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Now we can begin to access registers in DPRAM */ 12381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 12481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererset_sim_mcr: 12581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Set Module Configuration Register */ 12681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #MCU_SIM_MCR, MCR 12781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 12881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* to do: Determine cause of reset */ 12981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 13081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* 13181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * configure system clock MC68360 p. 6-40 13281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * (value +1)*osc/128 = system clock 13381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer */ 13481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererset_sim_clock: 13581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.w #MCU_SIM_PLLCR, PLLCR 13681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.b #MCU_SIM_CLKOCR, CLKOCR 13781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.w #MCU_SIM_CDVCR, CDVCR 13881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 13981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Wait for the PLL to settle */ 14081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.w #16384, %d0 14181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererpll_settle_wait: 14281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer subi.w #1, %d0 14381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer bne pll_settle_wait 14481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 14581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Setup the system protection register, and watchdog timer register */ 14681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.b #MCU_SIM_SWIV, SWIV 14781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.w #MCU_SIM_PICR, PICR 14881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.w #MCU_SIM_PITR, PITR 14981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.w #MCU_SIM_SYPCR, SYPCR 15081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 15181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Clear DPRAM - system + parameter */ 15281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer movea.l #_dprbase, %a0 15381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer movea.l #_dprbase+0x2000, %a1 15481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 15581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Copy 0 to %a0 until %a0 == %a1 */ 15681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererclear_dpram: 15781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer movel #0, %a0@+ 15881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer cmpal %a0, %a1 15981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer bhi clear_dpram 16081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 16181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererconfigure_memory_controller: 16281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Set up Global Memory Register (GMR) */ 16381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #MCU_SIM_GMR, %d0 16481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %d0, GMR 16581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 16681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererconfigure_chip_select_0: 167d046f6118bb2a207870e35db1411b958199a3750Greg Ungerer move.l #RAMEND, %d0 16881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer subi.l #__ramstart, %d0 16981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer subq.l #0x01, %d0 17081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer eori.l #SIM_OR_MASK, %d0 17181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer ori.l #SIM_OR0_MASK, %d0 17281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %d0, OR0 17381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 17481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #__ramstart, %d0 17581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer ori.l #SIM_BR0_MASK, %d0 17681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %d0, BR0 17781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 17881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererconfigure_chip_select_1: 179d773c660973560970a6b3697cb280ddc5389447dGreg Ungerer move.l #ROMEND, %d0 18081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer subi.l #__rom_start, %d0 18181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer subq.l #0x01, %d0 18281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer eori.l #SIM_OR_MASK, %d0 18381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer ori.l #SIM_OR1_MASK, %d0 18481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %d0, OR1 18581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 18681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #__rom_start, %d0 18781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer ori.l #SIM_BR1_MASK, %d0 18881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %d0, BR1 18981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 19081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.w #MCU_SIM_PEPAR, PEPAR 19181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 19281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* point to vector table: */ 19381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #_romvec, %a0 19481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #_ramvec, %a1 19581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerercopy_vectors: 19681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %a0@, %d0 19781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %d0, %a1@ 19881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %a0@, %a1@ 19981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer addq.l #0x04, %a0 20081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer addq.l #0x04, %a1 20181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer cmp.l #_start, %a0 20281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer blt copy_vectors 20381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 20481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #_ramvec, %a1 20581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer movec %a1, %vbr 20681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 20781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 20881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Copy data segment from ROM to RAM */ 20981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer moveal #_stext, %a0 21081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer moveal #_sdata, %a1 21181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer moveal #_edata, %a2 21281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 21381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Copy %a0 to %a1 until %a1 == %a2 */ 21481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg UngererLD1: 21581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %a0@, %d0 21681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer addq.l #0x04, %a0 21781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l %d0, %a1@ 21881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer addq.l #0x04, %a1 21981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer cmp.l #_edata, %a1 22081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer blt LD1 22181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 22281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer moveal #_sbss, %a0 22381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer moveal #_ebss, %a1 22481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 22581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Copy 0 to %a0 until %a0 == %a1 */ 22681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg UngererL1: 22781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer movel #0, %a0@+ 22881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer cmpal %a0, %a1 22981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer bhi L1 23081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 23181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererload_quicc: 23281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #_dprbase, _quicc_base 23381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 23481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererstore_ram_size: 23581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* Set ram size information */ 23681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #_sdata, _rambase 23781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer move.l #_ebss, _ramstart 238d046f6118bb2a207870e35db1411b958199a3750Greg Ungerer move.l #RAMEND, %d0 23981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/ 240d046f6118bb2a207870e35db1411b958199a3750Greg Ungerer move.l %d0, _ramend /* Different from RAMEND.*/ 24181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 24281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer pea 0 24381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer pea env 24481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer pea %sp@(4) 24581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer pea 0 24681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 24781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer lea init_thread_union, %a2 24881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer lea 0x2000(%a2), %sp 24981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 25081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererlp: 25181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer jsr start_kernel 25281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 25381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_exit: 25481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer jmp _exit 25581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 25681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 25781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .data 25881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .align 4 25981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererenv: 26081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 26181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_quicc_base: 26281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 26381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_periph_base: 26481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 26581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_ramvec: 26681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 26781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_rambase: 26881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 26981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_ramstart: 27081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 27181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_ramend: 27281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 27381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer_dprbase: 27481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0xffffe000 27581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 27681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .text 27781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 27881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* 27981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * These are the exception vectors at boot up, they are copied into RAM 28081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer * and then overwritten as needed. 28181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer */ 28281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer 2832c31c341a827b99eef743753aa9adb917b9ea6dbDenys Vlasenko.section ".data..initvect","awx" 284d046f6118bb2a207870e35db1411b958199a3750Greg Ungerer .long RAMEND /* Reset: Initial Stack Pointer - 0. */ 28581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long _start /* Reset: Initial Program Counter - 1. */ 28681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long buserr /* Bus Error - 2. */ 28781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Address Error - 3. */ 28881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Illegal Instruction - 4. */ 28981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Divide by zero - 5. */ 29081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* CHK, CHK2 Instructions - 6. */ 29181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* TRAPcc, TRAPV Instructions - 7. */ 29281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Privilege Violation - 8. */ 29381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trace - 9. */ 29481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Line 1010 Emulator - 10. */ 29581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Line 1111 Emualtor - 11. */ 29681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Harware Breakpoint - 12. */ 29781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */ 29881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Format Error - 14. */ 29981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Uninitialized Interrupt - 15. */ 30081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* (Unassigned, Reserver) - 16. */ 30181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* (Unassigned, Reserver) - 17. */ 30281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* (Unassigned, Reserver) - 18. */ 30381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* (Unassigned, Reserver) - 19. */ 30481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* (Unassigned, Reserver) - 20. */ 30581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* (Unassigned, Reserver) - 21. */ 30681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* (Unassigned, Reserver) - 22. */ 30781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* (Unassigned, Reserver) - 23. */ 30881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Spurious Interrupt - 24. */ 30981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Level 1 Interrupt Autovector - 25. */ 31081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Level 2 Interrupt Autovector - 26. */ 31181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Level 3 Interrupt Autovector - 27. */ 31281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Level 4 Interrupt Autovector - 28. */ 31381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Level 5 Interrupt Autovector - 29. */ 31481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Level 6 Interrupt Autovector - 30. */ 31581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Level 7 Interrupt Autovector - 31. */ 31681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long system_call /* Trap Instruction Vectors 0 - 32. */ 31781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 1 - 33. */ 31881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 2 - 34. */ 31981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 3 - 35. */ 32081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 4 - 36. */ 32181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 5 - 37. */ 32281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 6 - 38. */ 32381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 7 - 39. */ 32481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 8 - 40. */ 32581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 9 - 41. */ 32681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 10 - 42. */ 32781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 11 - 43. */ 32881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 12 - 44. */ 32981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 13 - 45. */ 33081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 14 - 46. */ 33181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long trap /* Trap Instruction Vectors 15 - 47. */ 33281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 48. */ 33381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 49. */ 33481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 50. */ 33581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 51. */ 33681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 52. */ 33781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 53. */ 33881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 54. */ 33981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 55. */ 34081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 56. */ 34181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 57. */ 34281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Reserved for Coprocessor) - 58. */ 34381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Unassigned, Reserved) - 59. */ 34481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Unassigned, Reserved) - 60. */ 34581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Unassigned, Reserved) - 61. */ 34681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Unassigned, Reserved) - 62. */ 34781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (Unassigned, Reserved) - 63. */ 34881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* The assignment of these vectors to the CPM is */ 34981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* dependent on the configuration of the CPM vba */ 35081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* fields. */ 35181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */ 35281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */ 35381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */ 35481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */ 35581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */ 35681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */ 35781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */ 35881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */ 35981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */ 36081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */ 36181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */ 36281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */ 36381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */ 36481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */ 36581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */ 36681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */ 36781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */ 36881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */ 36981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */ 37081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */ 37181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */ 37281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */ 37381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */ 37481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */ 37581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */ 37681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */ 37781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */ 37881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */ 37981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */ 38081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */ 38181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */ 38281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */ 38381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer /* I don't think anything uses the vectors after here. */ 38481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0 /* (User-Defined Vectors 34) - 96. */ 38581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */ 38681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */ 38781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */ 38881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */ 38981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */ 39081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */ 39181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */ 39281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */ 39381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */ 39481d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */ 39581d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */ 39681d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */ 39781d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */ 39881d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */ 39981d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */ 40081d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */ 40181d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer .long 0,0,0 /* (User-Defined Vectors 190 - 192). */ 40281d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungerer.text 40381d4903d2d17a9f33ece2666185a8b51e6935ae0Greg Ungererignore: rte 404