1/* 2 * head-rom.S - startup code for Motorola 68360 3 * 4 * Copyright (C) SED Systems, a Division of Calian Ltd. 5 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S 6 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7 7 * uClinux Kernel 8 * Copyright (C) Michael Leslie <mleslie@lineo.com> 9 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S 10 * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>, 11 * 12 */ 13 14.global _stext 15.global __bss_start 16.global _start 17 18.global _rambase 19.global _ramvec 20.global _ramstart 21.global _ramend 22 23.global _quicc_base 24.global _periph_base 25 26#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE) 27 28#define REGB 0x1000 29#define PEPAR (_dprbase + REGB + 0x0016) 30#define GMR (_dprbase + REGB + 0x0040) 31#define OR0 (_dprbase + REGB + 0x0054) 32#define BR0 (_dprbase + REGB + 0x0050) 33 34#define OR1 (_dprbase + REGB + 0x0064) 35#define BR1 (_dprbase + REGB + 0x0060) 36 37#define OR2 (_dprbase + REGB + 0x0074) 38#define BR2 (_dprbase + REGB + 0x0070) 39 40#define OR3 (_dprbase + REGB + 0x0084) 41#define BR3 (_dprbase + REGB + 0x0080) 42 43#define OR4 (_dprbase + REGB + 0x0094) 44#define BR4 (_dprbase + REGB + 0x0090) 45 46#define OR5 (_dprbase + REGB + 0x00A4) 47#define BR5 (_dprbase + REGB + 0x00A0) 48 49#define OR6 (_dprbase + REGB + 0x00b4) 50#define BR6 (_dprbase + REGB + 0x00b0) 51 52#define OR7 (_dprbase + REGB + 0x00c4) 53#define BR7 (_dprbase + REGB + 0x00c0) 54 55#define MCR (_dprbase + REGB + 0x0000) 56#define AVR (_dprbase + REGB + 0x0008) 57 58#define SYPCR (_dprbase + REGB + 0x0022) 59 60#define PLLCR (_dprbase + REGB + 0x0010) 61#define CLKOCR (_dprbase + REGB + 0x000C) 62#define CDVCR (_dprbase + REGB + 0x0014) 63 64#define BKAR (_dprbase + REGB + 0x0030) 65#define BKCR (_dprbase + REGB + 0x0034) 66#define SWIV (_dprbase + REGB + 0x0023) 67#define PICR (_dprbase + REGB + 0x0026) 68#define PITR (_dprbase + REGB + 0x002A) 69 70/* Define for all memory configuration */ 71#define MCU_SIM_GMR 0x00000000 72#define SIM_OR_MASK 0x0fffffff 73 74/* Defines for chip select zero - the flash */ 75#define SIM_OR0_MASK 0x20000000 76#define SIM_BR0_MASK 0x00000001 77 78/* Defines for chip select one - the RAM */ 79#define SIM_OR1_MASK 0x10000000 80#define SIM_BR1_MASK 0x00000001 81 82#define MCU_SIM_MBAR_ADRS 0x0003ff00 83#define MCU_SIM_MBAR_BA_MASK 0xfffff000 84#define MCU_SIM_MBAR_AS_MASK 0x00000001 85 86#define MCU_SIM_PEPAR 0x00B4 87 88#define MCU_DISABLE_INTRPTS 0x2700 89#define MCU_SIM_AVR 0x00 90 91#define MCU_SIM_MCR 0x00005cff 92 93#define MCU_SIM_CLKOCR 0x00 94#define MCU_SIM_PLLCR 0x8000 95#define MCU_SIM_CDVCR 0x0000 96 97#define MCU_SIM_SYPCR 0x0000 98#define MCU_SIM_SWIV 0x00 99#define MCU_SIM_PICR 0x0000 100#define MCU_SIM_PITR 0x0000 101 102 103#include <asm/m68360_regs.h> 104 105 106/* 107 * By the time this RAM specific code begins to execute, DPRAM 108 * and DRAM should already be mapped and accessible. 109 */ 110 111 .text 112_start: 113_stext: 114 nop 115 ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */ 116 /* We should not need to setup the boot stack the reset should do it. */ 117 movea.l #RAMEND, %sp /* set up stack at the end of DRAM:*/ 118 119 120set_mbar_register: 121 moveq.l #0x07, %d1 /* Setup MBAR */ 122 movec %d1, %dfc 123 124 lea.l MCU_SIM_MBAR_ADRS, %a0 125 move.l #_dprbase, %d0 126 andi.l #MCU_SIM_MBAR_BA_MASK, %d0 127 ori.l #MCU_SIM_MBAR_AS_MASK, %d0 128 moves.l %d0, %a0@ 129 130 moveq.l #0x05, %d1 131 movec.l %d1, %dfc 132 133 /* Now we can begin to access registers in DPRAM */ 134 135set_sim_mcr: 136 /* Set Module Configuration Register */ 137 move.l #MCU_SIM_MCR, MCR 138 139 /* to do: Determine cause of reset */ 140 141 /* 142 * configure system clock MC68360 p. 6-40 143 * (value +1)*osc/128 = system clock 144 * or 145 * (value + 1)*osc = system clock 146 * You do not need to divide the oscillator by 128 unless you want to. 147 */ 148set_sim_clock: 149 move.w #MCU_SIM_PLLCR, PLLCR 150 move.b #MCU_SIM_CLKOCR, CLKOCR 151 move.w #MCU_SIM_CDVCR, CDVCR 152 153 /* Wait for the PLL to settle */ 154 move.w #16384, %d0 155pll_settle_wait: 156 subi.w #1, %d0 157 bne pll_settle_wait 158 159 /* Setup the system protection register, and watchdog timer register */ 160 move.b #MCU_SIM_SWIV, SWIV 161 move.w #MCU_SIM_PICR, PICR 162 move.w #MCU_SIM_PITR, PITR 163 move.w #MCU_SIM_SYPCR, SYPCR 164 165 /* Clear DPRAM - system + parameter */ 166 movea.l #_dprbase, %a0 167 movea.l #_dprbase+0x2000, %a1 168 169 /* Copy 0 to %a0 until %a0 == %a1 */ 170clear_dpram: 171 movel #0, %a0@+ 172 cmpal %a0, %a1 173 bhi clear_dpram 174 175configure_memory_controller: 176 /* Set up Global Memory Register (GMR) */ 177 move.l #MCU_SIM_GMR, %d0 178 move.l %d0, GMR 179 180configure_chip_select_0: 181 move.l #0x00400000, %d0 182 subq.l #0x01, %d0 183 eori.l #SIM_OR_MASK, %d0 184 ori.l #SIM_OR0_MASK, %d0 185 move.l %d0, OR0 186 187 move.l #__rom_start, %d0 188 ori.l #SIM_BR0_MASK, %d0 189 move.l %d0, BR0 190 191 move.l #0x0, BR1 192 move.l #0x0, BR2 193 move.l #0x0, BR3 194 move.l #0x0, BR4 195 move.l #0x0, BR5 196 move.l #0x0, BR6 197 move.l #0x0, BR7 198 199 move.w #MCU_SIM_PEPAR, PEPAR 200 201 /* point to vector table: */ 202 move.l #_romvec, %a0 203 move.l #_ramvec, %a1 204copy_vectors: 205 move.l %a0@, %d0 206 move.l %d0, %a1@ 207 move.l %a0@, %a1@ 208 addq.l #0x04, %a0 209 addq.l #0x04, %a1 210 cmp.l #_start, %a0 211 blt copy_vectors 212 213 move.l #_ramvec, %a1 214 movec %a1, %vbr 215 216 217 /* Copy data segment from ROM to RAM */ 218 moveal #_etext, %a0 219 moveal #_sdata, %a1 220 moveal #_edata, %a2 221 222 /* Copy %a0 to %a1 until %a1 == %a2 */ 223LD1: 224 move.l %a0@, %d0 225 addq.l #0x04, %a0 226 move.l %d0, %a1@ 227 addq.l #0x04, %a1 228 cmp.l #_edata, %a1 229 blt LD1 230 231 moveal #__bss_start, %a0 232 moveal #__bss_stop, %a1 233 234 /* Copy 0 to %a0 until %a0 == %a1 */ 235L1: 236 movel #0, %a0@+ 237 cmpal %a0, %a1 238 bhi L1 239 240load_quicc: 241 move.l #_dprbase, _quicc_base 242 243store_ram_size: 244 /* Set ram size information */ 245 move.l #_sdata, _rambase 246 move.l #__bss_stop, _ramstart 247 move.l #RAMEND, %d0 248 sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/ 249 move.l %d0, _ramend /* Different from RAMEND.*/ 250 251 pea 0 252 pea env 253 pea %sp@(4) 254 pea 0 255 256 lea init_thread_union, %a2 257 lea 0x2000(%a2), %sp 258 259lp: 260 jsr start_kernel 261 262_exit: 263 jmp _exit 264 265 266 .data 267 .align 4 268env: 269 .long 0 270_quicc_base: 271 .long 0 272_periph_base: 273 .long 0 274_ramvec: 275 .long 0 276_rambase: 277 .long 0 278_ramstart: 279 .long 0 280_ramend: 281 .long 0 282_dprbase: 283 .long 0xffffe000 284 285 286 .text 287 288 /* 289 * These are the exception vectors at boot up, they are copied into RAM 290 * and then overwritten as needed. 291 */ 292 293.section ".data..initvect","awx" 294 .long RAMEND /* Reset: Initial Stack Pointer - 0. */ 295 .long _start /* Reset: Initial Program Counter - 1. */ 296 .long buserr /* Bus Error - 2. */ 297 .long trap /* Address Error - 3. */ 298 .long trap /* Illegal Instruction - 4. */ 299 .long trap /* Divide by zero - 5. */ 300 .long trap /* CHK, CHK2 Instructions - 6. */ 301 .long trap /* TRAPcc, TRAPV Instructions - 7. */ 302 .long trap /* Privilege Violation - 8. */ 303 .long trap /* Trace - 9. */ 304 .long trap /* Line 1010 Emulator - 10. */ 305 .long trap /* Line 1111 Emualtor - 11. */ 306 .long trap /* Harware Breakpoint - 12. */ 307 .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */ 308 .long trap /* Format Error - 14. */ 309 .long trap /* Uninitialized Interrupt - 15. */ 310 .long trap /* (Unassigned, Reserver) - 16. */ 311 .long trap /* (Unassigned, Reserver) - 17. */ 312 .long trap /* (Unassigned, Reserver) - 18. */ 313 .long trap /* (Unassigned, Reserver) - 19. */ 314 .long trap /* (Unassigned, Reserver) - 20. */ 315 .long trap /* (Unassigned, Reserver) - 21. */ 316 .long trap /* (Unassigned, Reserver) - 22. */ 317 .long trap /* (Unassigned, Reserver) - 23. */ 318 .long trap /* Spurious Interrupt - 24. */ 319 .long trap /* Level 1 Interrupt Autovector - 25. */ 320 .long trap /* Level 2 Interrupt Autovector - 26. */ 321 .long trap /* Level 3 Interrupt Autovector - 27. */ 322 .long trap /* Level 4 Interrupt Autovector - 28. */ 323 .long trap /* Level 5 Interrupt Autovector - 29. */ 324 .long trap /* Level 6 Interrupt Autovector - 30. */ 325 .long trap /* Level 7 Interrupt Autovector - 31. */ 326 .long system_call /* Trap Instruction Vectors 0 - 32. */ 327 .long trap /* Trap Instruction Vectors 1 - 33. */ 328 .long trap /* Trap Instruction Vectors 2 - 34. */ 329 .long trap /* Trap Instruction Vectors 3 - 35. */ 330 .long trap /* Trap Instruction Vectors 4 - 36. */ 331 .long trap /* Trap Instruction Vectors 5 - 37. */ 332 .long trap /* Trap Instruction Vectors 6 - 38. */ 333 .long trap /* Trap Instruction Vectors 7 - 39. */ 334 .long trap /* Trap Instruction Vectors 8 - 40. */ 335 .long trap /* Trap Instruction Vectors 9 - 41. */ 336 .long trap /* Trap Instruction Vectors 10 - 42. */ 337 .long trap /* Trap Instruction Vectors 11 - 43. */ 338 .long trap /* Trap Instruction Vectors 12 - 44. */ 339 .long trap /* Trap Instruction Vectors 13 - 45. */ 340 .long trap /* Trap Instruction Vectors 14 - 46. */ 341 .long trap /* Trap Instruction Vectors 15 - 47. */ 342 .long 0 /* (Reserved for Coprocessor) - 48. */ 343 .long 0 /* (Reserved for Coprocessor) - 49. */ 344 .long 0 /* (Reserved for Coprocessor) - 50. */ 345 .long 0 /* (Reserved for Coprocessor) - 51. */ 346 .long 0 /* (Reserved for Coprocessor) - 52. */ 347 .long 0 /* (Reserved for Coprocessor) - 53. */ 348 .long 0 /* (Reserved for Coprocessor) - 54. */ 349 .long 0 /* (Reserved for Coprocessor) - 55. */ 350 .long 0 /* (Reserved for Coprocessor) - 56. */ 351 .long 0 /* (Reserved for Coprocessor) - 57. */ 352 .long 0 /* (Reserved for Coprocessor) - 58. */ 353 .long 0 /* (Unassigned, Reserved) - 59. */ 354 .long 0 /* (Unassigned, Reserved) - 60. */ 355 .long 0 /* (Unassigned, Reserved) - 61. */ 356 .long 0 /* (Unassigned, Reserved) - 62. */ 357 .long 0 /* (Unassigned, Reserved) - 63. */ 358 /* The assignment of these vectors to the CPM is */ 359 /* dependent on the configuration of the CPM vba */ 360 /* fields. */ 361 .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */ 362 .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */ 363 .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */ 364 .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */ 365 .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */ 366 .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */ 367 .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */ 368 .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */ 369 .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */ 370 .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */ 371 .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */ 372 .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */ 373 .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */ 374 .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */ 375 .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */ 376 .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */ 377 .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */ 378 .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */ 379 .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */ 380 .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */ 381 .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */ 382 .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */ 383 .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */ 384 .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */ 385 .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */ 386 .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */ 387 .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */ 388 .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */ 389 .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */ 390 .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */ 391 .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */ 392 .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */ 393 /* I don't think anything uses the vectors after here. */ 394 .long 0 /* (User-Defined Vectors 34) - 96. */ 395 .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */ 396 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */ 397 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */ 398 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */ 399 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */ 400 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */ 401 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */ 402 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */ 403 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */ 404 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */ 405 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */ 406 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */ 407 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */ 408 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */ 409 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */ 410 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */ 411 .long 0,0,0 /* (User-Defined Vectors 190 - 192). */ 412.text 413ignore: rte 414