1ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman/* 2ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman * This file is subject to the terms and conditions of the GNU General Public 3ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman * License. See the file "COPYING" in the main directory of this archive 4ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman * for more details. 5ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman * 6ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman * Chris Dearman (chris@mips.com) 7ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman * Copyright (C) 2007 Mips Technologies, Inc. 8f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * Copyright (C) 2014 Imagination Technologies Ltd. 9ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman */ 10ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H 11ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H 12ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman 13ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras#include <asm/regdef.h> 14ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras#include <asm/mipsregs.h> 15ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras 16f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras /* 17f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * Prepare segments for EVA boot: 18f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 19f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * This is in case the processor boots in legacy configuration 20f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * (SI_EVAReset is de-asserted and CONFIG5.K == 0) 21f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 22f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * ========================= Mappings ============================= 23f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * Virtual memory Physical memory Mapping 24f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg) 25f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * Flat 2GB physical memory 26f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 27f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0) 28f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1) 29f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 0xc0000000 - 0xdfffffff - MK (kseg2) 30f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 0xe0000000 - 0xffffffff - MK (kseg3) 31f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 32f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * 33f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * Lowmem is expanded to 2GB 34ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras * 35ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras * The following code uses the t0, t1, t2 and ra registers without 36ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras * previously preserving them. 37ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras * 38f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras */ 39ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras .macro platform_eva_init 40ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras 41ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras .set push 42ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras .set reorder 43f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras /* 44f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * Get Config.K0 value and use it to program 45f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras * the segmentation registers 46f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras */ 47ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras mfc0 t1, CP0_CONFIG 48f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras andi t1, 0x7 /* CCA */ 49f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras move t2, t1 50f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras ins t2, t1, 16, 3 51f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras /* SegCtl0 */ 52f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras li t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \ 53f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (0 << MIPS_SEGCFG_PA_SHIFT) | \ 54f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (1 << MIPS_SEGCFG_EU_SHIFT)) | \ 55f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \ 56f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (0 << MIPS_SEGCFG_PA_SHIFT) | \ 57f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) 58f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras or t0, t2 59f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras mtc0 t0, $5, 2 60f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras 61f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras /* SegCtl1 */ 62f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 63f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (0 << MIPS_SEGCFG_PA_SHIFT) | \ 64f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (2 << MIPS_SEGCFG_C_SHIFT) | \ 65f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (1 << MIPS_SEGCFG_EU_SHIFT)) | \ 66f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 67f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (0 << MIPS_SEGCFG_PA_SHIFT) | \ 68f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) 69f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras ins t0, t1, 16, 3 70f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras mtc0 t0, $5, 3 71f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras 72f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras /* SegCtl2 */ 73f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 74f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (6 << MIPS_SEGCFG_PA_SHIFT) | \ 75f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (1 << MIPS_SEGCFG_EU_SHIFT)) | \ 76f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ 77f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (4 << MIPS_SEGCFG_PA_SHIFT) | \ 78f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras (1 << MIPS_SEGCFG_EU_SHIFT)) << 16) 79f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras or t0, t2 80f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras mtc0 t0, $5, 4 81f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras 82f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras jal mips_ihb 83f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras mfc0 t0, $16, 5 84f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras li t2, 0x40000000 /* K bit */ 85f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras or t0, t0, t2 86f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras mtc0 t0, $16, 5 87f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras sync 88f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras jal mips_ihb 89ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras 90ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras .set pop 91f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras .endm 92f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras 93ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman .macro kernel_entry_setup 94f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras 95f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras#ifdef CONFIG_EVA 96f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras sync 97f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras ehb 98f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras 99f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras mfc0 t1, CP0_CONFIG 100f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras bgez t1, 9f 101f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras mfc0 t0, CP0_CONFIG, 1 102f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras bgez t0, 9f 103f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras mfc0 t0, CP0_CONFIG, 2 104f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras bgez t0, 9f 105f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras mfc0 t0, CP0_CONFIG, 3 106f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras sll t0, t0, 6 /* SC bit */ 107f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras bgez t0, 9f 108f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras 109ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras platform_eva_init 110f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras b 0f 111f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras9: 112f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras /* Assume we came from YAMON... */ 113f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras PTR_LA v0, 0x9fc00534 /* YAMON print */ 114f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras lw v0, (v0) 115f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras move a0, zero 116f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras PTR_LA a1, nonsc_processor 117f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras jal v0 118f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras 119f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras PTR_LA v0, 0x9fc00520 /* YAMON exit */ 120f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras lw v0, (v0) 121f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras li a0, 1 122f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras jal v0 123f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras 124f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras1: b 1b 125f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras nop 126f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras __INITDATA 127f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandrasnonsc_processor: 128f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras .asciz "EVA kernel requires a MIPS core with Segment Control implemented\n" 129f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras __FINIT 130f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras#endif /* CONFIG_EVA */ 131f8b7faf17b36af3f2d0db0dbd3e60358965152faMarkos Chandras0: 132ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman .endm 133ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman 134ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman/* 135ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman * Do SMP slave processor setup necessary before we can safely execute C code. 136ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman */ 137ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman .macro smp_slave_setup 138d0ba3544a5ca185f69688fa0b51b187d3e78e31aMarkos Chandras#ifdef CONFIG_EVA 139d0ba3544a5ca185f69688fa0b51b187d3e78e31aMarkos Chandras sync 140d0ba3544a5ca185f69688fa0b51b187d3e78e31aMarkos Chandras ehb 141ca4d24f7954f3746742ba350c2276ff777f21173Markos Chandras platform_eva_init 142d0ba3544a5ca185f69688fa0b51b187d3e78e31aMarkos Chandras#endif 143ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman .endm 144ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman 145ecd27b92fbb41f779d857632a69bd45dbaf0f915Chris Dearman#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */ 146