1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13#ifndef _ASM_MIPSREGS_H 14#define _ASM_MIPSREGS_H 15 16#include <linux/linkage.h> 17#include <linux/types.h> 18#include <asm/hazards.h> 19#include <asm/war.h> 20 21/* 22 * The following macros are especially useful for __asm__ 23 * inline assembler. 24 */ 25#ifndef __STR 26#define __STR(x) #x 27#endif 28#ifndef STR 29#define STR(x) __STR(x) 30#endif 31 32/* 33 * Configure language 34 */ 35#ifdef __ASSEMBLY__ 36#define _ULCAST_ 37#else 38#define _ULCAST_ (unsigned long) 39#endif 40 41/* 42 * Coprocessor 0 register names 43 */ 44#define CP0_INDEX $0 45#define CP0_RANDOM $1 46#define CP0_ENTRYLO0 $2 47#define CP0_ENTRYLO1 $3 48#define CP0_CONF $3 49#define CP0_CONTEXT $4 50#define CP0_PAGEMASK $5 51#define CP0_WIRED $6 52#define CP0_INFO $7 53#define CP0_BADVADDR $8 54#define CP0_COUNT $9 55#define CP0_ENTRYHI $10 56#define CP0_COMPARE $11 57#define CP0_STATUS $12 58#define CP0_CAUSE $13 59#define CP0_EPC $14 60#define CP0_PRID $15 61#define CP0_CONFIG $16 62#define CP0_LLADDR $17 63#define CP0_WATCHLO $18 64#define CP0_WATCHHI $19 65#define CP0_XCONTEXT $20 66#define CP0_FRAMEMASK $21 67#define CP0_DIAGNOSTIC $22 68#define CP0_DEBUG $23 69#define CP0_DEPC $24 70#define CP0_PERFORMANCE $25 71#define CP0_ECC $26 72#define CP0_CACHEERR $27 73#define CP0_TAGLO $28 74#define CP0_TAGHI $29 75#define CP0_ERROREPC $30 76#define CP0_DESAVE $31 77 78/* 79 * R4640/R4650 cp0 register names. These registers are listed 80 * here only for completeness; without MMU these CPUs are not useable 81 * by Linux. A future ELKS port might take make Linux run on them 82 * though ... 83 */ 84#define CP0_IBASE $0 85#define CP0_IBOUND $1 86#define CP0_DBASE $2 87#define CP0_DBOUND $3 88#define CP0_CALG $17 89#define CP0_IWATCH $18 90#define CP0_DWATCH $19 91 92/* 93 * Coprocessor 0 Set 1 register names 94 */ 95#define CP0_S1_DERRADDR0 $26 96#define CP0_S1_DERRADDR1 $27 97#define CP0_S1_INTCONTROL $20 98 99/* 100 * Coprocessor 0 Set 2 register names 101 */ 102#define CP0_S2_SRSCTL $12 /* MIPSR2 */ 103 104/* 105 * Coprocessor 0 Set 3 register names 106 */ 107#define CP0_S3_SRSMAP $12 /* MIPSR2 */ 108 109/* 110 * TX39 Series 111 */ 112#define CP0_TX39_CACHE $7 113 114/* 115 * Coprocessor 1 (FPU) register names 116 */ 117#define CP1_REVISION $0 118#define CP1_STATUS $31 119 120/* 121 * FPU Status Register Values 122 */ 123/* 124 * Status Register Values 125 */ 126 127#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 128#define FPU_CSR_COND 0x00800000 /* $fcc0 */ 129#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 130#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 131#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 132#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 133#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 134#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 135#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 136#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 137 138/* 139 * Bits 18 - 20 of the FPU Status Register will be read as 0, 140 * and should be written as zero. 141 */ 142#define FPU_CSR_RSVD 0x001c0000 143 144/* 145 * X the exception cause indicator 146 * E the exception enable 147 * S the sticky/flag bit 148*/ 149#define FPU_CSR_ALL_X 0x0003f000 150#define FPU_CSR_UNI_X 0x00020000 151#define FPU_CSR_INV_X 0x00010000 152#define FPU_CSR_DIV_X 0x00008000 153#define FPU_CSR_OVF_X 0x00004000 154#define FPU_CSR_UDF_X 0x00002000 155#define FPU_CSR_INE_X 0x00001000 156 157#define FPU_CSR_ALL_E 0x00000f80 158#define FPU_CSR_INV_E 0x00000800 159#define FPU_CSR_DIV_E 0x00000400 160#define FPU_CSR_OVF_E 0x00000200 161#define FPU_CSR_UDF_E 0x00000100 162#define FPU_CSR_INE_E 0x00000080 163 164#define FPU_CSR_ALL_S 0x0000007c 165#define FPU_CSR_INV_S 0x00000040 166#define FPU_CSR_DIV_S 0x00000020 167#define FPU_CSR_OVF_S 0x00000010 168#define FPU_CSR_UDF_S 0x00000008 169#define FPU_CSR_INE_S 0x00000004 170 171/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 172#define FPU_CSR_RM 0x00000003 173#define FPU_CSR_RN 0x0 /* nearest */ 174#define FPU_CSR_RZ 0x1 /* towards zero */ 175#define FPU_CSR_RU 0x2 /* towards +Infinity */ 176#define FPU_CSR_RD 0x3 /* towards -Infinity */ 177 178 179/* 180 * Values for PageMask register 181 */ 182#ifdef CONFIG_CPU_VR41XX 183 184/* Why doesn't stupidity hurt ... */ 185 186#define PM_1K 0x00000000 187#define PM_4K 0x00001800 188#define PM_16K 0x00007800 189#define PM_64K 0x0001f800 190#define PM_256K 0x0007f800 191 192#else 193 194#define PM_4K 0x00000000 195#define PM_8K 0x00002000 196#define PM_16K 0x00006000 197#define PM_32K 0x0000e000 198#define PM_64K 0x0001e000 199#define PM_128K 0x0003e000 200#define PM_256K 0x0007e000 201#define PM_512K 0x000fe000 202#define PM_1M 0x001fe000 203#define PM_2M 0x003fe000 204#define PM_4M 0x007fe000 205#define PM_8M 0x00ffe000 206#define PM_16M 0x01ffe000 207#define PM_32M 0x03ffe000 208#define PM_64M 0x07ffe000 209#define PM_256M 0x1fffe000 210#define PM_1G 0x7fffe000 211 212#endif 213 214/* 215 * Default page size for a given kernel configuration 216 */ 217#ifdef CONFIG_PAGE_SIZE_4KB 218#define PM_DEFAULT_MASK PM_4K 219#elif defined(CONFIG_PAGE_SIZE_8KB) 220#define PM_DEFAULT_MASK PM_8K 221#elif defined(CONFIG_PAGE_SIZE_16KB) 222#define PM_DEFAULT_MASK PM_16K 223#elif defined(CONFIG_PAGE_SIZE_32KB) 224#define PM_DEFAULT_MASK PM_32K 225#elif defined(CONFIG_PAGE_SIZE_64KB) 226#define PM_DEFAULT_MASK PM_64K 227#else 228#error Bad page size configuration! 229#endif 230 231/* 232 * Default huge tlb size for a given kernel configuration 233 */ 234#ifdef CONFIG_PAGE_SIZE_4KB 235#define PM_HUGE_MASK PM_1M 236#elif defined(CONFIG_PAGE_SIZE_8KB) 237#define PM_HUGE_MASK PM_4M 238#elif defined(CONFIG_PAGE_SIZE_16KB) 239#define PM_HUGE_MASK PM_16M 240#elif defined(CONFIG_PAGE_SIZE_32KB) 241#define PM_HUGE_MASK PM_64M 242#elif defined(CONFIG_PAGE_SIZE_64KB) 243#define PM_HUGE_MASK PM_256M 244#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 245#error Bad page size configuration for hugetlbfs! 246#endif 247 248/* 249 * Values used for computation of new tlb entries 250 */ 251#define PL_4K 12 252#define PL_16K 14 253#define PL_64K 16 254#define PL_256K 18 255#define PL_1M 20 256#define PL_4M 22 257#define PL_16M 24 258#define PL_64M 26 259#define PL_256M 28 260 261/* 262 * PageGrain bits 263 */ 264#define PG_RIE (_ULCAST_(1) << 31) 265#define PG_XIE (_ULCAST_(1) << 30) 266#define PG_ELPA (_ULCAST_(1) << 29) 267#define PG_ESP (_ULCAST_(1) << 28) 268#define PG_IEC (_ULCAST_(1) << 27) 269 270/* 271 * R4x00 interrupt enable / cause bits 272 */ 273#define IE_SW0 (_ULCAST_(1) << 8) 274#define IE_SW1 (_ULCAST_(1) << 9) 275#define IE_IRQ0 (_ULCAST_(1) << 10) 276#define IE_IRQ1 (_ULCAST_(1) << 11) 277#define IE_IRQ2 (_ULCAST_(1) << 12) 278#define IE_IRQ3 (_ULCAST_(1) << 13) 279#define IE_IRQ4 (_ULCAST_(1) << 14) 280#define IE_IRQ5 (_ULCAST_(1) << 15) 281 282/* 283 * R4x00 interrupt cause bits 284 */ 285#define C_SW0 (_ULCAST_(1) << 8) 286#define C_SW1 (_ULCAST_(1) << 9) 287#define C_IRQ0 (_ULCAST_(1) << 10) 288#define C_IRQ1 (_ULCAST_(1) << 11) 289#define C_IRQ2 (_ULCAST_(1) << 12) 290#define C_IRQ3 (_ULCAST_(1) << 13) 291#define C_IRQ4 (_ULCAST_(1) << 14) 292#define C_IRQ5 (_ULCAST_(1) << 15) 293 294/* 295 * Bitfields in the R4xx0 cp0 status register 296 */ 297#define ST0_IE 0x00000001 298#define ST0_EXL 0x00000002 299#define ST0_ERL 0x00000004 300#define ST0_KSU 0x00000018 301# define KSU_USER 0x00000010 302# define KSU_SUPERVISOR 0x00000008 303# define KSU_KERNEL 0x00000000 304#define ST0_UX 0x00000020 305#define ST0_SX 0x00000040 306#define ST0_KX 0x00000080 307#define ST0_DE 0x00010000 308#define ST0_CE 0x00020000 309 310/* 311 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 312 * cacheops in userspace. This bit exists only on RM7000 and RM9000 313 * processors. 314 */ 315#define ST0_CO 0x08000000 316 317/* 318 * Bitfields in the R[23]000 cp0 status register. 319 */ 320#define ST0_IEC 0x00000001 321#define ST0_KUC 0x00000002 322#define ST0_IEP 0x00000004 323#define ST0_KUP 0x00000008 324#define ST0_IEO 0x00000010 325#define ST0_KUO 0x00000020 326/* bits 6 & 7 are reserved on R[23]000 */ 327#define ST0_ISC 0x00010000 328#define ST0_SWC 0x00020000 329#define ST0_CM 0x00080000 330 331/* 332 * Bits specific to the R4640/R4650 333 */ 334#define ST0_UM (_ULCAST_(1) << 4) 335#define ST0_IL (_ULCAST_(1) << 23) 336#define ST0_DL (_ULCAST_(1) << 24) 337 338/* 339 * Enable the MIPS MDMX and DSP ASEs 340 */ 341#define ST0_MX 0x01000000 342 343/* 344 * Bitfields in the TX39 family CP0 Configuration Register 3 345 */ 346#define TX39_CONF_ICS_SHIFT 19 347#define TX39_CONF_ICS_MASK 0x00380000 348#define TX39_CONF_ICS_1KB 0x00000000 349#define TX39_CONF_ICS_2KB 0x00080000 350#define TX39_CONF_ICS_4KB 0x00100000 351#define TX39_CONF_ICS_8KB 0x00180000 352#define TX39_CONF_ICS_16KB 0x00200000 353 354#define TX39_CONF_DCS_SHIFT 16 355#define TX39_CONF_DCS_MASK 0x00070000 356#define TX39_CONF_DCS_1KB 0x00000000 357#define TX39_CONF_DCS_2KB 0x00010000 358#define TX39_CONF_DCS_4KB 0x00020000 359#define TX39_CONF_DCS_8KB 0x00030000 360#define TX39_CONF_DCS_16KB 0x00040000 361 362#define TX39_CONF_CWFON 0x00004000 363#define TX39_CONF_WBON 0x00002000 364#define TX39_CONF_RF_SHIFT 10 365#define TX39_CONF_RF_MASK 0x00000c00 366#define TX39_CONF_DOZE 0x00000200 367#define TX39_CONF_HALT 0x00000100 368#define TX39_CONF_LOCK 0x00000080 369#define TX39_CONF_ICE 0x00000020 370#define TX39_CONF_DCE 0x00000010 371#define TX39_CONF_IRSIZE_SHIFT 2 372#define TX39_CONF_IRSIZE_MASK 0x0000000c 373#define TX39_CONF_DRSIZE_SHIFT 0 374#define TX39_CONF_DRSIZE_MASK 0x00000003 375 376/* 377 * Status register bits available in all MIPS CPUs. 378 */ 379#define ST0_IM 0x0000ff00 380#define STATUSB_IP0 8 381#define STATUSF_IP0 (_ULCAST_(1) << 8) 382#define STATUSB_IP1 9 383#define STATUSF_IP1 (_ULCAST_(1) << 9) 384#define STATUSB_IP2 10 385#define STATUSF_IP2 (_ULCAST_(1) << 10) 386#define STATUSB_IP3 11 387#define STATUSF_IP3 (_ULCAST_(1) << 11) 388#define STATUSB_IP4 12 389#define STATUSF_IP4 (_ULCAST_(1) << 12) 390#define STATUSB_IP5 13 391#define STATUSF_IP5 (_ULCAST_(1) << 13) 392#define STATUSB_IP6 14 393#define STATUSF_IP6 (_ULCAST_(1) << 14) 394#define STATUSB_IP7 15 395#define STATUSF_IP7 (_ULCAST_(1) << 15) 396#define STATUSB_IP8 0 397#define STATUSF_IP8 (_ULCAST_(1) << 0) 398#define STATUSB_IP9 1 399#define STATUSF_IP9 (_ULCAST_(1) << 1) 400#define STATUSB_IP10 2 401#define STATUSF_IP10 (_ULCAST_(1) << 2) 402#define STATUSB_IP11 3 403#define STATUSF_IP11 (_ULCAST_(1) << 3) 404#define STATUSB_IP12 4 405#define STATUSF_IP12 (_ULCAST_(1) << 4) 406#define STATUSB_IP13 5 407#define STATUSF_IP13 (_ULCAST_(1) << 5) 408#define STATUSB_IP14 6 409#define STATUSF_IP14 (_ULCAST_(1) << 6) 410#define STATUSB_IP15 7 411#define STATUSF_IP15 (_ULCAST_(1) << 7) 412#define ST0_CH 0x00040000 413#define ST0_NMI 0x00080000 414#define ST0_SR 0x00100000 415#define ST0_TS 0x00200000 416#define ST0_BEV 0x00400000 417#define ST0_RE 0x02000000 418#define ST0_FR 0x04000000 419#define ST0_CU 0xf0000000 420#define ST0_CU0 0x10000000 421#define ST0_CU1 0x20000000 422#define ST0_CU2 0x40000000 423#define ST0_CU3 0x80000000 424#define ST0_XX 0x80000000 /* MIPS IV naming */ 425 426/* 427 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 428 * 429 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 430 */ 431#define INTCTLB_IPPCI 26 432#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 433#define INTCTLB_IPTI 29 434#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 435 436/* 437 * Bitfields and bit numbers in the coprocessor 0 cause register. 438 * 439 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 440 */ 441#define CAUSEB_EXCCODE 2 442#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 443#define CAUSEB_IP 8 444#define CAUSEF_IP (_ULCAST_(255) << 8) 445#define CAUSEB_IP0 8 446#define CAUSEF_IP0 (_ULCAST_(1) << 8) 447#define CAUSEB_IP1 9 448#define CAUSEF_IP1 (_ULCAST_(1) << 9) 449#define CAUSEB_IP2 10 450#define CAUSEF_IP2 (_ULCAST_(1) << 10) 451#define CAUSEB_IP3 11 452#define CAUSEF_IP3 (_ULCAST_(1) << 11) 453#define CAUSEB_IP4 12 454#define CAUSEF_IP4 (_ULCAST_(1) << 12) 455#define CAUSEB_IP5 13 456#define CAUSEF_IP5 (_ULCAST_(1) << 13) 457#define CAUSEB_IP6 14 458#define CAUSEF_IP6 (_ULCAST_(1) << 14) 459#define CAUSEB_IP7 15 460#define CAUSEF_IP7 (_ULCAST_(1) << 15) 461#define CAUSEB_IV 23 462#define CAUSEF_IV (_ULCAST_(1) << 23) 463#define CAUSEB_PCI 26 464#define CAUSEF_PCI (_ULCAST_(1) << 26) 465#define CAUSEB_CE 28 466#define CAUSEF_CE (_ULCAST_(3) << 28) 467#define CAUSEB_TI 30 468#define CAUSEF_TI (_ULCAST_(1) << 30) 469#define CAUSEB_BD 31 470#define CAUSEF_BD (_ULCAST_(1) << 31) 471 472/* 473 * Bits in the coprocessor 0 config register. 474 */ 475/* Generic bits. */ 476#define CONF_CM_CACHABLE_NO_WA 0 477#define CONF_CM_CACHABLE_WA 1 478#define CONF_CM_UNCACHED 2 479#define CONF_CM_CACHABLE_NONCOHERENT 3 480#define CONF_CM_CACHABLE_CE 4 481#define CONF_CM_CACHABLE_COW 5 482#define CONF_CM_CACHABLE_CUW 6 483#define CONF_CM_CACHABLE_ACCELERATED 7 484#define CONF_CM_CMASK 7 485#define CONF_BE (_ULCAST_(1) << 15) 486 487/* Bits common to various processors. */ 488#define CONF_CU (_ULCAST_(1) << 3) 489#define CONF_DB (_ULCAST_(1) << 4) 490#define CONF_IB (_ULCAST_(1) << 5) 491#define CONF_DC (_ULCAST_(7) << 6) 492#define CONF_IC (_ULCAST_(7) << 9) 493#define CONF_EB (_ULCAST_(1) << 13) 494#define CONF_EM (_ULCAST_(1) << 14) 495#define CONF_SM (_ULCAST_(1) << 16) 496#define CONF_SC (_ULCAST_(1) << 17) 497#define CONF_EW (_ULCAST_(3) << 18) 498#define CONF_EP (_ULCAST_(15)<< 24) 499#define CONF_EC (_ULCAST_(7) << 28) 500#define CONF_CM (_ULCAST_(1) << 31) 501 502/* Bits specific to the R4xx0. */ 503#define R4K_CONF_SW (_ULCAST_(1) << 20) 504#define R4K_CONF_SS (_ULCAST_(1) << 21) 505#define R4K_CONF_SB (_ULCAST_(3) << 22) 506 507/* Bits specific to the R5000. */ 508#define R5K_CONF_SE (_ULCAST_(1) << 12) 509#define R5K_CONF_SS (_ULCAST_(3) << 20) 510 511/* Bits specific to the RM7000. */ 512#define RM7K_CONF_SE (_ULCAST_(1) << 3) 513#define RM7K_CONF_TE (_ULCAST_(1) << 12) 514#define RM7K_CONF_CLK (_ULCAST_(1) << 16) 515#define RM7K_CONF_TC (_ULCAST_(1) << 17) 516#define RM7K_CONF_SI (_ULCAST_(3) << 20) 517#define RM7K_CONF_SC (_ULCAST_(1) << 31) 518 519/* Bits specific to the R10000. */ 520#define R10K_CONF_DN (_ULCAST_(3) << 3) 521#define R10K_CONF_CT (_ULCAST_(1) << 5) 522#define R10K_CONF_PE (_ULCAST_(1) << 6) 523#define R10K_CONF_PM (_ULCAST_(3) << 7) 524#define R10K_CONF_EC (_ULCAST_(15)<< 9) 525#define R10K_CONF_SB (_ULCAST_(1) << 13) 526#define R10K_CONF_SK (_ULCAST_(1) << 14) 527#define R10K_CONF_SS (_ULCAST_(7) << 16) 528#define R10K_CONF_SC (_ULCAST_(7) << 19) 529#define R10K_CONF_DC (_ULCAST_(7) << 26) 530#define R10K_CONF_IC (_ULCAST_(7) << 29) 531 532/* Bits specific to the VR41xx. */ 533#define VR41_CONF_CS (_ULCAST_(1) << 12) 534#define VR41_CONF_P4K (_ULCAST_(1) << 13) 535#define VR41_CONF_BP (_ULCAST_(1) << 16) 536#define VR41_CONF_M16 (_ULCAST_(1) << 20) 537#define VR41_CONF_AD (_ULCAST_(1) << 23) 538 539/* Bits specific to the R30xx. */ 540#define R30XX_CONF_FDM (_ULCAST_(1) << 19) 541#define R30XX_CONF_REV (_ULCAST_(1) << 22) 542#define R30XX_CONF_AC (_ULCAST_(1) << 23) 543#define R30XX_CONF_RF (_ULCAST_(1) << 24) 544#define R30XX_CONF_HALT (_ULCAST_(1) << 25) 545#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 546#define R30XX_CONF_DBR (_ULCAST_(1) << 29) 547#define R30XX_CONF_SB (_ULCAST_(1) << 30) 548#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 549 550/* Bits specific to the TX49. */ 551#define TX49_CONF_DC (_ULCAST_(1) << 16) 552#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 553#define TX49_CONF_HALT (_ULCAST_(1) << 18) 554#define TX49_CONF_CWFON (_ULCAST_(1) << 27) 555 556/* Bits specific to the MIPS32/64 PRA. */ 557#define MIPS_CONF_MT (_ULCAST_(7) << 7) 558#define MIPS_CONF_AR (_ULCAST_(7) << 10) 559#define MIPS_CONF_AT (_ULCAST_(3) << 13) 560#define MIPS_CONF_M (_ULCAST_(1) << 31) 561 562/* 563 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 564 */ 565#define MIPS_CONF1_FP (_ULCAST_(1) << 0) 566#define MIPS_CONF1_EP (_ULCAST_(1) << 1) 567#define MIPS_CONF1_CA (_ULCAST_(1) << 2) 568#define MIPS_CONF1_WR (_ULCAST_(1) << 3) 569#define MIPS_CONF1_PC (_ULCAST_(1) << 4) 570#define MIPS_CONF1_MD (_ULCAST_(1) << 5) 571#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 572#define MIPS_CONF1_DA_SHF 7 573#define MIPS_CONF1_DA_SZ 3 574#define MIPS_CONF1_DA (_ULCAST_(7) << 7) 575#define MIPS_CONF1_DL_SHF 10 576#define MIPS_CONF1_DL_SZ 3 577#define MIPS_CONF1_DL (_ULCAST_(7) << 10) 578#define MIPS_CONF1_DS_SHF 13 579#define MIPS_CONF1_DS_SZ 3 580#define MIPS_CONF1_DS (_ULCAST_(7) << 13) 581#define MIPS_CONF1_IA_SHF 16 582#define MIPS_CONF1_IA_SZ 3 583#define MIPS_CONF1_IA (_ULCAST_(7) << 16) 584#define MIPS_CONF1_IL_SHF 19 585#define MIPS_CONF1_IL_SZ 3 586#define MIPS_CONF1_IL (_ULCAST_(7) << 19) 587#define MIPS_CONF1_IS_SHF 22 588#define MIPS_CONF1_IS_SZ 3 589#define MIPS_CONF1_IS (_ULCAST_(7) << 22) 590#define MIPS_CONF1_TLBS_SHIFT (25) 591#define MIPS_CONF1_TLBS_SIZE (6) 592#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) 593 594#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 595#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 596#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 597#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 598#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 599#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 600#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 601#define MIPS_CONF2_TU (_ULCAST_(7) << 28) 602 603#define MIPS_CONF3_TL (_ULCAST_(1) << 0) 604#define MIPS_CONF3_SM (_ULCAST_(1) << 1) 605#define MIPS_CONF3_MT (_ULCAST_(1) << 2) 606#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) 607#define MIPS_CONF3_SP (_ULCAST_(1) << 4) 608#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 609#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 610#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 611#define MIPS_CONF3_ITL (_ULCAST_(1) << 8) 612#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) 613#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 614#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 615#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 616#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 617#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 618#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 619#define MIPS_CONF3_MCU (_ULCAST_(1) << 17) 620#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) 621#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) 622#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 623#define MIPS_CONF3_PW (_ULCAST_(1) << 24) 624#define MIPS_CONF3_SC (_ULCAST_(1) << 25) 625#define MIPS_CONF3_BI (_ULCAST_(1) << 26) 626#define MIPS_CONF3_BP (_ULCAST_(1) << 27) 627#define MIPS_CONF3_MSA (_ULCAST_(1) << 28) 628#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) 629#define MIPS_CONF3_BPG (_ULCAST_(1) << 30) 630 631#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) 632#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 633#define MIPS_CONF4_FTLBSETS_SHIFT (0) 634#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) 635#define MIPS_CONF4_FTLBWAYS_SHIFT (4) 636#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) 637#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) 638/* bits 10:8 in FTLB-only configurations */ 639#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 640/* bits 12:8 in VTLB-FTLB only configurations */ 641#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 642#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 643#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 644#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) 645#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) 646#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) 647#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) 648#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) 649#define MIPS_CONF4_AE (_ULCAST_(1) << 28) 650#define MIPS_CONF4_IE (_ULCAST_(3) << 29) 651#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) 652 653#define MIPS_CONF5_NF (_ULCAST_(1) << 0) 654#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 655#define MIPS_CONF5_MRP (_ULCAST_(1) << 3) 656#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 657#define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 658#define MIPS_CONF5_CV (_ULCAST_(1) << 29) 659#define MIPS_CONF5_K (_ULCAST_(1) << 30) 660 661#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 662/* proAptiv FTLB on/off bit */ 663#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) 664/* FTLB probability bits */ 665#define MIPS_CONF6_FTLBP_SHIFT (16) 666 667#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 668 669#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 670 671#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) 672#define MIPS_CONF7_AR (_ULCAST_(1) << 16) 673 674/* MAAR bit definitions */ 675#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) 676#define MIPS_MAAR_ADDR_SHIFT 12 677#define MIPS_MAAR_S (_ULCAST_(1) << 1) 678#define MIPS_MAAR_V (_ULCAST_(1) << 0) 679 680/* EntryHI bit definition */ 681#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) 682 683/* CMGCRBase bit definitions */ 684#define MIPS_CMGCRB_BASE 11 685#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) 686 687/* 688 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 689 */ 690#define MIPS_FPIR_S (_ULCAST_(1) << 16) 691#define MIPS_FPIR_D (_ULCAST_(1) << 17) 692#define MIPS_FPIR_PS (_ULCAST_(1) << 18) 693#define MIPS_FPIR_3D (_ULCAST_(1) << 19) 694#define MIPS_FPIR_W (_ULCAST_(1) << 20) 695#define MIPS_FPIR_L (_ULCAST_(1) << 21) 696#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 697 698/* 699 * Bits in the MIPS32 Memory Segmentation registers. 700 */ 701#define MIPS_SEGCFG_PA_SHIFT 9 702#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) 703#define MIPS_SEGCFG_AM_SHIFT 4 704#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) 705#define MIPS_SEGCFG_EU_SHIFT 3 706#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) 707#define MIPS_SEGCFG_C_SHIFT 0 708#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) 709 710#define MIPS_SEGCFG_UUSK _ULCAST_(7) 711#define MIPS_SEGCFG_USK _ULCAST_(5) 712#define MIPS_SEGCFG_MUSUK _ULCAST_(4) 713#define MIPS_SEGCFG_MUSK _ULCAST_(3) 714#define MIPS_SEGCFG_MSK _ULCAST_(2) 715#define MIPS_SEGCFG_MK _ULCAST_(1) 716#define MIPS_SEGCFG_UK _ULCAST_(0) 717 718#define MIPS_PWFIELD_GDI_SHIFT 24 719#define MIPS_PWFIELD_GDI_MASK 0x3f000000 720#define MIPS_PWFIELD_UDI_SHIFT 18 721#define MIPS_PWFIELD_UDI_MASK 0x00fc0000 722#define MIPS_PWFIELD_MDI_SHIFT 12 723#define MIPS_PWFIELD_MDI_MASK 0x0003f000 724#define MIPS_PWFIELD_PTI_SHIFT 6 725#define MIPS_PWFIELD_PTI_MASK 0x00000fc0 726#define MIPS_PWFIELD_PTEI_SHIFT 0 727#define MIPS_PWFIELD_PTEI_MASK 0x0000003f 728 729#define MIPS_PWSIZE_GDW_SHIFT 24 730#define MIPS_PWSIZE_GDW_MASK 0x3f000000 731#define MIPS_PWSIZE_UDW_SHIFT 18 732#define MIPS_PWSIZE_UDW_MASK 0x00fc0000 733#define MIPS_PWSIZE_MDW_SHIFT 12 734#define MIPS_PWSIZE_MDW_MASK 0x0003f000 735#define MIPS_PWSIZE_PTW_SHIFT 6 736#define MIPS_PWSIZE_PTW_MASK 0x00000fc0 737#define MIPS_PWSIZE_PTEW_SHIFT 0 738#define MIPS_PWSIZE_PTEW_MASK 0x0000003f 739 740#define MIPS_PWCTL_PWEN_SHIFT 31 741#define MIPS_PWCTL_PWEN_MASK 0x80000000 742#define MIPS_PWCTL_DPH_SHIFT 7 743#define MIPS_PWCTL_DPH_MASK 0x00000080 744#define MIPS_PWCTL_HUGEPG_SHIFT 6 745#define MIPS_PWCTL_HUGEPG_MASK 0x00000060 746#define MIPS_PWCTL_PSN_SHIFT 0 747#define MIPS_PWCTL_PSN_MASK 0x0000003f 748 749#ifndef __ASSEMBLY__ 750 751/* 752 * Macros for handling the ISA mode bit for MIPS16 and microMIPS. 753 */ 754#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ 755 defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 756#define get_isa16_mode(x) ((x) & 0x1) 757#define msk_isa16_mode(x) ((x) & ~0x1) 758#define set_isa16_mode(x) do { (x) |= 0x1; } while(0) 759#else 760#define get_isa16_mode(x) 0 761#define msk_isa16_mode(x) (x) 762#define set_isa16_mode(x) do { } while(0) 763#endif 764 765/* 766 * microMIPS instructions can be 16-bit or 32-bit in length. This 767 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. 768 */ 769static inline int mm_insn_16bit(u16 insn) 770{ 771 u16 opcode = (insn >> 10) & 0x7; 772 773 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 774} 775 776/* 777 * TLB Invalidate Flush 778 */ 779static inline void tlbinvf(void) 780{ 781 __asm__ __volatile__( 782 ".set push\n\t" 783 ".set noreorder\n\t" 784 ".word 0x42000004\n\t" /* tlbinvf */ 785 ".set pop"); 786} 787 788 789/* 790 * Functions to access the R10000 performance counters. These are basically 791 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 792 * performance counter number encoded into bits 1 ... 5 of the instruction. 793 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 794 * disassembler these will look like an access to sel 0 or 1. 795 */ 796#define read_r10k_perf_cntr(counter) \ 797({ \ 798 unsigned int __res; \ 799 __asm__ __volatile__( \ 800 "mfpc\t%0, %1" \ 801 : "=r" (__res) \ 802 : "i" (counter)); \ 803 \ 804 __res; \ 805}) 806 807#define write_r10k_perf_cntr(counter,val) \ 808do { \ 809 __asm__ __volatile__( \ 810 "mtpc\t%0, %1" \ 811 : \ 812 : "r" (val), "i" (counter)); \ 813} while (0) 814 815#define read_r10k_perf_event(counter) \ 816({ \ 817 unsigned int __res; \ 818 __asm__ __volatile__( \ 819 "mfps\t%0, %1" \ 820 : "=r" (__res) \ 821 : "i" (counter)); \ 822 \ 823 __res; \ 824}) 825 826#define write_r10k_perf_cntl(counter,val) \ 827do { \ 828 __asm__ __volatile__( \ 829 "mtps\t%0, %1" \ 830 : \ 831 : "r" (val), "i" (counter)); \ 832} while (0) 833 834 835/* 836 * Macros to access the system control coprocessor 837 */ 838 839#define __read_32bit_c0_register(source, sel) \ 840({ int __res; \ 841 if (sel == 0) \ 842 __asm__ __volatile__( \ 843 "mfc0\t%0, " #source "\n\t" \ 844 : "=r" (__res)); \ 845 else \ 846 __asm__ __volatile__( \ 847 ".set\tmips32\n\t" \ 848 "mfc0\t%0, " #source ", " #sel "\n\t" \ 849 ".set\tmips0\n\t" \ 850 : "=r" (__res)); \ 851 __res; \ 852}) 853 854#define __read_64bit_c0_register(source, sel) \ 855({ unsigned long long __res; \ 856 if (sizeof(unsigned long) == 4) \ 857 __res = __read_64bit_c0_split(source, sel); \ 858 else if (sel == 0) \ 859 __asm__ __volatile__( \ 860 ".set\tmips3\n\t" \ 861 "dmfc0\t%0, " #source "\n\t" \ 862 ".set\tmips0" \ 863 : "=r" (__res)); \ 864 else \ 865 __asm__ __volatile__( \ 866 ".set\tmips64\n\t" \ 867 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 868 ".set\tmips0" \ 869 : "=r" (__res)); \ 870 __res; \ 871}) 872 873#define __write_32bit_c0_register(register, sel, value) \ 874do { \ 875 if (sel == 0) \ 876 __asm__ __volatile__( \ 877 "mtc0\t%z0, " #register "\n\t" \ 878 : : "Jr" ((unsigned int)(value))); \ 879 else \ 880 __asm__ __volatile__( \ 881 ".set\tmips32\n\t" \ 882 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 883 ".set\tmips0" \ 884 : : "Jr" ((unsigned int)(value))); \ 885} while (0) 886 887#define __write_64bit_c0_register(register, sel, value) \ 888do { \ 889 if (sizeof(unsigned long) == 4) \ 890 __write_64bit_c0_split(register, sel, value); \ 891 else if (sel == 0) \ 892 __asm__ __volatile__( \ 893 ".set\tmips3\n\t" \ 894 "dmtc0\t%z0, " #register "\n\t" \ 895 ".set\tmips0" \ 896 : : "Jr" (value)); \ 897 else \ 898 __asm__ __volatile__( \ 899 ".set\tmips64\n\t" \ 900 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 901 ".set\tmips0" \ 902 : : "Jr" (value)); \ 903} while (0) 904 905#define __read_ulong_c0_register(reg, sel) \ 906 ((sizeof(unsigned long) == 4) ? \ 907 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 908 (unsigned long) __read_64bit_c0_register(reg, sel)) 909 910#define __write_ulong_c0_register(reg, sel, val) \ 911do { \ 912 if (sizeof(unsigned long) == 4) \ 913 __write_32bit_c0_register(reg, sel, val); \ 914 else \ 915 __write_64bit_c0_register(reg, sel, val); \ 916} while (0) 917 918/* 919 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 920 */ 921#define __read_32bit_c0_ctrl_register(source) \ 922({ int __res; \ 923 __asm__ __volatile__( \ 924 "cfc0\t%0, " #source "\n\t" \ 925 : "=r" (__res)); \ 926 __res; \ 927}) 928 929#define __write_32bit_c0_ctrl_register(register, value) \ 930do { \ 931 __asm__ __volatile__( \ 932 "ctc0\t%z0, " #register "\n\t" \ 933 : : "Jr" ((unsigned int)(value))); \ 934} while (0) 935 936/* 937 * These versions are only needed for systems with more than 38 bits of 938 * physical address space running the 32-bit kernel. That's none atm :-) 939 */ 940#define __read_64bit_c0_split(source, sel) \ 941({ \ 942 unsigned long long __val; \ 943 unsigned long __flags; \ 944 \ 945 local_irq_save(__flags); \ 946 if (sel == 0) \ 947 __asm__ __volatile__( \ 948 ".set\tmips64\n\t" \ 949 "dmfc0\t%M0, " #source "\n\t" \ 950 "dsll\t%L0, %M0, 32\n\t" \ 951 "dsra\t%M0, %M0, 32\n\t" \ 952 "dsra\t%L0, %L0, 32\n\t" \ 953 ".set\tmips0" \ 954 : "=r" (__val)); \ 955 else \ 956 __asm__ __volatile__( \ 957 ".set\tmips64\n\t" \ 958 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 959 "dsll\t%L0, %M0, 32\n\t" \ 960 "dsra\t%M0, %M0, 32\n\t" \ 961 "dsra\t%L0, %L0, 32\n\t" \ 962 ".set\tmips0" \ 963 : "=r" (__val)); \ 964 local_irq_restore(__flags); \ 965 \ 966 __val; \ 967}) 968 969#define __write_64bit_c0_split(source, sel, val) \ 970do { \ 971 unsigned long __flags; \ 972 \ 973 local_irq_save(__flags); \ 974 if (sel == 0) \ 975 __asm__ __volatile__( \ 976 ".set\tmips64\n\t" \ 977 "dsll\t%L0, %L0, 32\n\t" \ 978 "dsrl\t%L0, %L0, 32\n\t" \ 979 "dsll\t%M0, %M0, 32\n\t" \ 980 "or\t%L0, %L0, %M0\n\t" \ 981 "dmtc0\t%L0, " #source "\n\t" \ 982 ".set\tmips0" \ 983 : : "r" (val)); \ 984 else \ 985 __asm__ __volatile__( \ 986 ".set\tmips64\n\t" \ 987 "dsll\t%L0, %L0, 32\n\t" \ 988 "dsrl\t%L0, %L0, 32\n\t" \ 989 "dsll\t%M0, %M0, 32\n\t" \ 990 "or\t%L0, %L0, %M0\n\t" \ 991 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 992 ".set\tmips0" \ 993 : : "r" (val)); \ 994 local_irq_restore(__flags); \ 995} while (0) 996 997#define read_c0_index() __read_32bit_c0_register($0, 0) 998#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 999 1000#define read_c0_random() __read_32bit_c0_register($1, 0) 1001#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 1002 1003#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 1004#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 1005 1006#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 1007#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 1008 1009#define read_c0_conf() __read_32bit_c0_register($3, 0) 1010#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 1011 1012#define read_c0_context() __read_ulong_c0_register($4, 0) 1013#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 1014 1015#define read_c0_userlocal() __read_ulong_c0_register($4, 2) 1016#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 1017 1018#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 1019#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 1020 1021#define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 1022#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 1023 1024#define read_c0_wired() __read_32bit_c0_register($6, 0) 1025#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 1026 1027#define read_c0_info() __read_32bit_c0_register($7, 0) 1028 1029#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 1030#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 1031 1032#define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 1033#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 1034 1035#define read_c0_count() __read_32bit_c0_register($9, 0) 1036#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 1037 1038#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 1039#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 1040 1041#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 1042#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 1043 1044#define read_c0_entryhi() __read_ulong_c0_register($10, 0) 1045#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 1046 1047#define read_c0_compare() __read_32bit_c0_register($11, 0) 1048#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 1049 1050#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 1051#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 1052 1053#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 1054#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 1055 1056#define read_c0_status() __read_32bit_c0_register($12, 0) 1057 1058#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 1059 1060#define read_c0_cause() __read_32bit_c0_register($13, 0) 1061#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 1062 1063#define read_c0_epc() __read_ulong_c0_register($14, 0) 1064#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 1065 1066#define read_c0_prid() __read_32bit_c0_register($15, 0) 1067 1068#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) 1069 1070#define read_c0_config() __read_32bit_c0_register($16, 0) 1071#define read_c0_config1() __read_32bit_c0_register($16, 1) 1072#define read_c0_config2() __read_32bit_c0_register($16, 2) 1073#define read_c0_config3() __read_32bit_c0_register($16, 3) 1074#define read_c0_config4() __read_32bit_c0_register($16, 4) 1075#define read_c0_config5() __read_32bit_c0_register($16, 5) 1076#define read_c0_config6() __read_32bit_c0_register($16, 6) 1077#define read_c0_config7() __read_32bit_c0_register($16, 7) 1078#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 1079#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 1080#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 1081#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 1082#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 1083#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 1084#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 1085#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 1086 1087#define read_c0_maar() __read_ulong_c0_register($17, 1) 1088#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) 1089#define read_c0_maari() __read_32bit_c0_register($17, 2) 1090#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) 1091 1092/* 1093 * The WatchLo register. There may be up to 8 of them. 1094 */ 1095#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 1096#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 1097#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 1098#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 1099#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 1100#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 1101#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 1102#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 1103#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 1104#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 1105#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 1106#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 1107#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 1108#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 1109#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 1110#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 1111 1112/* 1113 * The WatchHi register. There may be up to 8 of them. 1114 */ 1115#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 1116#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 1117#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 1118#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 1119#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 1120#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 1121#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 1122#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 1123 1124#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 1125#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 1126#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 1127#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 1128#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 1129#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 1130#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 1131#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 1132 1133#define read_c0_xcontext() __read_ulong_c0_register($20, 0) 1134#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 1135 1136#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 1137#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 1138 1139#define read_c0_framemask() __read_32bit_c0_register($21, 0) 1140#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 1141 1142#define read_c0_diag() __read_32bit_c0_register($22, 0) 1143#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 1144 1145#define read_c0_diag1() __read_32bit_c0_register($22, 1) 1146#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 1147 1148#define read_c0_diag2() __read_32bit_c0_register($22, 2) 1149#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 1150 1151#define read_c0_diag3() __read_32bit_c0_register($22, 3) 1152#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 1153 1154#define read_c0_diag4() __read_32bit_c0_register($22, 4) 1155#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 1156 1157#define read_c0_diag5() __read_32bit_c0_register($22, 5) 1158#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 1159 1160#define read_c0_debug() __read_32bit_c0_register($23, 0) 1161#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1162 1163#define read_c0_depc() __read_ulong_c0_register($24, 0) 1164#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1165 1166/* 1167 * MIPS32 / MIPS64 performance counters 1168 */ 1169#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1170#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1171#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1172#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1173#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1174#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1175#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1176#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1177#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1178#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1179#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1180#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1181#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1182#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1183#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1184#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1185#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1186#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1187#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1188#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1189#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1190#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1191#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1192#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1193 1194#define read_c0_ecc() __read_32bit_c0_register($26, 0) 1195#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1196 1197#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1198#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1199 1200#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1201 1202#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1203#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1204 1205#define read_c0_taglo() __read_32bit_c0_register($28, 0) 1206#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1207 1208#define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1209#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1210 1211#define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1212#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1213 1214#define read_c0_staglo() __read_32bit_c0_register($28, 4) 1215#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1216 1217#define read_c0_taghi() __read_32bit_c0_register($29, 0) 1218#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1219 1220#define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1221#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1222 1223/* MIPSR2 */ 1224#define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1225#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1226 1227#define read_c0_intctl() __read_32bit_c0_register($12, 1) 1228#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1229 1230#define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1231#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1232 1233#define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1234#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1235 1236#define read_c0_ebase() __read_32bit_c0_register($15, 1) 1237#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1238 1239/* MIPSR3 */ 1240#define read_c0_segctl0() __read_32bit_c0_register($5, 2) 1241#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) 1242 1243#define read_c0_segctl1() __read_32bit_c0_register($5, 3) 1244#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) 1245 1246#define read_c0_segctl2() __read_32bit_c0_register($5, 4) 1247#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) 1248 1249/* Hardware Page Table Walker */ 1250#define read_c0_pwbase() __read_ulong_c0_register($5, 5) 1251#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) 1252 1253#define read_c0_pwfield() __read_ulong_c0_register($5, 6) 1254#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) 1255 1256#define read_c0_pwsize() __read_ulong_c0_register($5, 7) 1257#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) 1258 1259#define read_c0_pwctl() __read_32bit_c0_register($6, 6) 1260#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) 1261 1262/* Cavium OCTEON (cnMIPS) */ 1263#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1264#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1265 1266#define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1267#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1268 1269#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1270#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1271/* 1272 * The cacheerr registers are not standardized. On OCTEON, they are 1273 * 64 bits wide. 1274 */ 1275#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1276#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1277 1278#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1279#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1280 1281/* BMIPS3300 */ 1282#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1283#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1284 1285#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1286#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1287 1288#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1289#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1290 1291/* BMIPS43xx */ 1292#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1293#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1294 1295#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1296#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1297 1298#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1299#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1300 1301#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1302#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1303 1304#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1305#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1306 1307/* BMIPS5000 */ 1308#define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1309#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1310 1311#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1312#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1313 1314#define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1315#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1316 1317#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1318#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1319 1320#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1321#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1322 1323#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1324#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1325 1326/* 1327 * Macros to access the floating point coprocessor control registers 1328 */ 1329#define _read_32bit_cp1_register(source, gas_hardfloat) \ 1330({ \ 1331 int __res; \ 1332 \ 1333 __asm__ __volatile__( \ 1334 " .set push \n" \ 1335 " .set reorder \n" \ 1336 " # gas fails to assemble cfc1 for some archs, \n" \ 1337 " # like Octeon. \n" \ 1338 " .set mips1 \n" \ 1339 " "STR(gas_hardfloat)" \n" \ 1340 " cfc1 %0,"STR(source)" \n" \ 1341 " .set pop \n" \ 1342 : "=r" (__res)); \ 1343 __res; \ 1344}) 1345 1346#ifdef GAS_HAS_SET_HARDFLOAT 1347#define read_32bit_cp1_register(source) \ 1348 _read_32bit_cp1_register(source, .set hardfloat) 1349#else 1350#define read_32bit_cp1_register(source) \ 1351 _read_32bit_cp1_register(source, ) 1352#endif 1353 1354#ifdef HAVE_AS_DSP 1355#define rddsp(mask) \ 1356({ \ 1357 unsigned int __dspctl; \ 1358 \ 1359 __asm__ __volatile__( \ 1360 " .set push \n" \ 1361 " .set dsp \n" \ 1362 " rddsp %0, %x1 \n" \ 1363 " .set pop \n" \ 1364 : "=r" (__dspctl) \ 1365 : "i" (mask)); \ 1366 __dspctl; \ 1367}) 1368 1369#define wrdsp(val, mask) \ 1370do { \ 1371 __asm__ __volatile__( \ 1372 " .set push \n" \ 1373 " .set dsp \n" \ 1374 " wrdsp %0, %x1 \n" \ 1375 " .set pop \n" \ 1376 : \ 1377 : "r" (val), "i" (mask)); \ 1378} while (0) 1379 1380#define mflo0() \ 1381({ \ 1382 long mflo0; \ 1383 __asm__( \ 1384 " .set push \n" \ 1385 " .set dsp \n" \ 1386 " mflo %0, $ac0 \n" \ 1387 " .set pop \n" \ 1388 : "=r" (mflo0)); \ 1389 mflo0; \ 1390}) 1391 1392#define mflo1() \ 1393({ \ 1394 long mflo1; \ 1395 __asm__( \ 1396 " .set push \n" \ 1397 " .set dsp \n" \ 1398 " mflo %0, $ac1 \n" \ 1399 " .set pop \n" \ 1400 : "=r" (mflo1)); \ 1401 mflo1; \ 1402}) 1403 1404#define mflo2() \ 1405({ \ 1406 long mflo2; \ 1407 __asm__( \ 1408 " .set push \n" \ 1409 " .set dsp \n" \ 1410 " mflo %0, $ac2 \n" \ 1411 " .set pop \n" \ 1412 : "=r" (mflo2)); \ 1413 mflo2; \ 1414}) 1415 1416#define mflo3() \ 1417({ \ 1418 long mflo3; \ 1419 __asm__( \ 1420 " .set push \n" \ 1421 " .set dsp \n" \ 1422 " mflo %0, $ac3 \n" \ 1423 " .set pop \n" \ 1424 : "=r" (mflo3)); \ 1425 mflo3; \ 1426}) 1427 1428#define mfhi0() \ 1429({ \ 1430 long mfhi0; \ 1431 __asm__( \ 1432 " .set push \n" \ 1433 " .set dsp \n" \ 1434 " mfhi %0, $ac0 \n" \ 1435 " .set pop \n" \ 1436 : "=r" (mfhi0)); \ 1437 mfhi0; \ 1438}) 1439 1440#define mfhi1() \ 1441({ \ 1442 long mfhi1; \ 1443 __asm__( \ 1444 " .set push \n" \ 1445 " .set dsp \n" \ 1446 " mfhi %0, $ac1 \n" \ 1447 " .set pop \n" \ 1448 : "=r" (mfhi1)); \ 1449 mfhi1; \ 1450}) 1451 1452#define mfhi2() \ 1453({ \ 1454 long mfhi2; \ 1455 __asm__( \ 1456 " .set push \n" \ 1457 " .set dsp \n" \ 1458 " mfhi %0, $ac2 \n" \ 1459 " .set pop \n" \ 1460 : "=r" (mfhi2)); \ 1461 mfhi2; \ 1462}) 1463 1464#define mfhi3() \ 1465({ \ 1466 long mfhi3; \ 1467 __asm__( \ 1468 " .set push \n" \ 1469 " .set dsp \n" \ 1470 " mfhi %0, $ac3 \n" \ 1471 " .set pop \n" \ 1472 : "=r" (mfhi3)); \ 1473 mfhi3; \ 1474}) 1475 1476 1477#define mtlo0(x) \ 1478({ \ 1479 __asm__( \ 1480 " .set push \n" \ 1481 " .set dsp \n" \ 1482 " mtlo %0, $ac0 \n" \ 1483 " .set pop \n" \ 1484 : \ 1485 : "r" (x)); \ 1486}) 1487 1488#define mtlo1(x) \ 1489({ \ 1490 __asm__( \ 1491 " .set push \n" \ 1492 " .set dsp \n" \ 1493 " mtlo %0, $ac1 \n" \ 1494 " .set pop \n" \ 1495 : \ 1496 : "r" (x)); \ 1497}) 1498 1499#define mtlo2(x) \ 1500({ \ 1501 __asm__( \ 1502 " .set push \n" \ 1503 " .set dsp \n" \ 1504 " mtlo %0, $ac2 \n" \ 1505 " .set pop \n" \ 1506 : \ 1507 : "r" (x)); \ 1508}) 1509 1510#define mtlo3(x) \ 1511({ \ 1512 __asm__( \ 1513 " .set push \n" \ 1514 " .set dsp \n" \ 1515 " mtlo %0, $ac3 \n" \ 1516 " .set pop \n" \ 1517 : \ 1518 : "r" (x)); \ 1519}) 1520 1521#define mthi0(x) \ 1522({ \ 1523 __asm__( \ 1524 " .set push \n" \ 1525 " .set dsp \n" \ 1526 " mthi %0, $ac0 \n" \ 1527 " .set pop \n" \ 1528 : \ 1529 : "r" (x)); \ 1530}) 1531 1532#define mthi1(x) \ 1533({ \ 1534 __asm__( \ 1535 " .set push \n" \ 1536 " .set dsp \n" \ 1537 " mthi %0, $ac1 \n" \ 1538 " .set pop \n" \ 1539 : \ 1540 : "r" (x)); \ 1541}) 1542 1543#define mthi2(x) \ 1544({ \ 1545 __asm__( \ 1546 " .set push \n" \ 1547 " .set dsp \n" \ 1548 " mthi %0, $ac2 \n" \ 1549 " .set pop \n" \ 1550 : \ 1551 : "r" (x)); \ 1552}) 1553 1554#define mthi3(x) \ 1555({ \ 1556 __asm__( \ 1557 " .set push \n" \ 1558 " .set dsp \n" \ 1559 " mthi %0, $ac3 \n" \ 1560 " .set pop \n" \ 1561 : \ 1562 : "r" (x)); \ 1563}) 1564 1565#else 1566 1567#ifdef CONFIG_CPU_MICROMIPS 1568#define rddsp(mask) \ 1569({ \ 1570 unsigned int __res; \ 1571 \ 1572 __asm__ __volatile__( \ 1573 " .set push \n" \ 1574 " .set noat \n" \ 1575 " # rddsp $1, %x1 \n" \ 1576 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1577 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1578 " move %0, $1 \n" \ 1579 " .set pop \n" \ 1580 : "=r" (__res) \ 1581 : "i" (mask)); \ 1582 __res; \ 1583}) 1584 1585#define wrdsp(val, mask) \ 1586do { \ 1587 __asm__ __volatile__( \ 1588 " .set push \n" \ 1589 " .set noat \n" \ 1590 " move $1, %0 \n" \ 1591 " # wrdsp $1, %x1 \n" \ 1592 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1593 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1594 " .set pop \n" \ 1595 : \ 1596 : "r" (val), "i" (mask)); \ 1597} while (0) 1598 1599#define _umips_dsp_mfxxx(ins) \ 1600({ \ 1601 unsigned long __treg; \ 1602 \ 1603 __asm__ __volatile__( \ 1604 " .set push \n" \ 1605 " .set noat \n" \ 1606 " .hword 0x0001 \n" \ 1607 " .hword %x1 \n" \ 1608 " move %0, $1 \n" \ 1609 " .set pop \n" \ 1610 : "=r" (__treg) \ 1611 : "i" (ins)); \ 1612 __treg; \ 1613}) 1614 1615#define _umips_dsp_mtxxx(val, ins) \ 1616do { \ 1617 __asm__ __volatile__( \ 1618 " .set push \n" \ 1619 " .set noat \n" \ 1620 " move $1, %0 \n" \ 1621 " .hword 0x0001 \n" \ 1622 " .hword %x1 \n" \ 1623 " .set pop \n" \ 1624 : \ 1625 : "r" (val), "i" (ins)); \ 1626} while (0) 1627 1628#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1629#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1630 1631#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1632#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1633 1634#define mflo0() _umips_dsp_mflo(0) 1635#define mflo1() _umips_dsp_mflo(1) 1636#define mflo2() _umips_dsp_mflo(2) 1637#define mflo3() _umips_dsp_mflo(3) 1638 1639#define mfhi0() _umips_dsp_mfhi(0) 1640#define mfhi1() _umips_dsp_mfhi(1) 1641#define mfhi2() _umips_dsp_mfhi(2) 1642#define mfhi3() _umips_dsp_mfhi(3) 1643 1644#define mtlo0(x) _umips_dsp_mtlo(x, 0) 1645#define mtlo1(x) _umips_dsp_mtlo(x, 1) 1646#define mtlo2(x) _umips_dsp_mtlo(x, 2) 1647#define mtlo3(x) _umips_dsp_mtlo(x, 3) 1648 1649#define mthi0(x) _umips_dsp_mthi(x, 0) 1650#define mthi1(x) _umips_dsp_mthi(x, 1) 1651#define mthi2(x) _umips_dsp_mthi(x, 2) 1652#define mthi3(x) _umips_dsp_mthi(x, 3) 1653 1654#else /* !CONFIG_CPU_MICROMIPS */ 1655#define rddsp(mask) \ 1656({ \ 1657 unsigned int __res; \ 1658 \ 1659 __asm__ __volatile__( \ 1660 " .set push \n" \ 1661 " .set noat \n" \ 1662 " # rddsp $1, %x1 \n" \ 1663 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1664 " move %0, $1 \n" \ 1665 " .set pop \n" \ 1666 : "=r" (__res) \ 1667 : "i" (mask)); \ 1668 __res; \ 1669}) 1670 1671#define wrdsp(val, mask) \ 1672do { \ 1673 __asm__ __volatile__( \ 1674 " .set push \n" \ 1675 " .set noat \n" \ 1676 " move $1, %0 \n" \ 1677 " # wrdsp $1, %x1 \n" \ 1678 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1679 " .set pop \n" \ 1680 : \ 1681 : "r" (val), "i" (mask)); \ 1682} while (0) 1683 1684#define _dsp_mfxxx(ins) \ 1685({ \ 1686 unsigned long __treg; \ 1687 \ 1688 __asm__ __volatile__( \ 1689 " .set push \n" \ 1690 " .set noat \n" \ 1691 " .word (0x00000810 | %1) \n" \ 1692 " move %0, $1 \n" \ 1693 " .set pop \n" \ 1694 : "=r" (__treg) \ 1695 : "i" (ins)); \ 1696 __treg; \ 1697}) 1698 1699#define _dsp_mtxxx(val, ins) \ 1700do { \ 1701 __asm__ __volatile__( \ 1702 " .set push \n" \ 1703 " .set noat \n" \ 1704 " move $1, %0 \n" \ 1705 " .word (0x00200011 | %1) \n" \ 1706 " .set pop \n" \ 1707 : \ 1708 : "r" (val), "i" (ins)); \ 1709} while (0) 1710 1711#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1712#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1713 1714#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1715#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1716 1717#define mflo0() _dsp_mflo(0) 1718#define mflo1() _dsp_mflo(1) 1719#define mflo2() _dsp_mflo(2) 1720#define mflo3() _dsp_mflo(3) 1721 1722#define mfhi0() _dsp_mfhi(0) 1723#define mfhi1() _dsp_mfhi(1) 1724#define mfhi2() _dsp_mfhi(2) 1725#define mfhi3() _dsp_mfhi(3) 1726 1727#define mtlo0(x) _dsp_mtlo(x, 0) 1728#define mtlo1(x) _dsp_mtlo(x, 1) 1729#define mtlo2(x) _dsp_mtlo(x, 2) 1730#define mtlo3(x) _dsp_mtlo(x, 3) 1731 1732#define mthi0(x) _dsp_mthi(x, 0) 1733#define mthi1(x) _dsp_mthi(x, 1) 1734#define mthi2(x) _dsp_mthi(x, 2) 1735#define mthi3(x) _dsp_mthi(x, 3) 1736 1737#endif /* CONFIG_CPU_MICROMIPS */ 1738#endif 1739 1740/* 1741 * TLB operations. 1742 * 1743 * It is responsibility of the caller to take care of any TLB hazards. 1744 */ 1745static inline void tlb_probe(void) 1746{ 1747 __asm__ __volatile__( 1748 ".set noreorder\n\t" 1749 "tlbp\n\t" 1750 ".set reorder"); 1751} 1752 1753static inline void tlb_read(void) 1754{ 1755#if MIPS34K_MISSED_ITLB_WAR 1756 int res = 0; 1757 1758 __asm__ __volatile__( 1759 " .set push \n" 1760 " .set noreorder \n" 1761 " .set noat \n" 1762 " .set mips32r2 \n" 1763 " .word 0x41610001 # dvpe $1 \n" 1764 " move %0, $1 \n" 1765 " ehb \n" 1766 " .set pop \n" 1767 : "=r" (res)); 1768 1769 instruction_hazard(); 1770#endif 1771 1772 __asm__ __volatile__( 1773 ".set noreorder\n\t" 1774 "tlbr\n\t" 1775 ".set reorder"); 1776 1777#if MIPS34K_MISSED_ITLB_WAR 1778 if ((res & _ULCAST_(1))) 1779 __asm__ __volatile__( 1780 " .set push \n" 1781 " .set noreorder \n" 1782 " .set noat \n" 1783 " .set mips32r2 \n" 1784 " .word 0x41600021 # evpe \n" 1785 " ehb \n" 1786 " .set pop \n"); 1787#endif 1788} 1789 1790static inline void tlb_write_indexed(void) 1791{ 1792 __asm__ __volatile__( 1793 ".set noreorder\n\t" 1794 "tlbwi\n\t" 1795 ".set reorder"); 1796} 1797 1798static inline void tlb_write_random(void) 1799{ 1800 __asm__ __volatile__( 1801 ".set noreorder\n\t" 1802 "tlbwr\n\t" 1803 ".set reorder"); 1804} 1805 1806/* 1807 * Manipulate bits in a c0 register. 1808 */ 1809#define __BUILD_SET_C0(name) \ 1810static inline unsigned int \ 1811set_c0_##name(unsigned int set) \ 1812{ \ 1813 unsigned int res, new; \ 1814 \ 1815 res = read_c0_##name(); \ 1816 new = res | set; \ 1817 write_c0_##name(new); \ 1818 \ 1819 return res; \ 1820} \ 1821 \ 1822static inline unsigned int \ 1823clear_c0_##name(unsigned int clear) \ 1824{ \ 1825 unsigned int res, new; \ 1826 \ 1827 res = read_c0_##name(); \ 1828 new = res & ~clear; \ 1829 write_c0_##name(new); \ 1830 \ 1831 return res; \ 1832} \ 1833 \ 1834static inline unsigned int \ 1835change_c0_##name(unsigned int change, unsigned int val) \ 1836{ \ 1837 unsigned int res, new; \ 1838 \ 1839 res = read_c0_##name(); \ 1840 new = res & ~change; \ 1841 new |= (val & change); \ 1842 write_c0_##name(new); \ 1843 \ 1844 return res; \ 1845} 1846 1847__BUILD_SET_C0(status) 1848__BUILD_SET_C0(cause) 1849__BUILD_SET_C0(config) 1850__BUILD_SET_C0(config5) 1851__BUILD_SET_C0(intcontrol) 1852__BUILD_SET_C0(intctl) 1853__BUILD_SET_C0(srsmap) 1854__BUILD_SET_C0(brcm_config_0) 1855__BUILD_SET_C0(brcm_bus_pll) 1856__BUILD_SET_C0(brcm_reset) 1857__BUILD_SET_C0(brcm_cmt_intr) 1858__BUILD_SET_C0(brcm_cmt_ctrl) 1859__BUILD_SET_C0(brcm_config) 1860__BUILD_SET_C0(brcm_mode) 1861 1862/* 1863 * Return low 10 bits of ebase. 1864 * Note that under KVM (MIPSVZ) this returns vcpu id. 1865 */ 1866static inline unsigned int get_ebase_cpunum(void) 1867{ 1868 return read_c0_ebase() & 0x3ff; 1869} 1870 1871#endif /* !__ASSEMBLY__ */ 1872 1873#endif /* _ASM_MIPSREGS_H */ 1874